Low density parity check encoder having length of 16200 and code rate of 4/15, and low density parity check encoding method using the same

Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Claims

1. A low density parity check (LDPC) decoder, comprising: a receiving unit configured to receive a signal corresponding to an LDPC codeword having a length of 16200 and a code rate of 4/15, the LDPC codeword encoded using a sequence corresponding to a parity check matrix (PCM); and a decoding unit configured to restore error-corrected bits from the received signal by performing decoding corresponding to the PCM, wherein the LDPC codeword is generated by performing accumulation of at least one of bits from a first memory at parity bit addresses of a second memory using the sequence, at least a part of the first memory initialized with information bits, the second memory set to zero initially, wherein the signal corresponds to a transmission signal transmitted over a physical channel, and the LDPC codeword includes parity bits for correcting errors over the physical channel, wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 4320, a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1080, and a second parity part corresponding to an identity matrix included in the PCM and having a length of 10800, and wherein the sequence is represented by the following Sequence Table: TABLE-US-00007 Sequence Table 1st row: 19 585 710 3241 3276 3648 6345 9224 9890 10841 2nd row: 181 494 894 2562 3201 4382 5130 5308 6493 10135 3rd row: 150 569 919 1427 2347 4475 7857 8904 9903 4th row: 1005 1018 1025 2933 3280 3946 4049 4166 5209 5th row: 420 554 778 6908 7959 8344 8462 10912 11099 6th row: 231 506 859 4478 4957 7664 7731 7908 8980 7th row: 179 537 979 3717 5092 6315 6883 9353 9935 8th row: 147 205 830 3609 3720 4667 7441 10196 11809 9th row: 60 1021 1061 1554 4918 5690 6184 7986 11296 10th row: 145 719 768 2290 2919 7272 8561 9145 10233 11st row: 388 590 852 1579 1698 1974 9747 10192 10255 12nd row: 231 343 485 1546 3155 4829 7710 10394 11336 13rd row: 4381 5398 5987 9123 10365 11018 11153 14th row: 2381 5196 6613 6844 7357 8732 11082 15th row: 1730 4599 5693 6318 7626 9231 10663.

2. The LDPC decoder of claim 1, wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part, that is, 4320, by a circulant permutation matrix (CPM) size corresponding to the PCM, that is, 360, and a value obtained by dividing a length of the first parity part, that is, 1080, by the CPM size.

3. The LDPC decoder of claim 1, wherein the LDPC codeword is generated by performing the accumulation with respect to the second memory and the accumulation is performed at parity bit addresses that are updated using the sequence.

4. The LDPC decoder of claim 3, wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by the CPM size of the PCM.

5. A low density parity check (LDPC) decoding method, comprising: receiving a signal corresponding to an LDPC codeword having a length of 16200 and a code rate of 4/15, the LDPC codeword encoded using a sequence corresponding to a parity check matrix (PCM); and restoring error-corrected bits from the received signal by performing decoding corresponding to the PCM, wherein the LDPC codeword is generated by performing accumulation of at least one of bits from a first memory at parity bit addresses of a second memory using the sequence, at least a part of the first memory initialized with information bits, the second memory set to zero initially, wherein the signal corresponds to a transmission signal transmitted over a physical channel, and the LDPC codeword includes parity bits for correcting errors over the physical channel, wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 4320, a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1080, and a second parity part corresponding to an identity matrix included in the PCM and having a length of 10800, and wherein the sequence is represented by the following Sequence Table: TABLE-US-00008 Sequence Table 1st row: 19 585 710 3241 3276 3648 6345 9224 9890 10841 2nd row: 181 494 894 2562 3201 4382 5130 5308 6493 10135 3rd row: 150 569 919 1427 2347 4475 7857 8904 9903 4th row: 1005 1018 1025 2933 3280 3946 4049 4166 5209 5th row: 420 554 778 6908 7959 8344 8462 10912 11099 6th row: 231 506 859 4478 4957 7664 7731 7908 8980 7th row: 179 537 979 3717 5092 6315 6883 9353 9935 8th row: 147 205 830 3609 3720 4667 7441 10196 11809 9th row: 60 1021 1061 1554 4918 5690 6184 7986 11296 10th row: 145 719 768 2290 2919 7272 8561 9145 10233 11st row: 388 590 852 1579 1698 1974 9747 10192 10255 12nd row: 231 343 485 1546 3155 4829 7710 10394 11336 13rd row: 4381 5398 5987 9123 10365 11018 11153 14th row: 2381 5196 6613 6844 7357 8732 11082 15th row: 1730 4599 5693 6318 7626 9231 10663.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

(2) FIG. 1 is a block diagram illustrating a broadcast signal transmission and reception system according to an embodiment of the present invention;

(3) FIG. 2 is an operation flowchart illustrating a broadcast signal transmission and reception method according to an embodiment of the present invention;

(4) FIG. 3 is a diagram illustrating the structure of a PCM corresponding to an LDPC code to according to an embodiment of the present invention;

(5) FIG. 4 is a block diagram illustrating an LDPC encoder according to an embodiment of the present invention:

(6) FIG. 5 is a block diagram illustrating an LDPC decoder according to an embodiment of the present invention;

(7) FIG. 6 is an operation flowchart illustrating an LDPC encoding method according to an embodiment of the present invention; and

(8) FIG. 7 is a graph plotting the performance of a QC-LDPC code having a length of 16200 and a code rate of 4/15 according to an embodiment of the present invention against E.sub.b/N.sub.o.

DETAILED DESCRIPTION

(9) Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Repeated descriptions and descriptions of well-known functions and configurations that have been deemed to make the gist of the present invention unnecessarily obscure will be omitted below. The embodiments of the present invention are intended to fully describe the present invention to persons having ordinary knowledge in the art to which the present invention pertains. Accordingly, the shapes, sizes, etc. of components in the drawings may be exaggerated to make the description obvious.

(10) Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

(11) FIG. 1 is a block diagram illustrating a broadcast signal transmission and reception system according to an embodiment of the present invention.

(12) Referring to FIG. 1, it can be seen that a transmitter 10 and a receiver 30 communicate with each other over a wireless channel 20.

(13) The transmitter 10 generates an n-bit codeword by encoding k information bits using an LDPC encoder 13. The codeword is modulated by the modulator 15, and is transmitted via an antenna 17. The signal transmitted via the wireless channel 20 is received via the antenna 31 of the receiver 30, and, in the receiver 30, is subjected to a process reverse to the process in the transmitter 10. That is, the received data is demodulated by a demodulator 33, and is then decoded by an LDPC decoder 35, thereby finally restoring the information bits.

(14) It will be apparent to those skilled in the art that the above-described transmission and reception processes have been described within a minimum range required for a description of the features of the present invention and various processes required for data transmission may be added.

(15) In the following, the specific processes of encoding and decoding that are performed using an LDPC code in the LDPC encoder 13 or LDPC decoder 35 and the specific configurations of encoding and decoding devices, such as the LDPC encoder 13 and the LDPC decoder 35, are described. The LDPC encoder 13 illustrated in FIG. 1 may have a structure illustrated in FIG. 4, and the LDPC decoder 35 may have a structure illustrated in FIG. 5.

(16) FIG. 2 is an operation flowchart illustrating a broadcast signal transmission and reception method according to an embodiment of the present invention.

(17) Referring to FIG. 2, in the broadcast signal transmission and reception method according to this embodiment of the present invention, input bits (information bits) are subjected to LDPC encoding at step S210.

(18) That is, at step S210, an n-bit codeword is generated by encoding k information bits using the LDPC encoder.

(19) In this case, step S210 may be performed as in an LDPC encoding method illustrated in FIG. 6.

(20) Furthermore, in the broadcast signal transmission and reception method, the encoded data is modulated at step S220.

(21) That is, at step S220, the encoded n-bit codeword is modulated using the modulator.

(22) Furthermore, in the broadcast signal transmission and reception method, the modulated data is transmitted at step S230.

(23) That is, at step S230, the modulated codeword is transmitted over a wireless channel via the antenna.

(24) Furthermore, in the broadcast signal transmission and reception method, the received data is demodulated at step S240.

(25) That is, at step S240, the signal transmitted over the wireless channel is received via the antenna of the receiver, and the received data is demodulated using the demodulator.

(26) Furthermore, in the broadcast signal transmission and reception method, the demodulated data is subjected to LDPC decoding at step S250.

(27) That is, at step S250, the information bits are finally restored by performing LDPC decoding using the demodulator of the receiver.

(28) In this case, step S250 corresponds to a process reverse to that of the LDPC encoding method illustrated in FIG. 6, and may correspond to the LDPC decoder of FIG. 5.

(29) An LDPC code is known as a code very close to the Shannon limit for an additive white Gaussian noise (AWGN) channel, and has the advantages of asymptotically excellent performance and parallelizable decoding compared to a turbo code.

(30) Generally, an LDPC code is defined by a low-density parity check matrix (PCM) that is randomly generated. However, a randomly generated LDPC code requires a large amount of memory to store a PCM, and requires a lot of time to access memory. In order to overcome these problems, a quasi-cyclic LDPC (QC-LDPC) code has been proposed. A QC-LDPC code that is composed of a zero matrix or a circulant permutation matrix (CPM) is defined by a PCM that is expressed by the following Equation 1:

(31) $\begin{array}{cc}H=\left[\begin{array}{cccc}{J}^{a_{11}}& J^{a_{12}}& \mathrm{.Math.}& J^{a_{1n}}\\ J^{a_{21}}& J^{a_{22}}& \mathrm{.Math.}& J^{a_{2n}}\\ \mathrm{.Math.}& \mathrm{.Math.}& \ddots & \mathrm{.Math.}\\ J^{a_{m1}}& J^{a_{m2}}& \mathrm{.Math.}& J^{a_{\mathrm{mn}}}\end{array}\right],\mathrm{for}{a}_{\mathrm{ij}}\in \left\{0,1,\mathrm{.Math.},L-1,\infty \right)& \left(1\right)\end{array}$

(32) In this equation, J is a CPM having a size of L×L, and is given as the following Equation 2. In the following description, L may be 360.

(33) $\begin{array}{cc}{J}_{L\times L}=\left[\begin{array}{ccccc}0& 1& 0& \mathrm{.Math.}& 0\\ 0& 0& 1& \mathrm{.Math.}& 0\\ \mathrm{.Math.}& \mathrm{.Math.}& \mathrm{.Math.}& \ddots & \mathrm{.Math.}\\ 0& 0& 0& \mathrm{.Math.}& 1\\ 1& 0& 0& \mathrm{.Math.}& 0\end{array}\right]& \left(2\right)\end{array}$

(34) Furthermore, J.sup.i is obtained by shifting an L×L identity matrix I (J.sup.0) to the right i (0≤i≤L) times, and J.sup.∞ is an L×L zero matrix. Accordingly, in the case of a QC-LDPC code, it is sufficient if only index exponent i is stored in order to store J′, and thus the amount of memory required to store a PCM is considerably reduced.

(35) FIG. 3 is a diagram illustrating the structure of a PCM corresponding to an LDPC code to according to an embodiment of the present invention.

(36) Referring to FIG. 3, the sizes of matrices A and C are g×K and (N−K−g)×(K+g), respectively, and are composed of an L×L zero matrix and a CPM, respectively. Furthermore, matrix Z is a zero matrix having a size of g×(N−K−g), matrix D is an identity matrix having a size of (N−K−g)×(N−K−g), and matrix B is a dual diagonal matrix having a size of g×g. In this case, the matrix B may be a matrix in which all elements except elements along a diagonal line and neighboring elements below the diagonal line are 0, and may be defined as the following Equation 3:

(37) $\begin{array}{cc}{B}_{g\times g}=\left[\begin{array}{ccccccc}{I}_{L\times L}& 0& 0& \mathrm{.Math.}& 0& 0& 0\\ I_{L\times L}& I_{L\times L}& 0& \mathrm{.Math.}& 0& 0& 0\\ 0& I_{L\times L}& I_{L\times L}& \mathrm{.Math.}& 0& 0& 0\\ \mathrm{.Math.}& \mathrm{.Math.}& \mathrm{.Math.}& \ddots & \mathrm{.Math.}& \mathrm{.Math.}& \mathrm{.Math.}\\ 0& 0& 0& \mathrm{.Math.}& I_{L\times L}& I_{L\times L}& 0\\ 0& 0& 0& \mathrm{.Math.}& 0& I_{L\times L}& I_{L\times L}\end{array}\right]& \left(3\right)\end{array}$
where I.sub.L×L is an identity matrix having a size of L×L.

(38) That is, the matrix B may be a bit-wise dual diagonal matrix, or may be a block-wise dual diagonal matrix having identity matrices as its blocks, as indicated by Equation 3. The bit-wise dual diagonal matrix is disclosed in detail in Korean Patent Application Publication No. 2007-0058438, etc.

(39) In particular, it will be apparent to those skilled in the art that when the matrix B is a bit-wise dual diagonal matrix, it is possible to perform conversion into a Quasi-cyclic form by applying row or column permutation to a PCM including the matrix B and having a structure illustrated in FIG. 3.

(40) In this case, N is the length of a codeword, and K is the length of information.

(41) The present invention proposes a newly designed QC-LDPC code in which the code rate thereof is 4/15 and the length of a codeword is 16200, as illustrated in the following Table 1. That is, the present invention proposes an LDPC code that is designed to receive information having a length of 4320 and generate an LDPC codeword having a length of 16200.

(42) Table 1 illustrates the sizes of the matrices A, B, C, D and Z of the QC-LDPC code according to the present invention:

(43) TABLE-US-00002 TABLE 1 Sizes Code rate Length A B C D Z 4/15 16200 1080 × 4320 1080 × 1080 10800 × 5400 10800 × 10800 1080 × 10800

(44) The newly designed LDPC code may be represented in the form of a sequence (progression), an equivalent relationship is established between the sequence and matrix (parity bit check matrix), and the sequence may be represented, as follows:

(45) TABLE-US-00003 Sequence Table 1st row: 19 585 710 3241 3276 3648 6345 9224 9890 10841 2nd row: 181 494 894 2562 3201 4382 5130 5308 6493 10135 3rd row: 150 569 919 1427 2347 4475 7857 8904 9903 4th row: 1005 1018 1025 2933 3280 3946 4049 4166 5209 5th row: 420 554 778 6908 7959 8344 8462 10912 11099 6th row: 231 506 859 4478 4957 7664 7731 7908 8980 7th row: 179 537 979 3717 5092 6315 6883 9353 9935 8th row: 147 205 830 3609 3720 4667 7441 10196 11809 9th row: 60 1021 1061 1554 4918 5690 6184 7986 11296 10th row: 145 719 768 2290 2919 7272 8561 9145 10233 11st row: 388 590 852 1579 1698 1974 9747 10192 10255 12nd row: 231 343 485 1546 3155 4829 7710 10394 11336 13rd row: 4381 5398 5987 9123 10365 11018 11153 14th row: 2381 5196 6613 6844 7357 8732 11082 15th row: 1730 4599 5693 6318 7626 9231 10663

(46) An LDPC code that is represented in the form of a sequence is being widely used in the DVB standard.

(47) According to an embodiment of the present invention, an LDPC code presented in the form of a sequence is encoded, as follows. It is assumed that there is an information block S=(s.sub.0, s.sub.1, . . . , s.sub.K−1) having an information size K. The LDPC encoder generates a codeword Λ=(λ.sub.0, λ.sub.1, λ.sub.2, . . . , λ.sub.N−1) having a size of N=K+M.sub.1+M.sub.2 using the information block S having a size K. In this case, M.sub.1=g, and M.sub.2=N−K−g. Furthermore, M.sub.1 is the size of parity bits corresponding to the dual diagonal matrix B, and M.sub.2 is the size of parity bits corresponding to the identity matrix D. The encoding process is performed, as follows:

(48) Initialization:
λ.sub.i=s.sub.i for i=0,1, . . . ,K−1
p.sub.j=0for j=0,1, . . . ,M.sub.1+M.sub.2−1  (4)

(49) First information bit λ.sub.0 is accumulated at parity bit addresses specified in the 1st row of the sequence of the Sequence Table. For example, in an LDPC code having a length of 16200 and a code rate of 4/15, an accumulation process is as follows:

(50) TABLE-US-00004 p.sub.19 = p.sub.19 ⊕ λ.sub.0 p.sub.585 = p.sub.585 ⊕ λ.sub.0 p.sub.710 = p.sub.710 ⊕ λ.sub.0 p.sub.3241 = p.sub.3241 ⊕ λ.sub.0 p.sub.3276 = p.sub.3276 ⊕ λ.sub.0 p.sub.3648 = p.sub.3648 ⊕ λ.sub.0 p.sub.6345 = p.sub.6345 ⊕ λ.sub.0 p.sub.9224 = p.sub.9224 ⊕ λ.sub.0 p.sub.9890 = p.sub.9890 ⊕ λ.sub.0 p.sub.10841 = p.sub.10841 ⊕ λ.sub.0
where the addition ⊕ occurs in GF(2).

(51) The subsequent L−1 information bits, that is, λ.sub.m, m=1, 2, . . . , L−1, are accumulated at parity bit addresses that are calculated by the following Equation 5:
(x+m×Q.sub.1)mod M.sub.1 if x<M.sub.1
M.sub.1+{(x−M.sub.1+m×Q.sub.2)mod M.sub.2} if x≥M.sub.1  (5)
where x denotes the addresses of parity bits corresponding to the first information bit λ.sub.0, that is, the addresses of the parity bits specified in the first row of the sequence of the Sequence Table, Q.sub.1=M.sub.1/L, Q.sub.2=M.sub.2/L, and L=360. Furthermore, Q.sub.1 and Q.sub.2 are defined in the following Table 2. For example, for an LDPC code having a length of 16200 and a code rate of 4/15, M.sub.1=1080, Q.sub.1=3, M.sub.2=10800, Q.sub.2=30 and L=360, and the following operations are performed on the second bit λ.sub.1 using Equation 5:

(52) TABLE-US-00005 p.sub.22 = p.sub.22 ⊕ λ.sub.1 p.sub.588 = p.sub.588 ⊕ λ.sub.1 p.sub.713 = p.sub.713 ⊕ λ.sub.1 p.sub.3271 = p.sub.3271 ⊕ λ.sub.1 p.sub.3306 = p.sub.3306 ⊕ λ.sub.1 p.sub.3678 = p.sub.3678 ⊕ λ.sub.1 p.sub.6375 = p.sub.6375 ⊕ λ.sub.1 p.sub.9254 = p.sub.9254 ⊕ λ.sub.1 p.sub.9920 = p.sub.9920 ⊕ λ.sub.1 p.sub.10871 = p.sub.10871 ⊕ λ.sub.1

(53) Table 2 illustrates the sizes of M.sub.1, Q.sub.1, M.sub.2 and Q.sub.2 of the designed QC-LDPC code:

(54) TABLE-US-00006 TABLE 2 Sizes Code rate Length M.sub.1 M.sub.2 Q.sub.1 Q.sub.2 4/15 16200 1080 10800 3 30

(55) The addresses of parity bit accumulators for new 360 information bits from λ.sub.L to λ.sub.2L-1 are calculated and accumulated from Equation 5 using the second row of the sequence.

(56) In a similar manner, for all groups composed of new L information bits, the addresses of parity bit accumulators are calculated and accumulated from Equation 5 using new rows of the sequence.

(57) After all the information bits from λ0 to λ.sub.K−1 have been exhausted, the operations of the following Equation 6 are sequentially performed from i=1:
p.sub.i=p.sub.i⊕p.sub.i-1 for i=0,1, . . . ,M.sub.1−1  (6)

(58) Thereafter, when a parity interleaving operation, such as that of the following Equation 7, is performed, parity bits corresponding to the dual diagonal matrix B are generated:
λ.sub.K+L.Math.t+s=p.sub.Q.sub.1.sub..Math.s+t for 0≤s≤L, 0≤t<Q.sub.1   (7)

(59) When the parity bits corresponding to the dual diagonal matrix B have been generated using K information bits λ0, λ1, . . . , λ.sub.K−1, parity bits corresponding to the identity matrix D are generated using the M.sub.1 generated parity bits λ.sub.K, λ.sub.K+1, . . . , λ.sub.K+M.sub.1.sub.−1.

(60) For all groups composed of L information bits from λ.sub.K to λ.sub.K+M.sub.1.sub.−1, the addresses of parity bit accumulators are calculated using the new rows (starting with a row immediately subsequent to the last row used when the parity bits corresponding to the dual diagonal matrix B have been generated) of the sequence and Equation 5, and related operations are performed.

(61) When a parity interleaving operation, such as that of the following Equation 8, is performed after all the information bits from λ.sub.K to λ.sub.K+M.sub.1.sub.−1 have been exhausted, parity bits corresponding to the identity matrix D are generated:
λ.sub.K+M.sub.1.sub.+L.Math.t+s=p.sub.M.sub.1.sub.+Q.sub.2.sub..Math.s+t for 0≤s<L, 0≤t<Q.sub.2   (8)

(62) FIG. 4 is a block diagram illustrating an LDPC encoder according to an embodiment of the present invention.

(63) Referring to FIG. 4, the LDPC encoder according to this embodiment of the present invention includes memory 310 and 320 and a processor 330.

(64) The memory 310 is memory that is used to store an LDPC codeword having a length of 16200 and a code rate of 4/15.

(65) The memory 320 is memory that is initialized to 0.

(66) The memory 310 and the memory 320 may correspond to λi (i=0, 1, . . . , N−1) and p.sub.j (j=0, 1, . . . , M.sub.1+M.sub.2−1), respectively.

(67) The memory 310 and the memory 320 may correspond to various types of hardware for storing sets of bits, and may correspond to data structures, such as an array, a list, a stack and a queue.

(68) The processor 330 generates an LDPC codeword corresponding to information bits by performing accumulation with respect to the memory 320 using a sequence corresponding to a PCM.

(69) In this case, the accumulation may be performed at parity bit addresses that are updated using the sequence of the above Sequence Table.

(70) In this case, the LDPC codeword may include a systematic part λ.sub.0, λ.sub.1, . . . , λ.sub.K−1 corresponding to the information bits and having a length of 4320 (=K), a first parity part λ.sub.K, λ.sub.K+1, . . . , λ.sub.K+M.sub.1.sub.−1 corresponding to a dual diagonal matrix included in the PCM and having a length of 1080 (=M.sub.1=g), and a second parity part λ.sub.K+M.sub.1, λ.sub.K+M.sub.1.sub.+1, . . . , λ.sub.K+M.sub.1.sub.+M.sub.2.sub.−1 corresponding to an identity matrix included in the PCM and having a length of 10800 (=M.sub.2).

(71) In this case, the sequence may have a number of rows equal to the sum (4320/360+1080/360=15) of a value obtained by dividing the length of the systematic part, that is, 4320, by a CPM size L corresponding to the PCM, that is, 360, and a value obtained by dividing the length M.sub.1 of the first parity part, that is, 1080, by 360.

(72) As described above, the sequence may be represented by the above Sequence Table.

(73) In this case, the memory 320 may have a size corresponding to the sum M.sub.1+M.sub.2 of the length M.sub.1 of the first parity part and the length M.sub.2 of the second parity part.

(74) In this case, the parity bit addresses may be updated based on the results of comparing each x of the previous parity bit addresses specified in respective rows of the sequence with the length M.sub.1 of the first parity part.

(75) That is, the parity bit addresses may be updated using Equation 5. In this case, x may be the previous parity bit addresses, m may be an information bit index that is an integer larger than 0 and smaller than L, L may be the CPM size of the PCM, Q.sub.1 may be M.sub.1/L, M.sub.1 may be the size of the first parity part, Q.sub.2 may be M.sub.2/L, and M.sub.2 may be the size of the second parity part.

(76) In this case, it may be possible to perform the accumulation while repeatedly changing the rows of the sequence by the CPM size L (=360) of the PCM, as described above.

(77) In this case, the first parity part λ.sub.K, λ.sub.K+1, . . . , λ.sub.K+M.sub.1.sub.−1 may be generated by performing parity interleaving using the memory 310 and the memory 320, as described in conjunction with Equation 7.

(78) In this case, the second parity part λ.sub.K+M.sub.1, λ.sub.K+M.sub.1.sub.+1, . . . , λ.sub.K+M.sub.1.sub.+M.sub.2.sub.−1 may be generated by performing parity interleaving using the memory 310 and the memory 320 after generating the first parity part λ.sub.K, λ.sub.K+1, . . . , λ.sub.K+M.sub.1.sub.−1 and then performing the accumulation using the first parity part λ.sub.K, λ.sub.K+1, . . . , λ.sub.K+M.sub.1.sub.−1 and the sequence, as described in conjunction with Equation 8.

(79) FIG. 5 is a block diagram illustrating an LDPC decoder according to an embodiment of the present invention.

(80) Referring to FIG. 5, the LDPC decoder according to this embodiment of the present invention may include a receiving unit 410 and a decoding unit 420.

(81) The receiving unit 410 receives an LDPC codeword that has been encoded using a sequence that corresponds to a PCM and is represented by the above Sequence Table.

(82) The decoding unit 420 restores information bits from the received LDPC codeword by performing decoding corresponding to the PCM.

(83) In this case, the sequence may be used to update the parity bit addresses of the memory, and the parity bit addresses are used for accumulation that is performed to generate parity bits corresponding to the LDPC codeword.

(84) In this case, the LDPC codeword may include a systematic part λ.sub.0, λ.sub.1, . . . , λ.sub.K−1 corresponding to the information bits, a first parity part λ.sub.K, λ.sub.K+1, . . . , λ.sub.K+M.sub.1.sub.−1 corresponding to a dual diagonal matrix included in the PCM, and a second parity part λ.sub.K+M.sub.1, λ.sub.K+M.sub.1.sub.+1, . . . , λ.sub.K+M.sub.1.sub.+M.sub.2.sub.−1 corresponding to an identity matrix included in the PCM.

(85) In this case, the parity bit addresses may be updated based on the results of comparing each x of the previous parity bit addresses specified in respective rows of the sequence with the length M.sub.1 of the first parity part.

(86) That is, the parity bit addresses may be updated using Equation 5. In this case, x may be the previous parity bit addresses, m may be an information bit index that is an integer larger than 0 and smaller than L, L may be the CPM size of the PCM, Q.sub.1 may be M.sub.1/L, M.sub.1 may be the size of the first parity part, Q.sub.2 may be M.sub.2/L, and M.sub.2 may be the size of the second parity part.

(87) FIG. 6 is an operation flowchart illustrating an LDPC encoding method according to an embodiment of the present invention.

(88) Referring to FIG. 6, the LDPC encoding method according to this embodiment of the present invention initializes the first memory that stores an LDPC codeword having a length of 16200 and a code rate of 4/15, and second memory at step S510.

(89) In this case, step S510 may be performed using Equation 4.

(90) Furthermore, in the LDPC encoding method according to this embodiment of the present invention, an LDPC codeword corresponding to information bits is generated by performing accumulation with respect to the second memory using a sequence corresponding to a PCM at step S520.

(91) In this case, the accumulation may be performed at parity bit addresses that are updated using the sequence corresponding to the PCM.

(92) In this case, the LDPC codeword may include a systematic part λ.sub.0, λ.sub.1, . . . , λ.sub.K−1 corresponding to the information bits and having a length of 4320 (=K), a first parity part λ.sub.K, λ.sub.K+1, . . . , λ.sub.K+M.sub.1.sub.−1 corresponding to a dual diagonal matrix included in the PCM and having a length of 1080 (=M.sub.1=g), and a second parity part λ.sub.K+M.sub.1, λ.sub.K+M.sub.1.sub.+1, . . . , λ.sub.K+M.sub.1.sub.+M.sub.2.sub.−1 corresponding to an identity matrix included in the PCM and having a length of 10800 (=M.sub.2).

(93) In this case, the sequence may have a number of rows equal to the sum (4320/360+1080/360=15) of a value obtained by dividing the length of the systematic part, that is, 4320, by a CPM size L corresponding to the PCM, that is, 360, and a value obtained by dividing the length M.sub.1 of the first parity part, that is, 1080, by 360.

(94) As described above, the sequence may be represented by the above Sequence Table.

(95) In this case, the parity bit addresses may be updated based on the results of comparing each x of the previous parity bit addresses specified in respective rows of the sequence with the length M.sub.1 of the first parity part.

(96) That is, the parity bit addresses may be updated using Equation 5. In this case, x may be the previous parity bit addresses, m may be an information bit index that is an integer larger than 0 and smaller than L, L may be the CPM size of the PCM, Q.sub.1 may be M.sub.1/L, M.sub.1 may be the size of the first parity part, Q.sub.2 may be M.sub.2/L, and M.sub.2 may be the size of the second parity part.

(97) In this case, it may be possible to perform the accumulation while repeatedly changing the rows of the sequence by the CPM size L (=360) of the PCM, as described above.

(98) In this case, the first parity part λ.sub.K, λ.sub.K+1, . . . , λ.sub.K+M.sub.1.sub.−1 may be generated by performing parity interleaving using the memory 310 and the memory 320, as described in conjunction with Equation 7.

(99) In this case, the second parity part λ.sub.K+M.sub.1, λ.sub.K+M.sub.1.sub.+1, . . . , λ.sub.K+M.sub.1.sub.+M.sub.2.sub.−1 may be generated by performing parity interleaving using the memory 310 and the memory 320 after generating the first parity part λ.sub.K, λ.sub.K+1, . . . , λ.sub.K+M.sub.1.sub.−1 and then performing the accumulation using the first parity part λ.sub.K, λ.sub.K+1, . . . , λ.sub.K+M.sub.1.sub.−1 and the sequence, as described in conjunction with Equation 8.

(100) FIG. 7 is a graph plotting the performance of a QC-LDPC code having a length of 16200 and a code rate of 4/15 according to an embodiment of the present invention against E.sub.b/N.sub.o.

(101) The graph illustrated in FIG. 7 illustrates results that were obtained on the assumption that a log-likelihood ratio (LLR)-based sum-product algorithm in which binary phase shift keying (BPSK) modulation and 50 rounds of repetitive decoding were performed was used for computational experiments. As illustrated in FIG. 7, it can be seen that the designed code is away from the Shannon limit by about 1.1 dB at BER=10.sup.−6.

(102) At least one embodiment of the present invention has the advantage of providing a new LDPC codeword having a length of 16200 and a code rate of 4/15, which is capable of being used for general purposes.

(103) At least one embodiment of the present invention has the advantage of providing an LDPC encoding technique that is capable of efficiently performing LDPC encoding using a sequence having a number of rows equal to a value that is obtained by dividing the sum of the length of the systematic part of an LDPC codeword, that is, 4320, and the length of the first parity part of the LDPC codeword, that is, 1080, by 360.

(104) Although the specific embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible without departing from the scope and spirit of the invention as disclosed in the accompanying claims.