Charge pump circuit and method for voltage conversion

Abstract

An inverter circuit arrangement that connects an IO-link master with a slave includes an AB class transistor circuit of which the currents are replicated by a current mirror to a terminal of the slave. A bias circuit provides bias voltages to the AB class transistors. A comparator forms a feedback between the master and slave terminals. The circuit provides for a bidirectional inversion to make a slave device IO-link compatible.

Claims

1. An inverter circuit arrangement, comprising: a first terminal, a second terminal, a terminal for a first supply potential and a terminal for a second supply potential; a pull-up resistor connected to the first terminal and to the terminal for the first supply potential; an AB class transistor circuit connected to the second terminal; a first current mirror having an input path connected to the terminal for the first supply potential and to one end of the AB class transistor circuit and having an output path connected to the first terminal; a second current mirror having an input path connected to the terminal for the second supply potential and to another end of the AB class transistor circuit and having an output path connected to the first terminal; a bias circuit comprising a bias current source to provide a bias current, a current mirror configured to receive the bias current and having an output path that includes a transistor of the AB class transistor circuit and having an input path that includes a diode connected to the terminal for the first supply potential and a transistor configured as a diode connected to the control terminal of the transistor of the AB class transistor circuit; another current mirror configured to receive the bias current and having an output path that includes another transistor of the AB class transistor circuit and having an input path that includes a diode connected to the terminal for the second supply potential and a transistor configured as a diode connected to the control terminal of the other transistor of the AB class transistor circuit; and a comparator connected to the first terminal having an output connected to the second terminal through a third current mirror.

2. The inverter circuit arrangement according to claim 1, further comprising a master circuit having an output terminal connected to the second terminal, the master circuit comprising a first switchable current source connected to the output terminal of the master circuit and the terminal for the second supply potential, a second current source connected to the output terminal of the master circuit and the terminal for the second supply potential and a third switchable current source connected to the output terminal of the master circuit and the terminal for the first supply potential.

3. The inverter circuit arrangement according to claim 2, further comprising a slave circuit having an output terminal connected to the first terminal, the slave circuit comprising a switchable current source connected to the terminal for the second supply potential and to the output terminal of the slave circuit.

4. The inverter circuit arrangement according to claim 3, wherein the terminal for the first supply potential is a terminal for a positive potential and the terminal for the second supply potential is a terminal for a ground potential, wherein current mirrors connected to the terminal for the positive potential include PNP transistors and current mirrors connected to the terminal for the ground potential include NPN transistors.

5. The inverter circuit arrangement according to claim 3, wherein the slave circuit includes an open collector driver transistor of which the collector is connected to the first terminal and the emitter is connected to the terminal for the second supply potential.

6. The inverter circuit arrangement according to claim 3, wherein the master circuit comprises an output stage that complies with European Norm EN 61131 part 9 and the slave circuit comprises an output stage that does not comply with European Norm EN 61131 part 9.

7. The inverter circuit arrangement according to claim 3, wherein the circuit is configured such that a current supplied by the output of the comparator is higher than the current supplied by the second current source of the master circuit and smaller than the sum of currents supplied by the first switchable current source of the master circuit and the second current source of the master circuit.

8. The inverter circuit arrangement according to claim 1, wherein the AB class transistor circuit comprises a PNP transistor and a NPN transistor, of which the emittors are connected to the second terminal.

9. The inverter circuit arrangement according to claim 1, wherein the comparator comprises a first input that is connected to a threshold voltage and a second input connected to the first terminal, wherein the output of the comparator is connected to a resistor, wherein the third current mirror comprises an input path connected to the resistor and an output path connected to the second terminal.

10. The inverter circuit arrangement according to claim 9, wherein the first input of the comparator is an inverting input that is connected to a voltage divider and the second input of the comparator is a non-inverting input connected to the first terminal.

11. The inverter circuit arrangement according to claim 1, wherein the second terminal is configured to be connected to an output terminal of a master circuit, the master circuit comprising a first switchable current source connected to the output terminal of the master circuit and the terminal for the second supply potential, a second current source connected to the output terminal of the master circuit and the terminal for the second supply potential and a third switchable current source connected to the output terminal of the master circuit and the terminal for the first supply potential.

12. The inverter circuit arrangement according to claim 11, wherein the first terminal is configured to be connected to an output terminal of a slave circuit, the slave circuit comprising a switchable current source connected to the terminal for the second supply potential and to the output terminal of the slave circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the drawings:

(2) FIG. 1 shows a top level block diagram of a circuit according to the principles of the present disclosure; and

(3) FIG. 2 shows a detailed schematic diagram of the inverter circuit connected between the slave and the master of the arrangement of FIG. 1.

DETAILED DESCRIPTION

(4) The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings showing embodiments of the disclosure. The disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will fully convey the scope of the disclosure to those skilled in the art. The drawings are not necessarily drawn to scale but are configured to clearly illustrate the disclosure.

Top Level Block Diagram

(5) The top level block diagram of FIG. 1 shows a master device 130 that includes an IO-link compatible output stage. The output terminal 131 is provided with a switchable high side current source 132 that supplies a current IQH.sub.M in response to a switching signal on/off. A low side current source 133 sinks a current ILL.sub.M from the terminal 131 to ground potential. The low side current source may be a resistor. Another switchable low side current source 134 sinks current IQL.sub.M in response to a switching signal on/off to ground potential. The switchable high side and low side current sources act in push-pull configuration and may be implemented with pnp and npn transistors, respectively.

(6) A slave device 110 may be a sensor or an actuator. The slave device 110 may particularly be a proximity sensor. The proximity sensor includes a switchable low side current source 112 connected between output 111 and ground potential. The switchable current source 112 sinks a current IQL.sub.D in response to a switching signal on/off. The low side current source may be an open collector NPN transistor of which the collector is connected to output terminal 111 and the emitter is connected to ground potential. The base of the NPN transistor is controlled on or off representing the function of the slave device. Alternatively, the low side current source may be an open drain NMOS transistor.

(7) Between terminals 111 and 131 there is provided an interface circuit 120 that matches the physical layer between the output terminals of the master 130 and the slave 110 that is between terminals 131 and 111. Interface circuit 120 is a bidirectional inverter that makes the IO-link master compatible with the slave that has a low side switch such as an open collector NPN transistor as output stage. Circuit 120 inverts the master input/output current at terminal C/Q to the terminal OUT1 for the slave input/output and at the same time limits the C/Q voltage range with class A/B transistor current comparators. These comparators switch off the appropriate current from the high side or the low side depending on the C/Q current polarity. With the correct dimensioning of the currents as explained in more detail below, the circuit is also able to override the master pull down current at terminal C/Q when terminal OUT1 is being driven low. At the idle state, the interface circuit provides a pull up resistor at the terminal OUT1 so that the terminal OUT1 is kept at a logical “1” and the master pull down current keeps the terminal C/Q at “0”.

Detailed Schematics of Inverter Circuit

(8) The detailed structure of circuit 120 is depicted in FIG. 2. The schematics of circuit 120 include a pull up resistor R.sub.3 connected to the terminal OUT1 and the terminal for the positive supply potential V.sub.supply. In an example, the positive supply potential V.sub.supply may be 24 V and the resistor R.sub.3 may be in the range of 200Ω. The terminal C/Q of circuit 120 is connected to AB class transistors Q.sub.nc2 and Q.sub.pc2. The emitter of NPN transistors Q.sub.nc2 is connected to the emitter of PNP transistor Q.sub.pc2 and to terminal C/Q. The collectors of transistors Q.sub.nc2 and Q.sub.pc2 are connected to corresponding current mirrors that replicate the current through these transistors to the terminal OUT1. Specifically, PNP transistor Q.sub.po1 is connected between the collector of NPN transistor Q.sub.nc2 and supply potential V.sub.supply. Transistor Q.sub.po1 is configured as a diode and is connected to the output path of the current mirror including PNP transistor Q.sub.po2 of which the collector is connected to the terminal OUT1. NPN transistor Q.sub.no1 is connected to the collector of PNP transistor Q.sub.pc2 and to ground potential V.sub.gnd. Transistor Q.sub.no1 is configured as a diode and replicates the current to the output path of the current mirror that includes NPN transistor Q.sub.no2 connected between the terminal OUT1 and ground potential V.sub.gnd.

(9) A bias circuit illustrated at the right-hand side of the schematic diagram includes a current source connected to supply potential V.sub.supply in the form of a resistor R.sub.b1 supplying current I.sub.b. The current I.sub.b flows through diode connected transistor Q.sub.b1 that replicates the current into a current mirror arrangement which is connected between supply potential V.sub.supply and ground potential V.sub.gnd. This current mirror arrangement includes a high side current mirror and a low side current mirror. The high side current mirror includes diode connected PNP transistor Q.sub.b4 and an output PNP transistor Q.sub.b5, both transistors connected to supply potential V.sub.supply. The low side current mirror includes NPN transistor Q.sub.b2 and NPN transistor Q.sub.b3 of which the bases are connected together and are connected to current source transistor Q.sub.b1, all transistors connected to ground potential V.sub.gnd. As a result, the current I.sub.b also flows through transistors Q.sub.b5 and Q.sub.b3.

(10) Further connected to transistor Q.sub.b5 is another current mirror including NPN transistor Q.sub.nc1 configured as a diode of which the emitter is connected through diode D.sub.1 to ground potential V.sub.gnd. The output side of this current mirror includes the high side AB class transistor Q.sub.nc2. The common bases of transistors Q.sub.nc1, Q.sub.nc2 carry bias potential V.sub.bn. At the low side portion, transistor Q.sub.b3 is connected to another current mirror including PNP transistor Q.sub.pc1 configured as a diode of which the emitter is connected through diode D.sub.2 to supply potential V.sub.supply. The output side of this current mirror includes the low side AB class transistor Q.sub.pc2. The common bases of transistors Q.sub.pc1, Q.sub.pc2 carry bias potential V.sub.bp. The bias potentials V.sub.bn, V.sub.bp are fixed at two diode voltages relative to the ground potential V.sub.gnd and the supply potential V.sub.supply, resp. The diodes D.sub.1, D.sub.2 may be omitted so that the bias voltages V.sub.bn, V.sub.bp are fixed at one diode voltage above or below potentials V.sub.gnd, V.sub.supply.

(11) A feedback path between terminals OUT1 and C/Q includes a comparator C. The non-inverting input “+” of comparator C is connected to the terminal OUT1. The inverting input “−” of comparator C is connected to a voltage divider which is connected between supply voltage V.sub.supply and ground potential V.sub.gnd. The voltage divider is symmetrical in that it includes two identical resistors R.sub.2 of which the midpoint is connected to the inverting input of comparator C. The voltage divider supplies a threshold voltage to the comparator to which the voltage at terminal OUT1 is compared. The output of comparator C is connected to a resistor R.sub.1 which is a portion of a current mirror circuit comprising diode connected PNP transistor Q.sub.d2 and output PNP transistor Q.sub.d1. The emitters of transistors Q.sub.d2, Q.sub.d1 are connected to supply potential V.sub.supply. The collector of transistor Q.sub.d1 is connected to the terminal C/Q and supplies current I.sub.d.

(12) Resistors may be provided (not shown in the drawings) between the collectors of transistors Q.sub.b4, Q.sub.b2 and between the collectors of transistors Q.sub.no1, Q.sub.pc2 and Q.sub.po1, Q.sub.nc2. These resistors reduce the respective collector voltages.

Operation of Inverter Circuit

(13) The operation of the circuit depicted in FIG. 2 is as follows. The transistor Q.sub.b1 and the resistor R.sub.b1 define the bias current I.sub.b which is used to biase the current comparators at the terminal C/Q. The current mirror formed by transistors Q.sub.b1, Q.sub.b2 and Q.sub.b3 and the current mirror formed by transistors Q.sub.b4 and Q.sub.b5 replicate this current through transistors Q.sub.pc1 and Q.sub.nc1.

(14) The current I.sub.b through diode D.sub.1 and transistor Q.sub.nc1 defines the potential V.sub.bn and the current I.sub.b through diode D.sub.2 and transistor Q.sub.pc1 defines the potential V.sub.bp. A current can flow through transistor Q.sub.nc2 only if the voltage at terminal C/Q is below V.sub.bn−Vbe.sub.nc2 (Vbe.sub.nc2: base emitter voltage of transistor Q.sub.nc2). A current can flow through transistor Q.sub.pc2 only if the voltage at terminal C/Q is above V.sub.bp+Veb.sub.pc2 (Vbe.sub.pc2: base emitter voltage of transistor Q.sub.pc2). So, no current can flow simultaneously through both transistors Q.sub.nc2 and Q.sub.pc2, achieving the class AB behavior. A quiescent current from supply to ground through these transistors is avoided.

(15) The comparator C compares the voltage at terminal OUT1 with half of the supply voltage V.sub.supply/2. If the voltage at terminal OUT1 is above this threshold, the output voltage of comparator C is set as V.sub.C=V.sub.supply so that there is no current through resistor R.sub.1. If the voltage at terminal OUT1 is below that threshold, the output voltage of comparator C is set as V.sub.C=V.sub.gnd so that the current through resistor R1 is injected at terminal C/Q by current the current mirror of transistors Q.sub.d1 and Q.sub.d2. The current through resistor R.sub.1 is
I.sub.d=(V.sub.supply−Vbe.sub.d2−V.sub.C)/R.sub.1,
when the potential at terminal OUT1 is low. The current I.sub.d=0, when the potential at terminal OUT1 is high. The function of comparator C can be summarized as follows:
OUT1=H, V.sub.C=V.sub.supply, I.sub.d=0
OUT1=L, V.sub.C=V.sub.gnd, I.sub.d=(V.sub.supply−Vbe.sub.d2−V.sub.C)/R.sub.1

(16) The IO-link master pulls down the potential at terminal C/Q with the current ILL.sub.M. At idle state, there is no other current generated by the master nor by the slave. So, the terminal C/Q is pulled down low and the current ILL.sub.M flows through transistor Q.sub.nc2. This current is replicated by current mirror of transistors Q.sub.po1 and Q.sub.po2 at the terminal OUT1 so that the potential at terminal OUT1 is pulled up. In order to avoid that terminal OUT1 floats and becomes low, current I.sub.d is injected at terminal C/Q higher than current ILL.sub.M so that the current through resistor R.sub.3 pulls up terminal OUT1 also.

(17) When the master wants to transmit a bit “1” after the idle state (start bit) or after a previous bit “0”, it pulls up terminal C/Q with current IQH.sub.M, higher than current ILL.sub.M. The differential current IQH.sub.M−ILL.sub.M flows through transistor Q.sub.pc2 and it is replicated by current mirror of transistors Q.sub.no1 and Q.sub.no2 at terminal OUT1. The differential current IQH.sub.M−ILL.sub.M must be higher than the current through resistor R.sub.3 which is V.sub.supply/R.sub.3, so that the master can turn terminal OUT1 low. When terminal OUT1 is low, the current Id is also injected at terminal C/Q, which enforces the pulling up of the terminal C/Q.

(18) When the master wants to transmit a bit “0” after a previous bit “1”, terminal C/Q is pulled down with current IQL.sub.M. Current ILL.sub.M also pulls down the terminal C/Q, while current I.sub.d pulls the terminal C/Q up. The current IQL.sub.M+ILL.sub.M−I.sub.d (higher than 0) flows through transistor Q.sub.nc2 and it is replicated by current mirror of transistors Q.sub.po1 and Q.sub.po2 at terminal OUT1 pulling up the terminal OUT1 with the help of resistor R.sub.3. At the moment when terminal OUT1 is high, current I.sub.d turns to zero and the final current through transistor Q.sub.nc2 is IQL.sub.M+ILL.sub.M.

(19) When the master stops transmitting after the stop bit, which is a bit “1”, terminal C/Q is pulled down by current ILLM. Current I.sub.d is activated as previously terminal C/Q was pulled up. As current I.sub.d is higher than current ILL.sub.M, terminal C/Q is not pulled down until terminal OUT1 is turned high by resistor R.sub.3.

(20) When the slave device wants to transmit a bit “1” at terminal C/Q after a previous idle state or previous bit “0”, the open drain NPN transistor at its output stage should be connected, pulling down terminal OUT1. Current I.sub.1 appears and terminal C/Q is pulled up as current I.sub.d is higher than current ILL.sub.M.

(21) When the slave device wants to transmit “0” at terminal C/Q from previous bit “1” or to come back to idle state, the open drain NPN transistor is disconnected and terminal OUT1 is pulled up by resistor R.sub.3. At the moment OUT1 is high, current I.sub.d is zero and current ILL.sub.M is able to pull down terminal C/Q.

(22) So, for current I.sub.d the constraint is that it should be higher than current ILL.sub.M and smaller than current IQL.sub.M+ILL.sub.M.

(23) The inverter circuit 120 inverts currents and voltages between the IO-link master and other devices that are not able to generate a high quiescent current to pull up the voltage of the signal line. With use of the inverter circuit 120 such slave devices are able to communicate using the IO-link protocol even at maximum speed.

(24) It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the disclosure as laid down in the appended claims. Since modifications, combinations, sub-combinations and variations of the disclosed embodiments incorporating the spirt and substance of the disclosure may occur to the persons skilled in the art, the disclosure should be construed to include everything within the scope of the appended claims.