VOLTAGE WAVEFORM GENERATOR FOR PLASMA ASSISTED PROCESSING APPARATUSES

Abstract

A voltage waveform generator for a plasma assisted processing apparatus includes a common node, a voltage supply circuit operable to switch between at least two voltage levels at a first switch node, a first inductor connected between the first switch node and the common node, and a control unit configured to operate the voltage supply circuit.

Claims

1. A voltage waveform generator for a plasma assisted processing apparatus, the voltage waveform generator comprising: a first switch node and a common node, a voltage supply circuit connected to the first switch node and operable to switch between at least two voltage levels at the first switch node, a first inductor connected between the first switch node and the common node, a control unit configured to operate the voltage supply circuit so as to obtain a predetermined voltage waveform at the common node, and a voltage clamping circuit coupled to the common node and operable to clamp a voltage of the common node at a predetermined level.

2. The voltage waveform generator of claim 1, wherein the control unit is configured to operate the voltage supply circuit so as to obtain a first current pulse of a first sign followed by a second current pulse of an opposite sign through the first inductor.

3. The voltage waveform generator of claim 1, wherein the control unit is configured to operate the voltage supply circuit so as to obtain at the switch node a switched voltage signal resulting in a current pulse through the first inductor allowing for obtaining the predetermined waveform at the common node.

4. The voltage waveform generator of claim 3, wherein the switched voltage signal comprises a sequence of voltage levels, wherein the sequence comprises a first voltage level having a first magnitude followed by a second voltage level having a second magnitude lower than the first magnitude followed by a third voltage level having a third magnitude higher than the second magnitude, wherein the third magnitude is equal to or different from the first magnitude.

5. The voltage waveform generator of claim 1, wherein the predetermined waveform is a voltage pulse.

6. The voltage waveform generator of claim 1, wherein the voltage supply circuit comprises a neutral-point-clamped converter operable to switch between at least three voltage levels at the first switch node.

7. (canceled)

8. (canceled)

9. The voltage waveform generator of claim 1, wherein the voltage clamping circuit is coupled to a voltage node of the voltage supply circuit, the voltage node configured for providing one of the at least two voltage levels as the predetermined level.

10. The voltage waveform generator of claim 1, wherein the voltage clamping circuit comprises one or more of: a passive clamping branch comprising one or more diodes, an active clamping branch and an electrical damping element.

11. The voltage waveform generator of claim 10, comprising the active clamping branch and the passive clamping branch, wherein the active clamping branch and the passive clamping branch are parallel connected.

12. The voltage waveform generator of claim 1, wherein the control unit is configured to determine a switching time for applying the at least two voltage levels at the switch node so as to achieve a voltage at the common node equal to the predetermined level at an instant when a current through the first inductor is substantially zero.

13. The voltage waveform generator of claim 1, further comprising an output terminal for connection to a plasma reactor, wherein the common node is connected to the output terminal through a DC current blocking capacitor.

14. An apparatus for plasma assisted processing of a substrate, the apparatus comprising: a plasma reactor for generating a plasma, a processing platform for supporting the substrate, and the voltage waveform generator of claim 1, wherein the common node is electrically connected to the processing platform.

15. A method of generating a voltage waveform for a substrate subjected to plasma assisted processing, the method comprising: applying a switched voltage to a switch node, the switch node connected to a common node via an inductor, the common node electrically coupled to the substrate, wherein the switched voltage causes a first current to flow through the inductor, and wherein the first current through the inductor defines a ramp up and a ramp down of a voltage pulse of the voltage waveform, and clamping a voltage at the common node to a clamping voltage level while an absolute value of the first current is substantially zero during a clamping period.

16. The method of claim 15, wherein applying the switched voltage comprises: applying a first voltage level having a first magnitude during a first period, causing an increase of the first current, applying a second voltage level having a second magnitude smaller than the first magnitude during a second period following the first period, causing a decrease of the first current, wherein the clamping period follows the second period.

17. (canceled)

18. The method of claim 16, further comprising applying a fourth voltage level having a fourth magnitude during a fourth period following the second period, causing an absolute value of the first current to increase.

19. The method of any one of the claim 16, further comprising applying a fifth voltage level having a fifth magnitude larger than the second magnitude during a fifth period following the second period, causing an absolute value of the first current to decrease.

20. (canceled)

21. The method of claim 15, further comprising applying a DC current to the common node, at least between consecutive cycles of applying the switched voltage.

22. The method of claim 21, wherein the DC current is applied continuously.

23. The voltage waveform generator of claim 1, further comprising a current source coupled to the common node and configured to draw a DC current from the common node.

24. The voltage waveform generator of claim 23, wherein the current source is continuously connected to the common node and configured to continuously draw the DC current.

25. A voltage waveform generator for a plasma assisted processing apparatus, the voltage waveform generator comprising: a first switch node and a common node, a voltage supply circuit connected to the first switch node and operable to switch between at least two voltage levels at the first switch node, a first inductor connected between the first switch node and the common node, a control unit configured to operate the voltage supply circuit so as to obtain a predetermined voltage waveform at the common node, and a voltage clamping circuit coupled to the common node, wherein the voltage clamping circuit is configured to provide a switchable connection between the common node and a voltage node of the voltage supply circuit, the voltage node configured for providing one of the at least two voltage levels.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0053] Aspects of the present disclosure will now be described in more detail with reference to the appended drawings, wherein same reference numerals illustrate same features.

[0054] FIG. 1 represents an example of a voltage waveform generator used as bias generator for an ICP (Inductively Coupled Plasma) reactor according to aspects of the present disclosure.

[0055] FIG. 2 represents a simplified plasma reactor model and the voltage waveform generator according to the present disclosure coupled to it.

[0056] FIG. 3 represents a block diagram of components of the voltage waveform generator according to the present disclosure.

[0057] FIG. 4A represents combined plasma voltage and sheath voltage, i.e. the voltage at the exposed substrate surface, during processing and discharge periods. FIG. 4B represents the voltage at the substrate stage during processing and discharge periods, i.e. the voltage provided by the bias generator according to the present disclosure. FIG. 4C represents the voltage generated within the bias voltage generator and biased through the DC blocking capacitor, during processing and discharge periods.

[0058] FIG. 5A represents sheath current and ion current during processing and discharge periods. FIG. 5B represents the substrate stage current during processing and discharge periods. FIG. 5C represents the current supplied by the bias generator according to the present disclosure during processing and discharge periods.

[0059] FIG. 6 represents a circuit diagram of a bias voltage generator according to the present disclosure.

[0060] FIG. 7 represents a circuit diagram of a neutral-point-clamped (NPC) electrical converter for use as DC power supply in the pulse generation circuit of the bias voltage generator of FIG. 6.

[0061] FIG. 8 represents a detail of the voltage waveform of FIG. 4C during a discharge period.

[0062] FIG. 9 represents a detail of the current provided by the pulse generation circuit during a discharge period.

[0063] FIG. 10 represents the current flow path through the bias voltage generator during a ramp up period of a voltage discharge pulse causing a current through the inductor coil of the pulse generation circuit to rise.

[0064] FIG. 11 represents the current flow path through the bias voltage generator during a freewheeling period of a voltage discharge pulse following ramp up causing a current through the inductor coil of the pulse generation circuit to decrease.

[0065] FIG. 12 represents an alternative current flow path through the bias voltage generator during the same freewheeling period as in FIG. 11.

[0066] FIG. 13 represents the current flow path through the bias voltage generator during a voltage clamping period of a voltage discharge pulse while no current flows through the inductor coil of the pulse generation circuit.

[0067] FIG. 14 represents the current flow path through the bias voltage generator during a ramp down period of a voltage discharge pulse causing a reverse current through the inductor coil of the pulse generation circuit to rise.

[0068] FIG. 15 represents the current flow path through the bias voltage generator during a freewheeling period following ramp down causing the reverse current through the inductor coil of the pulse generation circuit to decrease.

[0069] FIG. 16 represents a circuit diagram of a power supply for the current source of the bias voltage generator as described herein, provided as a ‘rainstick’ DC/DC converter.

[0070] FIG. 17 represents the voltage at the switch node of the current source versus the voltage at the common node of the bias voltage generator as described herein, wherein the current source is switched to obtain a switched voltage at the switch node to minimize the volt seconds across the inductor of the current source.

[0071] FIG. 18 represents the current ripple on the current through the inductor of the current source associated with the voltage waveforms of FIG. 17.

DETAILED DESCRIPTION

[0072] FIG. 1 shows one of the typical usages of a bias voltage waveform generator (BVG) 10 in an Inductively Coupled Plasma (ICP) apparatus 100, where the BVG 10 is controlling the substrate 101 (typically a wafer) voltage by controlling the substrate stage voltage. In a plasma reactor 102, a plasma 103 is generated by introduction of a plasma forming gas 104 in a dielectric tube 108 surrounded by an induction coil 107. The arrangement forms a plasma torch which directs the plasma 103 towards a platform 105 (substrate stage) on which the substrate 101 is positioned. Optionally, a precursor 109 can be introduced in the plasma reactor 102. A radio frequency (RF) voltage is applied to the induction coil 107 through a RF power supply 120, and a matching network 121 as known in the art. The RF power supply 120, as well as the BVG 10 can be controlled through a system host controller 130. Plasma processes suitable for the present disclosure are so called low or reduced pressure plasma, i.e. operating at a pressure significantly below atmospheric pressure, e.g. between 1 mTorr and 10 Torr. To this end, the plasma reactor 102 is advantageously airtight and the desired pressure in plasma reactor 102 is obtained through a vacuum pump 106.

[0073] The BVG 10 can also be used in other configurations like a Capacitively Coupled Plasma (CCP) reactor, or a configuration with a direct interconnection (not via the system host controller) of control signals between a source power generator (RF power supply) and BVG. A different source can be used to generate the plasma (e.g. Capacitively Coupled Plasma, Electron Cyclotron Resonance, Magnetron, DC voltage, etc.).

[0074] FIG. 2 represents an electrical model of a plasma reactor 102, showing the load posed by the reactor, the plasma, the sheath and the substrate seen by the BVG 10. The sheath is a boundary layer with a greater density of positive ions, and hence an overall excess positive charge, which forms on the exposed surface of the substrate due to the plasma. The excess positive charge typically balances an opposite negative charge on the exposed surface of the substrate with which it is in contact. V.sub.pl represents the plasma potential at the sheath above the substrate and I.sub.i the ion current in the sheath. v.sub.sh represents the voltage across the sheath. The sheath can be modelled as a sheath capacitance C.sub.sh with sheath-capacitance current i.sub.sh representing the limited ion mobility in the sheath, during the process period, while the diode D.sub.P represents the high electron mobility in the sheath, during the discharge period. v.sub.sub represents the voltage across the substrate 101. Lumped capacitance C.sub.sub represents the capacitance of the dielectric substrate. L.sub.par is a lumped inductance representing the stray inductance of the BVG output power interconnection and return path. C.sub.t is a lumped capacitance representing the capacitance of the substrate stage (e.g. due to the electrostatic (dielectric) chuck holder on/in the substrate stage) and from the substrate stage power interconnection to earth 14 with associated voltage v.sub.t and current i.sub.t. The latter capacitance is usually dominated by the capacitance from the substrate table to the dark shield, i.e. a metal shield adjacent the platform 105 preventing the plasma to propagate beyond the platform, e.g. into pump 106.

[0075] A DC (bias) voltage across the sheath ideally results in a narrow IED, with the level of the DC voltage controlling the level of the (average) ion energy. There is a charge build-up on dielectric substrates and/or substrate stages of dielectric material (e.g. electrostatic chuck holders) caused by the positively charged ions that are collected on the plasma-exposed surface. Due to the charge build-up, an (ever-)decreasing voltage would need to be applied by the BVG in order to keep the sheath voltage constant. This is not achievable in a practical implementation. The charge build-up and therefore the potential over the substrate and/or substrate stage needs to be limited to prevent damage of the substrate and/or substrate stage. This compensation can be achieved by a periodic discharge of the substrate and/or substrate stage during a discharge interval between consecutive (plasma) process periods.

[0076] Referring to FIG. 4A, a process cycle period T.sub.C comprises a plasma processing period T.sub.process preceded (or followed) by a discharge period T.sub.D. During the plasma processing period T.sub.process, the sheath voltage v.sub.sh and/or the process voltage on the exposed surface of the substrate, V.sub.process=v.sub.sh+V.sub.pl is advantageously (directly or indirectly) controlled and kept constant. Typical values of V.sub.process range between 0 V and −1000 V. During the discharge periods T.sub.D between consecutive plasma processing periods T.sub.process, a positive voltage pulse is applied to the substrate stage allowing removal of electric charge built up on the exposed substrate surface. The discharge period T.sub.D is advantageously as small as possible, typically on the order of 200-500 ns, and the voltage pulse generated during this period advantageously features fast rise and fall times and possibly minimized oscillation of the voltage peak.

[0077] The voltage shape described above can be obtained by generating a voltage waveform at the substrate stage, by the BVG 10, as depicted in FIG. 4B. Taking account of the equivalent electric scheme of FIG. 2, a voltage slope must be generated by the BVG during T.sub.process to compensate for the charge/voltage build-up across the substrate.

[0078] Referring to FIGS. 5A-C, the process currents corresponding to the voltage waveforms of FIG. 4A-B are depicted. It can be seen that the voltage pulse of T.sub.D is accompanied by a current pulse i.sub.shwhile the plasma current I.sub.i remains substantially constant during the whole cycle period T.sub.C, i.e. i.sub.sh=0 during T.sub.process. At the substrate, a very high current peak i.sub.sub occurs during T.sub.D while ideally i.sub.sub=−I.sub.i during T.sub.process. To generate i.sub.sub, an even higher current pulse i.sub.load must be generated by the BVG during T.sub.D, while the current i.sub.load that must be generated during T.sub.process is typically one order of magnitude smaller (between about 0 and 4 A, and in relation to the scheme of FIG. 2,

[00001]$i_{\mathrm{load}}=-I_i\left(1+\frac{C_t}{C_{\mathrm{sub}}}\right)).$

Voltage Waveform Generation Circuit

[0079] To obtain the desired voltage waveforms described above, according to the present disclosure, a BVG 10 is provided as shown schematically in FIG. 3. BVG 10 comprises a pulse generation circuit 11 and a current source 16 which are coupled to a common node 13. Common node 13 is coupled to the output node 12 of the BVG 10 through an optional physical DC blocking capacitor C.sub.block.

[0080] The pulse generation circuit 11 is configured to generate a voltage pulse during the discharge period T.sub.D, which is applied at common node 13, and via DC blocking capacitor C.sub.block to the output node 12. An optional voltage clamping circuit 15 can be coupled to the common node 13 to reduce voltage oscillation and/or overshoot at the top plateau of the voltage pulse, as will be described further below. Current source 16 is configured to provide a current i.sub.CS to the common node 13 at least during the processing period T.sub.process, while pulse generation circuit 11 is advantageously inoperative during T.sub.process. Hence i.sub.load=i.sub.CS during T.sub.process. It will be convenient to note that i.sub.CS is typically negative (current source 16 sinks current).

[0081] According to one aspect, current source 16 operates continuously during the entire cycle T.sub.C to provide i.sub.CS to common node 13. In the latter case, i.sub.load=i.sub.CS+i.sub.pulse during the discharge period T.sub.D. However, as is evident from the graphs FIGS. 5A-C, i.sub.CS (between 0.5 A and 4 A, preferably between 1 A and 2 A) is one order of magnitude smaller than i.sub.pulse (peak amplitude at least 30 A, advantageously at least 40 A) during T.sub.D, and therefore can have negligible influence in the generation of the voltage pulse.

[0082] Referring to FIG. 4C, the DC-bias voltage v.sub.Cblock across the DC blocking capacitor C.sub.block allows to set a bias on the voltage at the common node v.sub.CN.

[0083] A circuit diagram of the different parts of the BVG 10 is represented in FIG. 6. The pulse generation circuit 11 advantageously comprises or consists of a neutral-point-clamped (NPC) bridge circuit comprising active switches 112 connected to a (DC) power supply having at least two (DC) voltage nodes A-G, with G indicating electrical ground GND. The power supply is advantageously provided as a ‘rainstick’ converter 110, possibly in combination with an (isolated) DC/DC converter, as shown in FIG. 7, providing the at least two voltage nodes A-G (seven voltage nodes in the example of FIG. 7, hence six DC-bus voltages A-B, B-C, C-D, D-E, E-F and F-G). By way of example, each DC-bus voltage A-B, or F-G, etc. can provide for a DC voltage between 100 V and 400 V, advantageously between 200 V and 400 V. Advantageously, the DC-bus voltages A-B, B-C, etc. are controllable by adjusting operation of the active switches of converter 110.

[0084] The voltage nodes A-G are connected to a switch node 111 through operable switches 112 of the NPC bridge, and which are operably coupled to a control unit 17. Switches 112 are advantageously semiconductor switches, e.g. provided as Field Effect Transistors (FETs), and advantageously comprise internal anti-parallel diodes (not shown). Switch node 111 is connected to common node 13 via a physical inductor (e.g. a coil) L.sub.pulse. Inductor L.sub.pulse advantageously allows for accurately controlling the current i.sub.pulse drawn from pulse generation circuit 11 and substantially reducing or suppressing the influence of the parasitic inductance of the electrical coupling to the substrate stage (represented by L.sub.par in FIG. 2) in controlling i.sub.pulse. Indeed, absent L.sub.pulse, the current i.sub.pulse would be largely defined by the parasitic inductance L.sub.par, and since the latter is unknown, i.sub.pulse would be hard to estimate accurately. Advantageously, L.sub.par is relatively smaller compared to L.sub.pulse. Providing L.sub.pulse allows to lower the LC resonance frequency of the equivalent LC circuit seen by the switch node 111, and to increase the load impedance. When a voltage is applied to switch node 111, the current will rise more slowly making it easier to calculate the timings of the voltage pulses applied to the switch node 111 in order to generate a clean discharge pulse.

[0085] The voltage clamping circuit 15 provides a switchable connection between the common node 13 and a DC voltage node, in particular a voltage node of a DC power supply, such as voltage node A of power supply 110. To this end, a first branch 151 comprises one active switch or a series arrangement of active switches, e.g. active semiconductor switches 153, to provide for an actively switchable connection between common node 13 and voltage node A. Switches 153 can be operated through control unit 17. The voltage clamping circuit can comprise a second branch 152 in parallel with the first branch 151, which can comprise passive switches, such as one or a series of diodes 155 making the time instant at which active switches 153 are turned on less critical. The voltage clamping circuit 15 can comprise an electrical damping element, such as a resistor 154, advantageously connected in the first branch 151 in series with switches 153, or alternatively in the second branch 152, or in both branches 151 and 152. Resistor 154 allows for reducing/damping voltage oscillations caused by any voltage mismatch when activating the voltage clamping circuit 15.

Current Source Circuit

[0086] According to another aspect, which can be provided in combination or independently from the other aspects described herein, the current source 16 comprises a power supply having at least two voltage levels (nodes) X, Y switchably connected to a switch node 161 through switches 162, which can be active semiconductor switches, such as FETs and which can be operably coupled to control unit 17. Switch node 161 is advantageously connected to the common node 13 via a physical inductor (e.g. a coil) L.sub.CS. The current source 16 is advantageously provided as a buck converter wherein the duty ratio of switches 162 allows for adjusting a DC voltage at the switch node 161 of the current source. A DC-bus midpoint GND.sub.CS between voltage nodes X and Y is advantageously provided. The voltage level of the GND.sub.CS is advantageously controlled (e.g. by control unit 17) such that the volt second product across the inductor L.sub.CS is minimized. In one example, the (average) DC voltage at switch node 161 in case the duty cycle (duty ratio) of switches 162 is set to 0.5 (50%). In this case, the potentials of X and Y are advantageously symmetric around GND.sub.CS.

[0087] Referring to FIG. 16, the power supply of current source 16 can be provided as a so called ‘rainstick’ DC/DC converter 160 comprising a plurality of voltage nodes X, Y, Z and GND.sub.CS realizing a plurality of DC-bus voltages X-GND.sub.Cs, GND.sub.Cs-Y, Y-Z, etc. The voltages of the DC-busses are advantageously adjustable by appropriate switching of switches of the DC/DC converter 160 and can be set to suitable values, with voltage difference between consecutive nodes advantageously ranging between 100 V and 400 V. The node GND.sub.CS acts as a DC-bus midpoint in the buck converter of current source 16 and is interposed between node X and Y. Advantageously, the ‘rainstick’ DC/DC converters 160 and the ‘rainstick’ converter of power supply 110 are connected to a shared power supply, in particular the converters/power supplies 160 and 110 share a DC-bus, e.g. DC-bus E-F is shared between the two.

Voltage Waveform (Pulse) Generation

[0088] The operation of the pulse generation circuit 11 for generating a voltage pulse during a discharge period T.sub.D will now be described. An enlarged waveform of the voltage pulse v.sub.CN generated at the common node 13 during T.sub.D is shown in solid line in FIG. 8. The corresponding current i.sub.pulse provided by pulse generation circuit 11 and flowing through inductor L.sub.pulse is shown in FIG. 9.

[0089] The voltage pulse comprises a ramp up period T.sub.12, starting at time instant t.sub.1 during which switches 112 are operated, e.g. by control unit 17, to connect a high voltage level, e.g. voltage level at node A, to switch node 111. This is shown in FIG. 8 with the dashed line indicating the voltage v.sub.SN at switch node 111. In this case, all switches 112 between switch node 111 and node A are closed, causing a current to flow through the pulse generation circuit as shown by the grey arrows in FIG. 10. The high voltage will cause the current i.sub.pulse through L.sub.pulse to increase, as shown in FIG. 9. The slope of i.sub.pulse is advantageously defined by the inductance of L.sub.pulse. A smaller inductance value will generally allow a faster ramping up of current and voltage, but will typically result in a higher peak current making switching timing as described above more critical and increasing sensitivity to signal oscillation in case of small mismatch in timing of the switches. A larger inductance value of L.sub.pulse will decrease the ramp slope. Therefore, optimal inductance values of L.sub.pulse are between 0.5 μH and 10 μH, advantageously between 1 μH and 5 μH.

[0090] At time instant t.sub.2, the switches 112 are opened and turn to non-conducting state and all switches 112 are maintained in non-conducting state. This signs the end of ramp up period T.sub.12 and beginning of a freewheeling period T.sub.23. Time instant t.sub.2 can be selected as the time instant at which the voltage at common node 13 almost reaches the voltage level at switch node 111 (e.g., voltage level of node A). Since the current i.sub.pulse through the inductor L.sub.pulse must be continuous, a current path is created from electrical ground at node G, through the internal anti-parallel diodes of the switches 112 arranged between node G and switch node 111, as shown by the grey arrows in FIG. 11. The voltage v.sub.SN at switch node 111 drops to the voltage level of node G, while the voltage v.sub.CN at common node 13 continues to rise somewhat due to the current in inductor L.sub.pulse that is still flowing and is ramping down while releasing its energy to the load capacitance, still charging this capacitance. Voltage v.sub.CN can eventually reach the level of node A. The current i.sub.pulse through inductor L.sub.pulse will hence decrease to eventually become zero at time instant t.sub.3, signing the end of freewheeling period T.sub.23.

[0091] It is alternatively possible to connect switch node 111 to an intermediate voltage level B-F during freewheeling period T.sub.23. This will alter the falling slope of i.sub.pulse and hence have an impact on the slope of the rising edge of the voltage, and therefore a suitable voltage level can be selected based on a desired waveform. The current path is shown in FIG. 12 for the exemplary case in which switch node 111 is connected to voltage node F. In the latter case, switches 112a is actively closed to create the current path through node F.

[0092] At time instant t.sub.3, the voltage at common node 13 is advantageously clamped to its maximum level, e.g. level of node A, during a clamping period T.sub.34. The voltage clamping circuit 15 is advantageously used for this purpose. Switches 153, which can be active semiconductor switches, e.g. FETs, are operated by control unit 17 to turn to a conductive state. As a result, the voltage level at common node 13 is clamped to the voltage of node A. Any voltage mismatch between common node 13 and voltage node A at turn-on of the switches 153 is advantageously suppressed by resistor 154. Since the current i.sub.pulse through inductor L.sub.pulse at time instant t.sub.3 was zero, and all switches 112 are maintained in non-conducting state during T.sub.34, i.sub.pulse will remain zero during the entire clamping period T.sub.34. The length of clamping period T.sub.34 is advantageously selected based on a desired length T.sub.D of the voltage pulse.

[0093] It will be convenient to note that diodes 155 of clamping branch 152 allow clamping the voltage v.sub.CN in case it would rise too fast and e.g. reach the level of node A too early, in particular before the current through inductor L.sub.pulse becomes zero. This may be the case when a switching timing mismatch occurs.

[0094] A possible current path through the BVG during clamping period T.sub.34 is represented by the grey arrows in FIG. 13. As the voltage level of common node 13 will eventually reach the level of node A at the opposite side of the voltage clamping circuit 15, the diodes 155 may start conducting. At this time, switches 153 can be switched to non-conducting state.

[0095] Alternatively, switches 153 can be maintained in conducting state during T.sub.34. This is particularly relevant if the current source 16 is operating also during the discharge period T.sub.D. The switches 153 in that case prevent that the current drawn by the current source 16 would discharge the load capacitance during the clamping interval, causing the voltage of common node 13 to decrease below A. Switches 153 therefore allow to conduct the current drawn by the current source 16 and keep the voltage of common node 13 clamped to the voltage of voltage node A.

[0096] It is alternatively possible to dispense with the clamping period T.sub.34. In such case, voltage clamping circuit 15 need not be provided.

[0097] Advantageously, a clamping diode (not shown) is provided between the common node 13 and voltage node G allowing to limit the magnitude of the voltage spikes as visible in FIG. 4C. These voltage spikes are induced at turn-off (opening) of the switches 153 of the clamping circuit 15, causing the current of the current source 16 to be interrupted. A diode between 13 and G would clamp this voltage spike.

[0098] At time instant t.sub.4, the ramp down of the voltage pulse is initiated. This signs the end of the clamping period T.sub.34, and the start of the ramp down period T.sub.45. To obtain a ramp down, the current i.sub.pulse through inductor L.sub.pulse is made to become negative. To this end, switch node 111 is connected to a voltage node of DC power supply 110 having a voltage potential which is lower than the (instantaneous) voltage potential of common node 13. In the present exemplary embodiment, since common node is bound to voltage level A due to voltage clamping circuit 15, it will be sufficient to select any one of levels B-G. The level selected will of course have an impact on the slope of the ramp down, and therefore a suitable level can be selected based on a desired waveform.

[0099] By way of example, the current path through the BVG 10 during the ramp down period is shown in FIG. 14 for the case that switch node 111 is connected to voltage node C by operating switches 112b and 112c to become conducting. The voltages v.sub.CN and v.sub.SN during T.sub.45 are shown in FIG. 8 and the current i.sub.pulse through inductor L.sub.pulse is shown in FIG. 9.

[0100] The ramp down period T.sub.45 is followed by a freewheeling period T.sub.56 to bring the current i.sub.pulse through L.sub.pulse back to zero before ending the discharge period (and hence operation of the pulse generation circuit 11) and starting a new processing period T.sub.process. To this end, at t.sub.5 switches 112b and 112c are switched back to the non-conducting state and all of switches 112 remain in non-conducting state (or any other suitable voltage level can be selected). Since i.sub.pulse must remain continuous, the inductor L.sub.pulse will cause a current to flow between switch node 111 and voltage node A. Switches 112 can be provided with internal anti-parallel diodes, in which case they will conduct this current. Alternatively, external diodes can be provided in anti-parallel with the switches 112. Yet alternatively, other solutions mimicking the operation of such anti-parallel diodes can be used, e.g. switches 112 can be GaN normally-off junction gate field effect transistor (JFET) switches, which allow third quadrant operation, i.e. behaving similarly as diodes in reverse conduction. The resulting current path during T.sub.56 is represented by the grey arrows in FIG. 15. The internal diodes of switches 112 will automatically turn to non-conducting state once the current i.sub.pulse has become zero at time instant t.sub.6 (see FIG. 9). This signs the end of a discharge period and the start of a new processing period T.sub.process.

[0101] The time instants t.sub.1-t.sub.6 and the voltage levels A-G applied to switch node 111 are advantageously selected to maintain a V.s (volt seconds) balance of the inductor L.sub.pulse. In other words and referring to FIG. 8, the resulting area between curves v.sub.CN and v.sub.SN should be zero over the time span of T.sub.D. This allows for maintaining a steady-state condition/operation in which the average value of the current i.sub.pulse in inductor L.sub.pulse does not drift away. It will be convenient to note that, when i.sub.CS is made to flow continuously over TD, the average value of i.sub.pulse over T.sub.D (and T.sub.C) is not zero and is related to i.sub.CS and thus to I.sub.i. It will be convenient to note that additional voltage switching states (periods of v.sub.SN) can be added, before, after or in between the periods T.sub.12-T.sub.56 in order to obtain a desired voltage waveform for v.sub.CN.

[0102] During a process period T.sub.process, the pulse generation circuit 11 remains inoperative, and no current i.sub.pulse flows through inductor L.sub.pulse. As a result, the voltage over L.sub.pulse is zero and the voltage level at switch node 111 will follow the voltage level of the common node 13 during T.sub.process.

Current Generation

[0103] The operation of the current source 16 will now be described. To compensate for the charging of the load capacitance C.sub.sub due to I.sub.i a current needs to be sunk from C.sub.sub (and hence also from C.sub.t). To this end, a voltage slope must be obtained at the common node 13 (and hence at the output node 12) during the process period T.sub.process, as shown in FIGS. 4B-C. The current source 16 is operated to provide a suitable DC current i.sub.CS. The current source 16 is advantageously continuously connected to the common node 13 to continuously provide a current i.sub.CS during an entire cycle period T.sub.C, i.e. both during T.sub.process and during T.sub.D, since this avoids any distortions that would occur when enabling/disabling or connecting/disconnecting the current source 16, and avoids system complexity related with the measures that would need to be taken to implement a connection/disconnection device/circuitry.

[0104] Referring to FIGS. 17-18, one advantage of the switch node 161 of current source 16 allowing to switch between different voltage levels (of nodes X-Y), is that the current ripple of i.sub.CS can be minimized over one period, e.g. one cycle period T.sub.C or one process period T.sub.process as the case may be. Switching the voltage v.sub.CS of switch node 161 allows for making the volt seconds (V.s) over inductor L.sub.CS zero over the given period, as can be seen in FIG. 17, where the hatched areas indicating the difference between the voltage v.sub.CN at the common node 13 and the voltage of v.sub.CS fully compensate one another over one period. This also means that the average value of i.sub.CS will not drift away and a steady-state condition can be achieved. This can be achieved by measuring the average value of i.sub.CS (by a current measuring means) and adapting the duty ratio of switches 162 such that the average value of i.sub.CS is equal to a predetermined value (which can be implemented by a current control loop implemented in control unit 17). Alternatively, or in addition, the voltage potentials of nodes X and Y can be suitably adjusted. FIG. 17 shows the voltage v.sub.CS at switch node 161 is switched at time instant t.sub.7 between nodes X and Y.

[0105] The current ripple can be reduced by aligning v.sub.CS with v.sub.CN in a way that all the individual volt-second areas between the curves of v.sub.CS and v.sub.CN are minimized. Alternatively, or in addition, the voltage levels of X and Y can be adapted to minimize current ripple of i.sub.CS. This is advantageously performed while maintaining a steady-state condition, i.e. zero net volt-second area or in other words: the average of v.sub.CS is equal to the average of v.sub.CN. A reduced current ripple on i.sub.CS advantageously results in a reduced ripple of the sheath voltage.

[0106] In another aspect, control unit 17 is configured to synchronize switching of switches 162 of the current source 16 and switches 112 of pulse generation circuit 11, advantageously both in frequency and phase. This can be achieved by implementing a same clock for operating the switches 162 and 112 within control unit 17. This allows for synchronizing the voltage switches of switch node 161 of the current source with the voltage switches of switch node 111 of the pulse generation circuit. As a result, the volt seconds of inductor L.sub.CS can be made zero over a given period with greater ease, and avoiding any possible mismatch due to non-synchronous clocks. By so doing, a smaller inductor coil L.sub.CS can be used, making the circuit more compact. Additionally, a smaller current ripple on i.sub.CS is obtained. Advantageously, the inductance of L.sub.CS is between 500 pH and 1 mH. Advantageously, the switching frequency of switches 162 is between 1 kHz and 10 MHz, in particular between 10 kHz and 1 MHz.

[0107] The current source 16 can comprise more than two switchable voltage levels allowing to further reduce the current ripple on i.sub.CS. This way, the voltage at the switch node 161 of the current source can be made to more closely follow the waveform of the voltage v.sub.CN of the common node 13. However, this may increase the footprint of the current source circuits and a two-voltage-level circuit (buck converter) can be considered an optimal compromise between performance and footprint.

[0108] The pulse generation circuit 11 and possibly voltage clamping circuit 15 and/or the current source 16 can be operated by the control unit 17 through open loop. Alternatively, it may be advantageous to implement a closed loop control in control unit 17 for operating any one of pulse generation circuit 11, voltage clamping circuit 15, and current source 16. To this end, the BVG 10 can comprise measurement devices configured to measure one or a combination of:

the voltage waveform (voltage envelope), which may be measured at common node 13 and/or output node 12;
the voltage level of the common node 13 and/or output node 12 at the start of a discharge period (time instant t.sub.1);
the voltage level of the common node 13 and/or output node 12 at the end of a discharge period (time instant t.sub.6);
the current i.sub.pulse through the inductor L.sub.pulse;
the current i.sub.CS generated by the current source 16 (through inductor L.sub.Cs);
the current through the clamping circuit 15,
one or more voltage levels of the DC bus of power supply 11 and/or 160, and
a process voltage in the plasma chamber 102 (e.g., v.sub.t).
Any one of the above measurements can be used in a feedback control loop implemented in control unit 17 to control the operation of the pulse generation circuit and/or the voltage clamping circuit during a discharge period. In addition, or alternatively, these measurements can also be used to control operation of the current source 16, during either one or both a process period and a discharge period.