METHOD AND SYSTEM FOR THE PRODUCTION OF A STARTING MATERIAL FOR A SILICON SOLAR CELL WITH PASSIVATED CONTACTS

Abstract

The present invention is directed to a method as well as to a machine for producing a starting material for a silicon solar cell with passivated contacts.

Claims

1. A method for producing a starting material for a silicon solar cell with passivated contacts, comprising: providing a silicon wafer with a tunnel oxide layer coating the tunnel oxide layer with at least one first layer of amorphous silicon by means of cathode sputtering; coating the at least one first layer with at least one second layer comprising a dopant by means of cathode sputtering; and annealing the coated silicon wafer at a temperature of at least 700° C.

2. The method according to claim 1, wherein the tunnel oxide layer comprises an SiO.sub.2 layer having a thickness of 0.5 nm to 10 nm.

3. The method according to claim 1, wherein the at least one first layer consists of intrinsic silicon and/or doped silicon.

4. The method according to claim 1, wherein the at least one second layer comprises one or a combination of the following materials: silicon or silicon oxide doped with an element from the 3rd or 5th main group or an element from the 3rd or 5th main group as a pure substance or in the form of an oxide.

5. The method according to claim 4, wherein the proportion of the element from the 3rd or 5th main group is at least 0.5 mol % of the second layer.

6. The method according to claim 1, wherein the second layer has a thickness between 10 nm and 1 μm.

7. The method according to claim 1, wherein the provision of a silicon wafer with a tunnel oxide layer comprises wet-chemical generation of the tunnel oxide layer or generation of the tunnel oxide layer by a plasma process on the silicon wafer.

8. The method according to claim 1, wherein the at least one first layer and the at least one second layer are applied in a same cathode sputtering machine.

9. The method according to claim 1, wherein the annealing step causes that the at least one first layer of amorphous silicon is converted into a doped polycrystalline silicon layer.

10. The method according to claim 9, wherein a silicon layer doped with the dopant of the at least one second layer is formed directly below the tunnel oxide layer in the silicon wafer and wherein the dopant concentration drops across said silicon layer.

11. The method according to claim 10, wherein the silicon layer doped with the dopant of the second layer is formed in a region extending from the tunnel oxide layer to a maximum of 50 nm below the tunnel oxide layer.

12. The method according to claim 9, wherein the electrically active dopant concentration in the doped polycrystalline silicon layer is at least 1×10.sup.20 cm.sup.−3 in the case of p-doping and at least 5×10.sup.19 cm.sup.−3 in the case of n-doping.

13. The method according to claim 1, further comprising: coating the side of the silicon wafer opposite the tunnel oxide layer with at least one third layer comprising a dopant by means of cathode sputtering.

14. The method according to claim 13, wherein the third layer comprises one or a combination of the following materials: silicon or silicon oxide doped with an element from the 3rd or 5th main group, or an element from the 3rd or 5th main group as a pure substance or in the form of an oxide.

15. The method according to claim 13, wherein the annealing step causes that a silicon layer doped with the dopant of the third layer is formed below the third layer in the silicon wafer.

16. The method according to claim 1, wherein the silicon wafer is provided with a tunnel oxide layer on both sides and wherein the method comprises: coating each of the two tunnel oxide layers with at least one first layer of amorphous silicon by means of cathode sputtering; coating each of the two first layers with at least one second layer comprising a dopant by means of cathode sputtering.

17. The method according to claim 16, wherein the annealing step causes a simultaneous conversion of each of the at least one first layer of amorphous silicon on both sides into a doped polycrystalline silicon layer.

18. The method according to claim 17, wherein the annealing step causes the formation of a silicon layer doped with the dopant of the at least one second layer directly below and directly above the tunnel oxide layer and wherein the dopant concentration drops across said silicon layers.

19. The method according to claim 17, wherein the silicon layers doped with the dopant of the at least one second layer are formed in a region extending from the tunnel oxide layer to a maximum of 50 nm below and above the tunnel oxide layer.

20. The method according to claim 1, further comprising: coating the at least one second layer with a hydrogen-enriched cover layer comprising a nitride and/or an oxide.

21. The method according to claim 1, wherein the silicon wafer is moved during the two coatings with the first and second layers as well as between the two coatings.

22. The method according to claim 1, wherein the provision of a silicon wafer with a tunnel oxide layer comprises coating the silicon wafer with the tunnel oxide layer by means of cathode sputtering.

23. The method according to claim 22, wherein the silicon wafer is moved during the two coatings with the first and second layers as well as during the coating with the tunnel oxide layer.

24. The method according to claim 1, wherein the production takes place in a continuous process.

25. A machine for producing a starting material for a silicon solar cell with passivated contacts, comprising: a first cathode sputtering unit adapted to coat a substrate with at least one first layer of amorphous silicon; a second cathode sputtering unit adapted to coat the first layer with at least one second layer comprising a dopant; and optionally an annealing unit adapted to anneal the substrate coated with the first and second layers at a temperature of at least 700° C.; wherein the first and second cathode sputtering devices are integrated in a common vacuum process section of the machine.

26. The machine according to claim 25, wherein the first and second cathode sputtering devices are spaced apart from each other along the process section.

27. The machine according to claim 26, wherein the distance between the outer sides of the cathodes of the first and second cathode sputtering devices is at least 10 cm.

28. The machine according to claim 25, further comprising an upstream wet-chemical unit adapted to provide a silicon wafer with a tunnel oxide layer by a wet-chemical process, or a plasma unit adapted to provide a silicon wafer with a tunnel oxide layer by a plasma process.

29. The machine according to claim 25, further comprising: a further cathode sputtering unit adapted to coat the silicon wafer with a tunnel oxide layer; wherein the first, the second and the further cathode sputtering devices are integrated in a common vacuum process section of the machine.

30. The machine according to claim 25, further comprising: a third cathode sputtering unit adapted to coat the substrate on the side opposite the first layer with at least one third layer comprising a dopant; wherein the first, second and third cathode sputtering devices are integrated in a common vacuum process section of the machine.

31. The machine according to claim 25, further comprising: a third cathode sputtering unit adapted to coat the substrate on the side opposite the first layer with at least one first layer of amorphous silicon; and a fourth cathode sputtering unit adapted to coat the first layer with at least one second layer comprising a dopant; wherein the first, second, third and fourth cathode sputtering devices are integrated in a common vacuum process section of the machine.

Description

[0056] In the following, preferred embodiments of the present invention will be described in more detail with reference to the Figures, in which:

[0057] FIG. 1 shows a cross-section through a solar cell with charge carrier-selective, polycrystalline silicon contacts according to a preferred embodiment of the present invention;

[0058] FIG. 2 shows a cross-section through a solar cell with charge carrier-selective, polycrystalline silicon contacts according to a further preferred embodiment of the present invention;

[0059] FIG. 3 shows a cross-section through a starting material for a silicon solar cell with passivated contacts before the annealing step according to a preferred embodiment of the present invention;

[0060] FIG. 4 shows the starting material according to FIG. 3 after the annealing step;

[0061] FIG. 5 shows a starting material for a silicon solar cell with passivated contacts before the annealing step according to a preferred embodiment of the present invention;

[0062] FIG. 6 shows the starting material according to FIG. 5 after the annealing step according to a first variant;

[0063] FIG. 7 shows the starting material according to FIG. 5 after the annealing step according to a second variant;

[0064] FIG. 8 shows the starting material for a silicon solar cell with passivated contacts before the annealing step according to a further preferred embodiment of the present invention;

[0065] FIG. 9 shows the starting material according to FIG. 8 after the annealing step according to a first variant;

[0066] FIG. 10 shows the starting material according to FIG. 8 after the annealing step according to a second variant;

[0067] FIG. 11 shows the starting material according to FIG. 8 after the annealing step according to a third variant;

[0068] FIG. 12 shows a starting material for a silicon solar cell with passivated contacts according to a further preferred embodiment of the present invention;

[0069] FIG. 13 shows a starting material for a silicon solar cell with passivated contacts according to a further preferred embodiment of the present invention;

[0070] FIG. 14 shows a starting material for a silicon solar cell with passivated contacts according to a further preferred embodiment of the present invention;

[0071] FIG. 15 shows a starting material for a silicon solar cell with passivated contacts according to a further preferred embodiment of the present invention;

[0072] FIG. 16 shows a starting material for a silicon solar cell with passivated contacts according to a further preferred embodiment of the present invention;

[0073] FIG. 17 shows a starting material for a silicon solar cell with passivated contacts according to a further preferred embodiment of the present invention;

[0074] FIG. 18 shows a starting material for a silicon solar cell with passivated contacts according to a further preferred embodiment of the present invention;

[0075] FIG. 19 shows a starting material for a silicon solar cell with passivated contacts according to a further preferred embodiment of the present invention;

[0076] FIG. 20 shows a starting material for a silicon solar cell with passivated contacts according to a further preferred embodiment of the present invention;

[0077] FIG. 21 shows a starting material for a silicon solar cell with passivated contacts according to a further preferred embodiment of the present invention;

[0078] FIG. 22 shows a starting material for a silicon solar cell with passivated contacts according to a further preferred embodiment of the present invention;

[0079] FIG. 23 shows a schematic diagram of a machine for producing a starting material for a silicon solar cell with passivated contacts according to a preferred embodiment of the present invention;

[0080] FIG. 24 shows a schematic diagram of a machine for producing a starting material for a silicon solar cell with passivated contacts according to a preferred embodiment of the present invention;

[0081] FIG. 25 shows a schematic diagram of a machine for producing a starting material for a silicon solar cell with passivated contacts according to a preferred embodiment of the present invention;

[0082] FIG. 26 shows a schematic diagram of a machine for producing a starting material for a silicon solar cell with passivated contacts according to a preferred embodiment of the present invention;

[0083] FIG. 27 shows a schematic diagram of a machine for producing a starting material for a silicon solar cell with passivated contacts according to a preferred embodiment of the present invention;

[0084] FIG. 28 shows a schematic diagram of a machine for producing a starting material for a silicon solar cell with passivated contacts according to a preferred embodiment of the present invention;

[0085] FIG. 29 shows a schematic diagram of a machine for producing a starting material for a silicon solar cell with passivated contacts according to a preferred embodiment of the present invention; and

[0086] FIG. 30 shows a schematic diagram of a machine for producing a starting material for a silicon solar cell with passivated contacts according to a preferred embodiment of the present invention.

[0087] FIGS. 1 and 2, illustrate cross-sections through silicon solar cells with passivated contacts analogous to those shown in FIG. 1 of WO 2018/102852 A1. In FIG. 1, a p-doped silicon wafer 5a is provided with an n.sup.+ diffusion layer 8a and an SiN.sub.X layer 9. The latter is penetrated by the metal contacts 21 of the front side. On the back side of the wafer 5a there is an SiO.sub.X tunnel oxide layer 6 as well as a p.sup.+-doped polycrystalline silicon layer 101a, on which the metal contact 20 of the back side is arranged.

[0088] FIG. 2 shows an analogous cell with an n-doped silicon wafer 5b, a p.sup.+ diffusion layer 8b, and an n.sup.+-doped polycrystalline silicon layer 101b.

[0089] As has already been explained in detail, it is an object of the present invention to provide an improved method for producing a starting material for such a silicon solar cell with passivated contacts, with the aid of which a respectively high dopant concentration can be achieved in a simple manner.

[0090] According to the invention, a silicon wafer 5 (cf. FIG. 3) with a tunnel oxide layer 6 is provided for this purpose and the tunnel oxide layer 6 is coated with at least one first layer 1 of amorphous silicon by means of cathode sputtering. The first layer 1 is then coated with at least one second layer 2 comprising a dopant by means of cathode sputtering. The result of these two coating processes can be seen in a schematic cross-sectional view in FIG. 3. The tunnel oxide layer 6 preferably consists of SiO.sub.2 and preferably has a thickness between 0.5 nm and 10 nm. The first layer 1 of amorphous silicon preferably consists of intrinsic silicon and/or doped silicon and preferably has a thickness between 1 and 100 nm. The second layer 2 preferably comprises one or a combination of the following materials: silicon or silicon oxide doped with an element from the 3rd or 5th main group, preferably phosphosilicate glass or borosilicate glass, an element from the 3rd or 5th main group as a pure substance or in the form of an oxide.

[0091] According to the invention, the coated silicon wafer 5 (including layers 1, 2 and 6 as well as, where applicable, further layers) is annealed at a temperature of at least 700° C. This annealing step preferably causes diffusion of the dopant contained in the second layer 2 into the adjacent first layer 1 of amorphous silicon and optionally through the tunnel oxide layer 6 into the region of the silicon wafer 5 directly adjacent to the tunnel oxide layer 6. In other words, the annealing step preferably causes that the first layer 1 of amorphous silicon is converted into a doped polycrystalline silicon layer 101 (cf. FIG. 4) and that optionally a silicon layer 7 doped with the dopant of the second layer 2 is formed below the tunnel oxide layer 6 in the silicon wafer 5.

[0092] An example of the result of such an annealing step, in which likewise a silicon layer 7 doped with the dopant of the second layer 2 is formed below the tunnel oxide layer 6 in the silicon wafer 5, is schematically shown in FIG. 4.

[0093] Preferably, the dopant concentration in the doped polycrystalline silicon layer 101 is at least 1×10.sup.20 cm.sup.−3 in the case of p-doping and at least 5×10.sup.19 cm.sup.−3 in the case of n-doping. The second layer 2 (cf. FIG. 3) is denoted by reference sign 102 after the annealing step (cf. FIG. 4), since its dopant concentration may be reduced, compared to its state before the annealing step, due to the diffusion of the dopant into the layers 101 and 7. The thicknesses of layers 6, 101 and 102 after the annealing step are essentially the same as the thicknesses of layers 6, 1 and 2 before the annealing step. The silicon layer 7 doped with the dopant of the second layer 2 preferably has a thickness between 50 and 200 nm.

[0094] Furthermore, according to the invention, the side of the silicon wafer 5 opposite the tunnel oxide layer 6 can be coated with at least one third layer 3 comprising a dopant. This coating with the third layer 3 is preferably also carried out before the annealing step described above. The result of the coating is schematically shown in FIG. 5.

[0095] Analogous to the materials of the second layer 2, the third layer 3 can comprise one or a combination of the following materials: silicon or silicon oxide doped with an element from the 3rd or 5th main group, preferably phosphosilicate glass or borosilicate glass, an element from the 3rd or 5th main group as a pure substance or in the form of an oxide, wherein the second layer 2 and the third layer 3 preferably are oppositely doped. This leads to corresponding n- and p-doped layers analogously to FIGS. 1 and 2.

[0096] Depending on the thicknesses, dopant concentrations and diffusion properties of the individual layers as well as the parameters selected during annealing, annealing the layer sequence according to FIG. 5 can lead to a starting material according to FIG. 6 or to an alternative starting material according to FIG. 7. In both cases, the annealing process causes that a silicon layer 8 doped with the dopant of the third layer 3 is formed below the third layer 3, 103 in the silicon wafer 5. In both cases, the annealing process further causes that the first layer 1 of amorphous silicon is transformed into a doped polycrystalline silicon layer 101. Depending on whether the dopant from the second layer 2 diffuses through the tunnel oxide layer 6 into the silicon wafer 5 adjacent thereto, the annealing step can additionally cause that a silicon layer 7 doped with the dopant from the second layer 2 is formed below the tunnel oxide layer 6 in the silicon wafer 5. The latter alternative is shown in FIG. 7.

[0097] The layer sequence according to FIGS. 5 to 7 can be used, for example, as a starting material for a silicon solar cell with passivated contacts on one side and a classical diffused emitter on the other side. Alternatively, the method according to the invention can also be used for producing a starting material for a silicon solar cell with passivated contacts on both sides.

[0098] For this purpose, a silicon wafer 5 is preferably provided on both sides with corresponding tunnel oxide layers 6 (cf. FIG. 8). Subsequently, each of the two tunnel oxide layers 6 is coated with at least one first layer 1 of amorphous silicon and each of the two first layers 1 is coated with at least one second layer 2 comprising a dopant. The result of these coating processes is schematically illustrated in FIG. 8.

[0099] This stack of layers is then annealed at a temperature of at least 700° C., which, analogously to the above statements, causes that each of the first layers 1 of amorphous silicon is converted into a doped polycrystalline silicon layer 101 on both sides. This conversion takes place essentially simultaneously in the course of a common annealing step.

[0100] The result of such an annealing step is again schematically shown in FIG. 9. Analogously to the above statements, however, starting materials with layer sequences corresponding to FIGS. 10 and 11 can also be achieved by the annealing step when the annealing process causes a formation of a doped silicon layer 7 below one of (cf. FIG. 10) or below each of the two tunnel oxide layers 6 (cf. FIG. 11) in the silicon wafer 5.

[0101] It is further preferred that the second layer 2 and/or the third layer 3 is coated with a hydrogen-enriched cover layer 9 comprising a nitride and/or an oxide, preferably a hydrogen-enriched silicon nitride. In FIGS. 12 to 22, the preferred embodiments of the starting material according to the invention as already discussed above are schematically illustrated in each case with one or two such cover layers 9. FIGS. 12 to 22 show the starting material in each case after the annealing step, so that the cover layer 9 is in each case on the second layer 102 and/or the third layer 103 after the annealing step.

[0102] FIGS. 23 to 30 schematically illustrate preferred embodiments of the machine according to the invention for producing a starting material for a silicon solar cell with passivated contacts. As shown in FIG. 23, such a machine comprises a first cathode sputtering unit 11 adapted to coat at least one substrate 10 with at least one first layer of amorphous silicon. The machine further comprises a second sputtering unit 12 adapted to coat the first layer with at least one second layer comprising a dopant. The first cathode sputtering device 11 and the second cathode sputtering device 12 are integrated in a common vacuum process section of the machine, which is symbolized by the double arrow.

[0103] Optionally, an annealing unit 15 can be provided (cf. FIG. 24), which is adapted to anneal the substrate coated with the first and second layers at a temperature of at least 700° C. The annealing unit 15 can be integrated in the same vacuum process section, as schematically illustrated in FIG. 24, or represent a separate module (cf. FIG. 25).

[0104] The machine can further comprise an upstream wet-chemical unit 16 (cf. FIG. 26), which is adapted to provide a silicon wafer with a tunnel oxide layer by means of a wet-chemical process. This wet-chemical unit 16 can be a separate module, which is connected to the vacuum process section according to FIG. 27 via a process section or forms a completely separate unit.

[0105] Alternatively, a plasma unit 17 can be provided (cf. FIG. 28), which is adapted to provide a silicon wafer with a tunnel oxide layer by means of a plasma process. Together with the first cathode sputtering device 11 and the second cathode sputtering device 12, the plasma unit 17 can be integrated in a common vacuum process section of the machine, which is also symbolized by the double arrow in FIG. 28. Alternatively, the plasma unit 17 can also form a separate module.

[0106] The machine can further comprise a third cathode sputtering unit 13 adapted to coat the substrate on the side opposite the first layer with at least one third layer comprising a dopant. The first cathode sputtering device 11, the second cathode sputtering device 12 and the third cathode sputtering device 13 are preferably integrated in a common vacuum process section of the machine, as schematically illustrated in FIG. 29.

[0107] Alternatively, the machine can include a third cathode sputtering unit 13 adapted to coat the substrate on the side opposite the first layer with at least one first layer of amorphous silicon, as well as a fourth cathode sputtering unit 14 adapted to coat the first layer with at least one second layer comprising a dopant. As can be seen in FIG. 30, the first cathode sputtering device 11, the second cathode sputtering device 12, the third cathode sputtering device 13 and the fourth cathode sputtering device 14 are preferably integrated in a common vacuum process section of the machine, which is again symbolically represented by the double arrow.

[0108] In the following, a concrete embodiment of the method according to the invention will be described in detail.

[0109] The starting point was a silicon wafer with the following properties: p-type monocrystalline wafer material with a typical conductivity of 10 Ohm*cm. After wet-chemically cleaning the wafers, using, for example, RCA or an alternative industrial cleaning process with acidic or alkaline media (for example KOH/H.sub.2O.sub.2), at least the front side of the wafers was subjected to wet-chemical alkaline texturing (e.g. using KOH and an additive, for example CellTex). Subsequently, a tunnel oxide of a thickness of approximately 1.4 nm was generated only on the back side of the wafer in a bath with an ozone-containing solution at an elevated temperature.

[0110] The tunnel oxide layer of the silicon wafer was then coated with a first layer of amorphous silicon. For this purpose, a horizontal sputtering machine of the type GENERIS from the company SINGULUS TECHNOLOGIES AG was used, in which up to 64 wafers per substrate carrier are transported at a constant linear speed of approximately 1 to 3 m/min through the evacuated process area comprising one or more linear coating sources, for example with planar or cylindrical magnetrons. Typical process conditions were: sputtering pressure/gas: 8×10.sup.−3 mbar/argon, wafer temperature: 200° C., sputtering targets: planar Si sputtering targets with 5N purity, electrical excitation: DC with a power density of 3 W/cm.sup.2.

[0111] The first layer of amorphous silicon thus formed has a thickness of 20 nm. Subsequently, a second layer with a layer thickness of 100 nm was applied to the first layer in the same sputtering machine. The sputtering target was a planar phosphosilicate glass with a phosphorus doping of >1%.

[0112] In the subsequent annealing step, the electrical activation and diffusion of the doping and at the same time the conversion of the amorphous silicon layer into a polycrystalline silicon layer took place in a furnace under N.sub.2 inert gas at 800° C.-850° C. for <30 min.

[0113] Subsequently, the front side was optionally post-cleaned (HF dip), then coated with approximately 10 nm AlOx and then both sides, the front side and the annealed layer on the back side, were each covered with an SiN:H layer of a thickness of 80 nm. These coatings were performed according to typical PERC solar cell recipes at a substrate temperature of approximately 400° C. in a PECVD machine, likewise of the type GENERIS from the company SINGULUS TECHNOLOGIES AG. For classical PERC solar cells, the AlOx+SiN:H layer system is applied to the back side, here on the textured front side. For this purpose, adjustments had to be made in the layer thickness as well as in the gas ratio SiH4:NH3 for SiN:H and TMAL+Ar+N.sub.2O for AlOx. The plasma sources used for this CVD process were inductively driven at 13.56 MHz and linearly arranged.

[0114] As already mentioned, the present invention enables the production within the scope of a continuous process, for example by means of the aforementioned sputtering machine of the type GENERIS from the company SINGULUS TECHNOLOGIES AG.

[0115] For this purpose, the wafers are located on a substrate carrier in pockets, typically 30 to 80 wafers per carrier, depending on the size of the wafers (typical square wafer sizes: M0-G12 (156 mm-210 mm), typical round wafer sizes: 1″-300 mm). These substrate carriers are usually loaded in air (dust-free enclosure) with low-contact/contactless grippers.

[0116] Subsequently, individual carriers (or carrier groups) are introduced in a so-called loadlock chamber. After the introduction of the carrier(s), this chamber is pumped down from 1,000 mbar to about 1 mbar. The typical cycle time therefor (including flap movements, pumping down, transport of the carrier(s), flooding, transport of next carrier(s)) is 25 s-120 s. Optionally, multi-stage loadlocks can also be used for the introduction, i.e., an extension by a further chamber which also runs in cycle mode, but in which the vacuum is brought from approximately 1 mbar to, for example, 10.sup.−4 mbar.

[0117] Optionally, the wafers are then subjected to a cleaning process by excited gas in the plasma (DC glow or RF bias indirectly at the chamber or atom/ion sources directed at the wafers).

[0118] For the further production in a continuous process, a continuous train is then formed from a plurality of substrate carriers, as already explained above. This train formation takes place in the so-called extension chamber (which is part of the process space). This train of essentially directly adjacent substrate carriers, on which the wafers are supported, is passed under the sputtering cathodes at a constant speed, whereby the coating can be used efficiently, since no coating material is lost, for example, between successive wafers.

[0119] The cathodes used in the sputtering process can comprise planar or tubular targets as the sputtering targets. The following parameters are preferably used in the sputtering process: [0120] coating width: >600 mm, better>1,000 mm [0121] power: planar target: >3 W/cm.sup.2, preferably >5 W/cm.sup.2 [0122] tubular target: >6 kW/m, preferably >10 kW/m [0123] basic pressure for process: <5×10.sup.−5 mbar, better<10.sup.−6 mbar [0124] optionally: cold trap to freeze out the water [0125] working pressure for process: 10.sup.−4-10.sup.−2 mbar [0126] heated process area: heaters enable substrate temperature of at least 200° C., [0127] better>400° C.

[0128] If the tunnel oxide layer is also applied by means of sputtering (top side and/or bottom side of the wafer), the coating sequence according to the invention is: [0129] sputtering source(s) for deposition of the tunnel oxide (e.g. SiO.sub.2) [0130] gas separation due to O-containing gases [0131] sputtering source(s) for deposition of the intrinsic material (e.g. a-Si:H) [0132] sputtering source(s) for deposition of the highly doped material (e.g. a-Si:P)

[0133] Preferably, firstly the tunnel oxide is applied at the top and bottom, then a gas separation takes place, subsequently the other layers are applied at the top and bottom. For all coatings, the carriers are passed through the continuous processing machine in a continuous train.

[0134] After coating with the layers according to the invention, the train is disintegrated again i.e., separated into individual substrate carriers (or substrate carrier groups), since this simplifies their removal.

[0135] The removal then takes place analogously or inversely to the introduction, unloading takes place either before or after the return transport of the carriers.