Semiconductor Device and Method of Driving the Semiconductor Device

Abstract

Display irregularities in light emitting devices, which develop due to dispersions per pixel in the threshold value of TFTs for supplying electric current to light emitting elements, are obstacles to increasing the image quality of the light emitting devices. An electric potential in which the threshold voltage of a TFT (105) is either added to or subtracted from the electric potential of a reset signal line (110) is stored in capacitor means (108). A voltage, in which the corresponding threshold voltage is added to an image signal, is applied to a gate electrode of a TFT (106). TFTs within a pixel are disposed adjacently, and dispersion in the characteristics of the TFTs does not easily develop. The threshold value of to the TFT (105) is thus cancelled, even if the threshold values of the TFTs (106) differ per pixel, and a predetermined drain current can be supplied to an EL element (109).

Claims

1. (canceled)

2. A semiconductor device comprising: a light-emitting element; a first transistor; a second transistor; a first capacitor; and a second capacitor, wherein one of a source and a drain of the first transistor is electrically connected to the light-emitting element, wherein the other of the source and the drain of the first transistor is electrically connected to an electric current supply line, wherein a first electrode of the first capacitor is electrically connected to a gate of the first transistor, wherein a second electrode of the first capacitor is electrically connected to one of a source and a drain of the second transistor, wherein the other of the source and the drain of the second transistor is electrically connected to a source signal line, wherein a first electrode of the second capacitor is electrically connected to the gate of the first transistor, and wherein a second electrode of the second capacitor is electrically connected to the electric current supply line.

3. The semiconductor device according to claim 2, further comprising a third transistor, wherein one of a source and a drain of the third transistor is electrically connected to the light-emitting element, and wherein the other of the source and the drain of the third transistor is electrically connected to an electric power source line.

4. The semiconductor device according to claim 2, further comprising a fourth transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor.

5. The semiconductor device according to claim 4, wherein the other of the source and the drain of the fourth transistor is electrically1 connected to the source signal line.

6. The semiconductor device according to claim 2, further comprising a fifth transistor, wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor, and wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor.

Description

BRIEF DESCRIPTION OF THE DRAWING

[0340] In the accompanying drawings:

[0341] FIGS. 1A and 1B are diagrams for explaining an embodiment mode of the present invention, and operation of the embodiment mode;

[0342] FIGS. 2A to 2E are diagrams for explaining an embodiment mode of the present invention, and operation of the embodiment mode;

[0343] FIGS. 3A to 3E are diagrams for explaining an embodiment mode of the present invention, and operation of the embodiment mode;

[0344] FIGS. 4A to 4C are diagrams for explaining an embodiment mode of the present invention, and operation of the embodiment mode;

[0345] FIGS. 5A to 5C are diagrams for explaining an embodiment mode of the present invention, and operation of the embodiment mode;

[0346] FIGS. 6A to 6C are diagrams for explaining an embodiment mode of the present invention, and operation of the embodiment mode;

[0347] FIGS. 7A to 7D are diagrams for explaining an embodiment mode of the present invention, and operation of the embodiment mode;

[0348] FIG. 8 is a diagram showing the structure of a pixel in a general light emitting device;

[0349] FIGS. 9A to 9C are diagrams for explaining a method combining a digital gray scale method and a time gray scale method;

[0350] FIGS. 10A and 10B are diagrams for explaining an example of a pixel of a light emitting device capable of correcting dispersions in TFT threshold values, and operation of the light emitting device pixel;

[0351] FIGS. 11A to 11F are diagrams for explaining an example of a pixel of a light emitting device capable of correcting dispersions in TFT threshold values, and operation of the light emitting device pixel; to FIGS. 12A to 12C are diagrams for explaining operation when a method combining a digital gray scale method and a time gray scale method is used in the present invention;

[0352] FIGS. 13A to 13H are diagrams showing examples of electronic equipment capable of applying the present invention;

[0353] FIGS. 14A to 14E are diagrams for explaining the operating principle of the present invention;

[0354] FIGS. 15A to 15C are an upper surface diagram and cross sectional diagrams of a light emitting device;

[0355] FIGS. 16A and 16B are diagrams for explaining an embodiment mode of the present invention, and operation of the embodiment mode;

[0356] FIGS. 17A to 17E are diagrams for explaining an embodiment mode of the present invention, and operation of the embodiment mode;

[0357] FIGS. 18A to 18C are diagrams for explaining an outline of a light emitting device using an analog signal method;

[0358] FIGS. 19A and 19B are diagrams showing examples of the structure of a source signal line driver circuit and a gate signal line driver circuit, respectively, used in FIGS. 18A to 18C;

[0359] FIGS. 20A and 20B are diagrams for explaining an outline of a light emitting device using a digital signal method;

[0360] FIGS. 21A and 21B are diagrams showing examples of the structure of a source signal line driver circuit and a gate signal line driver circuit, respectively, used in FIGS. 20A to 20C;

[0361] FIG. 22 is a diagram showing an example of a layout of pixels having the structure shown in FIGS. 1A and 1B;

[0362] FIGS. 23A and 23B are diagrams showing examples of the structure of an electric current source circuit using the threshold value correcting principle of the present invention;

[0363] FIGS. 24A and 24B are diagrams showing examples of the structure of an electric current source circuit using the threshold value correcting principle of the present invention;

[0364] FIGS. 25A and 25B are diagrams showing examples of the structure of an electric current source circuit using the threshold value correcting principle of the present invention; and

[0365] FIGS. 26A and 26B are diagrams showing examples of the structure of an electric current source circuit using the threshold value correcting principle of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiment Mode 1

[0366] Embodiment Mode 1 of the present invention is shown in FIG. 1A. Embodiment Mode 1 has a source signal line 101, a first gate signal line 102, a second gate signal line 103, TFTs 104 to 107, capacitor means 108, an EL element 109, a reset electric power source line 110, an electric current supply line 111, and an electric power source line 112. In addition, a storage capacitor means 113 for storing an image signal may also be formed.

[0367] A gate electrode of the TFT 104 is connected to the first gate signal line 102, a first electrode of the TFT 104 is connected to the source signal line 101, and a second electrode of the TFT 104 is connected to a first electrode of the capacitor means 108. A gate electrode and a first electrode of the TFT 105 are connected with each other, and also connected to a second electrode of the capacitor means 108. A second electrode of the TFT 105 is connected to the reset electric power source line 110. A gate electrode of the TFT 106 is connected to the second electrode of the capacitor means 108, and to the gate electrode and the first electrode of the TFT 105. A first electrode of the TFT 106 is connected to the electric current supply line 111, and a second electrode of the TFT 106 is connected to a first to electrode of the EL element 109. A second electrode of the EL element 109 is connected to the electric power source line 112, and has a mutual electric potential difference with the electric current supply line 111. A gate electrode of the TFT 107 is connected to the second gate signal line 103, a first electrode of the TFT 107 is connected to the source signal line 101, and a second electrode of the TFT 107 is connected to the gate electrode of the TFT 106. When forming the storage capacitor means 113, formation is possible between the gate electrode of the TFT 106 and a position at which a fixed electric potential can be obtained, such as the electric current supply line 111.

[0368] FIG. 1B shows the timing at which pulses are input to the first and the second gate signal lines. Operation is explained using FIGS. 1A and IB, and FIGS. 2A to 2D. Note that although a structure is used here wherein the TFTs 104 and 107 are n-channel TFTs, and the TFTs 105 and 106 are p-channel TFTs, the TFTs 104 and 107 may have any polarity, provided that they function as simple switching elements.

[0369] The electric potential of the reset electric power source line 110 is V.sub.Reset, and the electric potential of the electric current supply line 111 is V.sub.DD, where V.sub.Reset<V.sub.DD. The electric potential of the source signal line 101 first becomes V.sub.SS (where V.sub.SS<V.sub.Reset), and in addition, the second gate signal line 103 becomes H level and the TFT 107 turns on. The electric potentials of the gate electrodes of the TFTs 105 and 106 thus drop. The voltage between the gate and the source of the TFT 106 soon becomes less than the threshold value, and the TFT 106 turns on. The voltage between the gate and the source of the TFT 105 also becomes less than the threshold value, and the TFT 105 also turns on (see FIG. 2A). Although the TFT 104 is off in FIG. 2A at this point, it may also be on during this period.

[0370] An electric current path develops from the reset electric power source line 110 to the TFT 105 to the TFT 107 and to the source signal line 101 when the TFT 105 turns on. The to second gate signal line 103 therefore becomes L level after the TFT 105 turns on, and the TFT 107 turns off. The first gate signal line 102 becomes H level at the same time, and the TFT 104 turns on. Electric charge thus moves as shown in FIG. 2B. The TFT 105 is on, and therefore the electric potentials of the gate electrodes of the TFTs 105 and 106 increase. The gate and the drain of the TFT 105 are connected here, and therefore the TFT 105 turns off at the point when the voltage between the gate and the source of the TFT 105, that is, the voltage between the source and the drain of the TFT 105, becomes equal to the threshold value. The electric potentials of the gate electrodes of the TFTs 105 and 106 is (V.sub.Reset−|V.sub.th|) at this point. In focusing on the capacitor means 108, however, electric charge accumulates such that the voltage between both electrodes of the capacitor means 108 becomes (V.sub.Reset−|V.sub.th|).

[0371] An image signal is then input from the source signal line 101 (see FIG. 2C). The electric potential of the source signal line 101 changes by Vpata from Vss. The electric potentials of the gate electrodes of the TFTs 105 and 106 also change by VDat 3 due to capacitive coupling with the capacitor means 108. The TFT 105 should not tum on at this point. Conditions of the values of VData at this point are discussed below. On the other hand, the electric potential of the source of the TFT 106 is V.sub.DD (where V.sub.DD>V.sub.Reset), and the voltage between the gate and the source of the TFT 106 becomes (V.sub.Reset−|V.sub.th|+V.sub.Data−V.sub.DD). A drain current corresponding to the voltage between the gate and the source of the TFT 106 is supplied to the EL element 109, and light is emitted (see FIG. 2D).

[0372] The relationship between the sizes of the electric potential V.sub.Reset of the reset electric power source line 110, the electric potential V.sub.DD of the electric current supply line 111, the electric potential of the source signal line 101, and the image signal V.sub.Data is explained here using FIG. 2E.

[0373] First of all, the fixed electric potential size relationship follows V.sub.SS<V.sub.Reset<V.sub.DD.

[0374] Next, consider the electric potentials of the gate electrodes of the TFTs 105 and 106.

[0375] The electric potentials of the gate electrodes of the TFTs 105 and 106 become the electric potential shown by symbol [1] in FIG. 2E due to the initialization of FIG. 2A, that is, V.sub.SS. The electric potentials of the gate electrodes of the TFTs 105 and 106 rise in the period during which storage of the threshold value is performed, and finally arrive at the electric potential shown by symbol [2] in FIG. 2E, that is, (V.sub.Reset−|V.sub.th|). The electric potentials then additionally change by V.sub.Data from the potential shown by symbol [2] when the image signal is input. The electric potentials of the gate electrodes of the TFTs 105 and 106 become lower than the electric potential of symbol [2] in the case where V.sub.Data is a negative value. That is, the voltage between the gate and the source of the TFT 105 becomes lower than the threshold value, and the TFT 105 turns on, and this is contrary to the previous conditions. It is therefore necessary for V.sub.Data to be a positive value. The electric potentials of the TFTs 105 and 106 become electric potentials shown by symbol [3] in FIG. 2E due to the input image signal, that is, (V.sub.Reset−|V.sub.th|+V.sub.Data). Further, the TFT 106 turns off if the electric potential of the gate electrode of the TFT 106 becomes higher than V.sub.DD−|V.sub.th|, and therefore the range of electric potential values which the image signal V.sub.Data is capable of taking is the range denoted by reference numeral 200 in FIG. 2E. In other words, it is necessary that the following relationship be true: 0≤V.sub.Data≤V.sub.DD−V.sub.Reset (preferably, 0<V.sub.Data≤V.sub.DD−V.sub.Reset to ensure that the TFT 105 turns off). However, at a gray scale 0, that is, when the EL element 109 is in a state of absolutely no light emission, an electric potential that is slightly higher than the electric potential at which the TFT 106 turns off, in other words, slightly higher than (V.sub.DD−V.sub.Reset), may be applied.

[0376] The closer V.sub.Data comes to zero at this point, the larger the absolute value of the voltage between the gate and the source of the TFT 106, and therefore the higher the brightness of the EL element 109 becomes. The larger VData becomes, the smaller the absolute value of the voltage between the gate and the source of the TFT 106 becomes, and therefore the brightness of the EL element 109 is low.

[0377] Display of an image is performed by performing the above operations over one screen. Storage of the threshold value is accomplished in the present invention by using only the capacitor means 108, and therefore it is possible to perform accurate correction of the threshold value without dispersion in the capacitance values influencing the value of electric current flowing in the EL elements 109, as discussed above.

Embodiment Mode 2

[0378] A digital gray scale method for controlling the EL element 109 in only two states, one having a brightness of 100% and one a brightness of 0%, by using a region in which it is difficult for TFT threshold values and the like to influence the on electric current is proposed as a method differing from the analog gray scale method discussed above. Only two gray scales, white and black, can be achieved by this method, and therefore multiple gray scales are realized by combining this method with a time gray scale method, a surface area gray scale method, or the like.

[0379] The term time gray scale method refers to a method in which a visible brightness difference can be achieved by utilizing a difference in the amount of time that the EL elements 109 emit light. The operation of this method will be described in detail in another section of this specification, and only two states of the EL elements 109, that is, light emission and non-light emission, need to be used with this type of driving method. Therefore only two electric potentials need to be imparted by the image signal V.sub.Data, that is, H level and L level.

[0380] The TFT 106 is a p-channel TFT here, and therefore the EL element 109 emits light when V.sub.Data is L level, and the EL element 109 does not emit light when V.sub.Data is H level. From the conditions of V.sub.Data shown in Embodiment Mode 1, the electric potential is in the range shown by the reference numeral 200 in FIG. 2E and as much electric current as possible can be supplied to the EL element 109 at this point when V.sub.Data is L level. In addition, an electric potential at which the TFT 105 does not turn on may also be used. In other words, an electric potential equal to, or slightly greater than, (V.sub.Reset−|Vth|) may be used. On the other hand, an electric potential able to ensure that the TFT 106 turns off may be used when V.sub.Data is H level. It is not particularly necessary that the electric potential be in the range denoted by the reference numeral 200 for this case. Rather, it is desirable that an electric potential higher than the range denoted by the reference numeral 200 (for example, VDD or the like) be input.

Embodiment Mode 3

[0381] An example in which some TFT connections differ is shown in FIG. 3A as a third embodiment mode. Although generally similar to the structure shown in FIG. 1A, there is a difference in that a first electrode of a TFT 307 is connected to a second electrode of a TFT 304, not to a source signal line.

[0382] Operation is explained following FIGS. 3B to 3E. The electric potential of a reset electric power source line 310 is V.sub.Reset, and the electric potential of an electric current supply line 311 is V.sub.DD, such that V.sub.Reset<V.sub.DD. First, the electric potential of a source signal line 301 becomes Vss (where V.sub.SS<V.sub.Reset), and in addition, first and second gate signal lines 302 and 303 become H level, while TFTs 304 and 307 turn on. The electric potentials of gate electrodes of TFTs 305 and 306 thus drop. The voltage between the gate and the source of to the TFT 305 soon becomes lower than the threshold value of the TFT 305, which turns on, and the voltage between the gate and the source of the TFT 306 becomes lower than the threshold value of the TFT 306, which also turns on (see FIG. 3B).

[0383] An electric current path from the reset electric power source line 310 to the TFT 305, to the TFT 307, to the TFT 304, and to the source signal line 301 develops due to the TFT 305 turning on. The second gate signal line 303 therefore becomes L level immediately after both the TFTs 305 and 306 turn on, and the TFT 307 turns off. Movement of electric charge as shown in FIG. 3C thus develops. The TFT 305 is on, and therefore the electric potentials of the gate electrodes of the TFTs 305 and 306 rise. The gate and the drain of the TFT 305 are connected here, and therefore the TFT 305 turns off at the point when the voltage between the gate and the source of the TFT 305, that is the voltage between the source and the drain of the TFT 305, becomes equal to the threshold value V.sub.th. The electric potentials of the gate electrodes of the TFTs 305 and 306 are (V.sub.Reset−|V.sub.th|) at this point. In focusing on the capacitor means 308, however, electric charge accumulates by the amount that the electric potential of the second electrode changes.

[0384] An image signal is then input from the source signal line 301 (see FIG. 3D). The electric potential of the source signal line 301 changes by V.sub.Data from V.sub.SS. The electric potentials of the gate electrodes of the TFTs 305 and 306 also change by V.sub.Data due to capacitive coupling with the capacitor means 308. The TFT 305 does not turn on at this point. On the other hand, the electric potential of the source of the TFT 306 is V.sub.DD (where V.sub.DD>V.sub.Reset), and the voltage between the gate and the source of the TFT 306 becomes (V.sub.Reset−|V.sub.th|+V.sub.Data−V.sub.DD). A drain current corresponding to the voltage between the gate and the source of the TFT 306 is supplied to the EL element 309, and light is emitted (see FIG. 3E).

Embodiment Mode 4

[0385] A method of combining a digital gray scale method and a time gray scale method is explained here. The structure of a pixel shown in FIG. 9A is an example that can be employed by driving with using this type of method. It becomes possible to minutely control the length of time during which light is emitted by using an erasure TFT 906 in addition to a switching TFT 904, and a driver TFT 905.

[0386] One frame period is divided into a plurality of subframe periods when combining a digital gray scale method and a time gray scale method, as shown in FIG. 9B. Each of the subframe periods has an address (write in) period and a sustain (light emitting) period as shown in FIG. 9C, and in addition, an erasure period if necessary. A method of gray scale expression may be used, for example, in which the number of subframe periods are formed corresponding to the number of display bits, and the lengths of the sustain (light emitting) period in each of the subframe periods are taken as 2.sup.(n-1): 2.sup.(n-2): . . . :2:1. Light emission or non-light emission by the EL element is selected for each sustain (light emitting) period, and gray scale expression is performed by utilizing the difference in the lengths of the total time during which the EL element emits light in one frame period. It is recognized that brightness increases with a longer total light emitting period, and brightness decreases with a shorter total light emitting period. A 1-bit gray scale example is shown in FIG. 9B, and one frame period is divided into four subframe periods. By combining the subframe periods with sustain (light emitting) periods, 2.sup.4=16 gray scales can be expressed. Note that the number of divisions of the frame period is not limited to four, and that it is also possible to further divide the frame period into more subframe periods.

[0387] Further, it is not always necessary that the relative lengths of the sustain (light emitting) periods during gray scale expression be 2.sup.(n-1):2.sup.(n-2): . . . :2:1.

[0388] The length of the sustain (light emitting) period of lower bits becomes very short when forming multiple gray scales by this method, and therefore a period develops, after the sustain (light emitting) period is complete and the next address period immediately begins, during which address (write in) periods of different subframe periods overlap. In this case, an image signal input to a certain pixel is also input at the same time to different pixels, and correct display therefore cannot be performed. The erasure period is formed in order to solve this problem, and is formed after Ts3 and Ts4 in FIG. 9B so that address (write in) periods belonging to adjacent subframe periods do not overlap. Erasure periods are not formed in SF1 and SF2, which have long sustain (light emitting) periods and in which there is no concern that address (write in) periods belonging to adjacent subframe periods will overlap.

[0389] FIG. 1A shows a method of combining a digital gray scale method and a time gray scale method, wherein a third gate signal line 414 and an erasure TFT 415 are added to the pixel structure shown in Embodiment Mode 1. A gate electrode of the erasure TFT 415 is connected to the third gate signal line 414, a first electrode of the erasure TFT 415 is connected to a gate signal line of a TFT 406, and a second electrode of the erasure TFT 415 is connected to an electric current supply line 411. Further, in the case where a storage capacitor means 413 for storing an image signal is formed, it may be formed between a gate electrode of the TFT 406 and a location at which a fixed electric potential can be obtained. The storage capacitor means 413 is formed between the gate electrode of the TFT 406 and the electric current supply line 411 in FIGS. 4A to 4C, but it may also be formed, for example, between the gate electrode of the TFT 406 and a prior stage gate signal line. Further, it may also be formed between a second electrode of the TFT 404 and a fixed electric potential such as the electric current supply line 411, and it may be formed on both if there is a desire to to make the storage capacitance larger.

[0390] Operations from initialization, to input of an image signal, and to light emission is similar to the explanation provided in Embodiment Mode 1. Note that the erasure TFT 415 is off during initialization, input of the image signal, and the sustain (light emitting) period.

[0391] Operation from the sustain (light emitting) period to the erasure period is explained here using FIGS. 4A to 4C, and FIGS. 12A to 12C. FIG. 12A is similar to the diagram shown in FIG. 9B, and one frame period has four subframe periods. Subframe periods SF3 and SF4, which have short sustain (light emitting) periods, each have erasure periods Te3 and Te4, as shown in FIG. 12B. Operation during the sustain period SF 3 is taken as an example here for explanation.

[0392] Electric current corresponding to the voltage between the gate and the source of the TFT 406 flows in the EL element 409 as shown in FIG. 4B after input of the image signal is complete. A pulse is then input to the third gate signal line 414 when a timing for completion of the corresponding sustain (light emitting) period is complete, the third gate signal line 416 becomes H level, and the TFT 415 turns on. The voltage between the gate and the source of the TFT 406 is zero, as shown in FIG. 4C. The TFT 406 thus turns off by this operation, and electric current to the EL element 409 is cut off. The EL element 409 is therefore forcibly placed in a non-light emitting state.

[0393] The timing chart for these operations is shown in FIG. 12C. Periods for performing initialization, threshold value storage, and write in of the image signal are contained in the address (write in) period. A period beginning after a pulse is input to the third gate signal line 414 after the sustain (light emitting) period and the EL element 409 becomes non-light emitting, up through when a pulse is next input to the second gate signal line 403 and initialization begins, is the erasure period.

Embodiment Mode 5

[0394] An example of performing erasure operations using a structure that differs from the structure of Embodiment Mode 4 is explained using FIGS. 5A to 5C in Embodiment Mode 5.

[0395] FIG. 5A shows a structure having the erasure TFT 415, similar to Embodiment Mode 4. However, although the first electrode of the TFT 415 is connected to the gate electrode of the TFT 406, namely to a second electrode of capacitor means 408 in Embodiment Mode 4, the first electrode of the TFT 415 is connected to a first electrode of the capacitor means 408 in FIG. 5.

[0396] Electric current corresponding to the voltage between the gate and the source of the TFT 406 flows in the EL element 409 as shown in FIG. 5B after input of the image signal is complete. A pulse is then input to the third gate signal line 414, which becomes H level, when a timing for completion of the corresponding sustain (light emitting) period is reached, and the TFT 415 turns on. The electric potential of the first electrode of the capacitor means 408 becomes V.sub.DD, as shown in FIG. 5C. The electric potential of the gate electrode of the TFT 406 consequently becomes higher than V.sub.DD, and therefore the voltage between the gate and the source becomes a positive value. The TFT 406 thus turns off by this operation, electric current to the EL element 409 is cut off, and the EL element 409 is forcibly placed in a non-light emitting state.

[0397] Operations during the erasure period are such that electric current to the EL element 409 is cut off by making the voltage between the gate and the source of the TFT 406, which functions as a driver TFT in order to supply electric current to the EL element 409, a voltage at which the TFT 406 turns off. Provided that operation is based upon this principle, there are no limitations placed on the placement of the erasure TFT 415.

Embodiment Mode 6

[0398] Operation during the erasure period in Embodiment Modes 4 and 5 is such that electric current to the EL element 409 is cut off by making the voltage between the gate and the source of the TFT 406, which functions as a driver TFT for supplying electric current to the EL element 409, a voltage at which the TFT 406 turns off An example of using another method is shown in FIG. 6A. The erasure TFT 415 is formed between the electric current supply line 411 and the gate electrode of the TFT 406, or between the electric current supply line 411 and the first electrode of the capacitor means 408 in Embodiment Modes 4 and 5. However, the erasure TFT 415 is formed between the TFT 406 and the EL element 409 in Embodiment Mode 6. That is, a TFT is added in any place of the pathway from the electric current supply line to the TFT 406 and to the EL element 409 with the method of Embodiment Mode 6, and the supply of electric current to the EL element 409 is cut off by turning this TFT off.

[0399] Initialization, input of an image signal, and light emission are similar to those of Embodiment Modes 4 and 5. However, the erasure TFT 415 is on only during the sustain (light emitting) period, and electric current flows as shown in FIG. 6B. The TFT 415 is off during initialization, input of the image signal, and during the erasure period, and electric current to the EL element 409 is cut off during these periods.

[0400] Differences in operation between Embodiment Mode 6 and Embodiment Modes 4 and 5 are explained. The voltage between the gate and the source of the TFT 406 is controlled by turning the erasure TFT 415 on once in Embodiment Modes 4 and 5, and therefore the EL element 409 does not emit light after this operation is performed until the next image signal is written in. Consequently, pulses input to the third gate signal line 414 may be short pulses to input at a timing at which the erasure period begins, as shown in FIG. 12C. In Embodiment Mode 6, however, it is necessary for the erasure TFT 415 to be on throughout the sustain (light emitting) period, and therefore it is necessary to input pulses to the third gate signal line 415, the pulses lengths equal to the sustain (light emitting) periods, for each of the subframe periods.

[0401] Further, although the erasure TFT 415 uses an n-channel TFT in Embodiment Modes 4, 5, and 6, there are no particular limitations placed on the polarity in Embodiment Mode 6 because the erasure TFT 415 functions solely as a switching element.

Embodiment Mode 7

[0402] Initialization operations prior to the input of image signals are performed by using a certain TFT in Embodiment Modes 1 to 6. Specifically, a threshold value appearing between the source and the drain of a TFT, which has a connection between a gate electrode and a drain electrode, is obtained. In contrast, a diode 713 is used as a substitute for the TFT in FIG. 7A. A first electrode of the diode 713 is connected to a gate electrode of a TFT 706, and a second electrode of the diode 713 is connected to a second gate signal line 703. Further, if capacitor means 712 is formed in order to store image signals, then the capacitor means may be formed between the gate electrode of the TFT 706 and a location at which a fixed electric potential can be obtained, such as an electric current supply line 710. Furthermore, the capacitor means 712 may also be formed between a second electrode of a TFT 704 and a location at which a fixed electric potential can be obtained, such as the electric current supply line 710. The capacitor means may also be formed in both locations if a large value of storage capacitance is desired. Reference numerals 701, 707, 709 and 711 denote a source signal line, a capacitor means, a reset power source line and a power supply line, respectively. to Only operations during initialization differ from Embodiment Mode 1. Explanations regarding input of an image signal and light emitting operations are omitted here. Operations during initialization are explained using FIG. 7B.

[0403] First, the electric potential of the second gate signal line 703 is set to H level (for example, V.sub.DD. A forward bias is then imparted to the diode 713 if the electric potential of the second gate signal line 703 is set to L level (for example, V.sub.SS) at the initialization timing. Electric current develops as shown in FIG. 7B from nodes having a high electric potential to nodes having a low electric potential, and the electric potential of a gate electrode of a TFT 705, and the electric potential of the gate electrode of the TFT 706, drop The voltage between the gate and the source of the TFT 705 soon becomes lower than the threshold voltage, and the TFT 705 turns on. Thereafter, the voltage between the gate and the source of the TFT 706 becomes lower than the threshold voltage, and the TFT 706 also turns on. Initialization is complete at this point, and the electric potential of the second gate signal line 703 once again becomes H level. A reverse bias is imparted to the diode 713 at this point, and electric current does not flow during periods for performing image signal input and light emission operations.

[0404] Electric current corresponding to the input image signal then flows in the EL element 708, and the EL element 708 emits light, similar to Embodiment Mode 1.

[0405] FIG. 7C shows an example of forming capacitor means 714 as a substitute for the diode 713. A first electrode of the capacitor means 714 is connected to the gate electrode of to the TFT 706, and a second electrode of the capacitor means 714 is connected to the second gate signal line 703. Also in this case, operation is similar to that shown in FIG. 7B. First, the second gate signal line 703 is set to H level, and the electric potential of the second gate signal line 703 is set to L level at the initialization timing. The TFT 705 turns off at this point, and therefore the electric potentials of the gate electrodes of the TFTs 705 and 706 drop due to capacitive coupling with the capacitor means 714. The voltage between the gate and the source of the TFT 705 soon becomes lower than the threshold voltage, and the TFT 705 turns on. The voltage between the gate and the source of the TFT 706 then becomes lower than the threshold voltage, and the TFT 706 also turns on.

[0406] The TFT 704 then turns on, and input of an image signal is performed. The second gate signal line 703 is L level at this point, but may also be set to H level during input of the image signal.

[0407] Electric current corresponding to the input image signal then flows in the EL element 708, and the EL element 708 emits light, similar to Embodiment Mode 1.

Embodiment Mode 8

[0408] Display devices having an integrally formed pixel portion and peripheral circuits, formed by TFTs and the like built into a substrate, have the advantages of small size and light weight. However, their manufacturing processes are complex, such as element formation by repeatedly performing film formation and etching, and the addition of impurity elements for imparting conductivity to semiconductor layers. In particular, processes for adding impurity to elements differ between p-channel TFTs and n-channel TFTs, and this therefore invites further increases of processing.

[0409] Processes for adding impurity elements can be partly omitted by structuring the pixel portion and the peripheral circuits using TFTs having a single polarity. Not only does it thus become possible to shorten processing, but the number of photomasks can also be reduced.

[0410] An example of a structure that uses TFTs having a single polarity type is the structure disclosed in Japanese Patent Application No. 2001-348032 by the applicants of the present invention. This is a structure in which only n-channel TFTs having a high field-effect mobility are used, and in addition, a structure in which drops in brightness do not easily occur, even if EL elements deteriorate.

[0411] A structure provided with both advantages, that is a structure in which drops in

[0412] brightness following deterioration of EL elements are controlled, and one in which correction of dispersion in TFT threshold values is possible, is explained in Embodiment Mode 8 by combining the aforementioned technique with the present invention.

[0413] FIG. 16A shows an example structure. The structure has a source signal line 1601, a first gate signal line 1602, a second gate signal line 1603, a third gate signal line 1604, TFTs 1605 to 1609, capacitor means 1610 and 1611, an EL element 1612, a reset electric power source line 1613, an electric current supply line 1614, and electric power source lines 1615 and 1616. If a storage capacitor means 1617 is formed, it may be formed between a gate electrode of the TFT 1607 and a location at which a fixed electric potential can be obtained, such as the electric current supply line 1614.

[0414] A gate electrode of the TFT 1605 is connected to the first gate signal line 1602, a first electrode of the TFT 1605 is connected to the source signal line 1601, and a second electrode of the TFT 1605 is connected to a first electrode of the capacitor means 1610. A gate to electrode and a first electrode of the TFT 1606 are connected with each other, and then connected to a second electrode of the capacitor means 1610. A second electrode of the TFT 1606 is connected to the reset electric power source line 1613. The gate electrode of the TFT 1607 is connected to the gate electrode and the first electrode of the TFT 1606. A first electrode of the TFT 1607 is connected to the electric current supply line 1614, and a second electrode of the TFT 1607 is connected to a first electrode (anode) of the EL element 1612. A gate electrode of the TFT 1608 is connected to the second gate signal line 1603, a first electrode of the TFT 1608 is connected to the source signal line 1601, and a second electrode of the TFT 1608 is connected to the gate electrodes of the TFTs 1606 and 1607. A gate electrode of the TFT 1609 is connected to the third gate signal line 1604, a first electrode of the TFT 1609 is connected to the electric power source line 1616, and a second electrode of the TFT 1609 is connected to the first electrode (anode) of the EL element 1612. A second electrode (cathode) of the EL element 1612 is connected to the electric power source line 1615. A first electrode of the capacitor means 1611 is connected to the second electrode of the TFT 1605, and a second electrode of the capacitor means 1611 is connected to the first electrode (anode) of the EL element 1612.

[0415] Operation is explained following FIG. 16B and FIGS. 17A to 17E. A timing chart for pulses input into the first to the third gate signal lines 1602 to 1604, and for an image signal input to the source signal line 1601 is shown in FIG. 16B. The image signal is input at a timing denoted by symbol “V”, and at a predetermined electric potential.

[0416] The electric potential of the reset electric power source line 1613 is V.sub.Reset, the electric potential of the electric current supply line 1614 is V.sub.DD, the electric potential of the electric power source line 1615 is V.sub.C, and the electric potential of the electric power source line 1616 is V.sub.SS, where V.sub.SS<V.sub.C<V.sub.DD<V.sub.Reset. First, the electric potential of the source signal line 1601 is set to V.sub.x (where V.sub.x>V.sub.Reset). The second gate signal line 1603 and the third gate signal line 1604 then become H level, the TFTs 1608 and 1609 both turn on, an electric current develops as shown in FIG. 17A, and the electric potentials of the gate electrodes of the TFTs 1606 and 1607 rise. The voltage between the gate and the source of the TFT 1606 soon rises above the threshold value, and the TFT 1606 turns on. In addition, the voltage between the gate and the source of the TFT 1607 rises above the threshold value, and the TFT 1607 turns on. Initialization is thus complete by the above operations.

[0417] The second gate signal line becomes L level immediately after initialization is complete, and the TFT 1608 turns off. The electric potentials of the gate electrodes of the TFTs 1606 and 1607 thus begin to drop. The TFT 1606 turns off at the point where the electric potential becomes (V.sub.Reset+V.sub.th), that is when the voltage between the gate and the source of the TFT 1606 becomes equal to the threshold value. An electric potential difference thus develops between both electrodes of the capacitor means 1610, and this electric potential difference is stored.

[0418] On the other hand, the voltage between the gate and the source of the TFT 1607 at this point exceeds the threshold value, and therefore the TFT 1607 turns on. The TFT 1609 also turns on, and therefore electric current flows as shown in FIG. 17B in a pathway from the electric current supply line 1614, to the TFT 1607, to the TFT 1609, and to the electric power source line 1616. Electric current does not flow in the EL element 1612 at this point, however, because V.sub.SS<V.sub.C. The EL element 1612 therefore does not emit light.

[0419] Input of an image signal begins next. An image signal having a predetermined electric potential is input to the source signal line 1601, which is fixed to the electric potential V.sub.x, and the electric potential of the source signal line 1601 becomes (V.sub.x−V.sub.Data). The voltage between the gate and the source of the TFT 1606 becomes lower than the threshold to value, and the TFT remains off. On the other hand, the voltage between the gate and the source of the TFT 1607 becomes (V.sub.Reset+V.sub.th−V.sub.Data−V.sub.DD), and a drain current corresponding to this voltage flows (see FIG. 17C).

[0420] The first gate signal line 1602 becomes L level when input of the image signal is complete, and the TFT 1605 turns off. The third gate signal line 1604 then becomes L level, and the TFT 1609 turns off. Electric current flowing in the TFT 1607 thus flows in the EL element 1612, and light is emitted (see FIG. 17D).

[0421] An explanation regarding the relationship between the sizes of the electric potential V.sub.Reset of the reset electric power source line 1613, the electric potential V.sub.DD of the electric current supply line 1614, the electric potential of the source signal line 1601, and the image signal V.sub.Data is made here using FIG. 17E.

[0422] Consider the electric potentials of the gate electrodes of the TFTs 1606 and 1607. The electric potentials of the gate electrodes of the TFTs 1606 and 1607 become the electric potential denoted by symbol [1] in FIG. 17E due to the initialization of FIG. 17A. That is, the electric potentials become V.sub.x. The electric potentials of the gate electrodes of the TFTs 1606 and 1607 drop during a period for performing storage of the threshold values, and finally become the electric potential denoted by symbol [2] in FIG. 17E. That is, the electric potentials become (V.sub.Reset+|V.sub.th|). Subsequently, when an image signal is input, the electric potentials of the gate electrodes of the TFTs 1606 and 1607 further change by V.sub.Delta from the electric potential of symbol [2]. The electric potentials of the gate electrodes of the TFTs 1606 and 1607 becomes higher than the electric potential of symbol [2] here in the case where the change is positive. That is, the voltage between the gate and the source of the TFT 1606 becomes higher than the threshold voltage, and the TFT 1606 turns on, which is contrary to the prior conditions. It is therefore necessary that the change to the image signal be negative. to The electric potentials of the TFTs 1606 and 1607 therefore become an electric potential denoted by symbol [3] in FIG. 17E due to the input of the image signal. That is, the electric potentials become (V.sub.Reset+|V.sub.th|−V.sub.Data). Further, the electric potential of the gate electrode of the TFT 1607 becomes lower than VDD+|V.sub.th|, and the TFT 1607 turns off, and therefore a range of electric potentials at which the image signal V.sub.Data can be obtained is a range denoted by reference numeral 1700 in FIG. 17E. That is, it is necessary that 0≤V.sub.Data≤V.sub.Reset−V.sub.DD (preferably 0<V.sub.Data≤V.sub.Reset−V.sub.DD in order to ensure that the TFT 1606 is off). However, at a gray scale of zero, namely when the EL element 1612 is in a non-light emitting state, an electric potential slightly larger than (V.sub.Reset−V.sub.DD) may also be imparted as V.sub.Data SO as to ensure that the TFT 1607 turns off.

[0423] The closer V.sub.Data is to zero at this point, the higher the absolute value of the voltage between the gate and the source of the TFT 1607 becomes, and therefore the higher the brightness of the EL element 1612 becomes. The larger Vona becomes, the smaller the absolute value of the voltage between the gate and the source of the TFT 1607, and therefore the lower the brightness of the EL element 1612 becomes.

[0424] The above explanation is made for an example of performing display by an analog gray scale method, but display by a digital gray scale method like that disclosed by Embodiment Mode 2 can also be similarly made. Further, it is easy to combine Embodiment Mode 8 with a structure in which an erasure TFT is formed when using a time gray scale method.

Embodiments

[0425] Hereafter, the embodiments of the invention will be described.

Embodiment 1

[0426] In this embodiment, the configuration of a light-emitting device in which analog video signals are used for video signals for display will be described. A configuration example of the light-emitting device is shown in FIG. 18A. The device has a pixel portion 1802 wherein a plurality of pixels is arranged in a matrix shape over a substrate 1801, and it has a source signal line driver circuit 1803 and first and second gate signal line driver circuits 1804 and 1805 around the pixel portion. In FIG. 18A, two couples of gate signal line driver circuits are used, which control first and second gate signal lines.

[0427] Signals inputted to the source signal line driver circuit 1803, and the first and second gate signal line driver circuits 1804 and 1805 are provided from outside through a flexible printed circuit (FPC) 1806.

[0428] FIG. 18B shows a configuration example of the source signal line driver circuit. This is the source signal line driver circuit for using analog video signals for video signals for display, which has a shift register 1811, a buffer 1812, and a sampling circuit 1813. Not shown particularly, but a level shifter may be added if necessary.

[0429] The operation of the source signal line driver circuit will be described. FIG. 19A shows the more detailed configuration, thus referring to the drawing.

[0430] A shift register 1901 is formed of a plurality of flip-flop circuits (FF) 1902, to which the clock signal (S-CLK), the clock inverted signal (S-CLKb), and the start pulse (S-SP) are inputted. In response to the timing of these signals, sampling pulses are outputted sequentially.

[0431] The sampling pulses outputted from the shift register 1901 are passed through a buffer 1903 etc. and amplified, and then inputted to a sampling circuit. The sampling circuit 1904 is formed of a plurality of sampling switches (SW) 1905, which samples video signals in a certain column in accordance with the timing of inputting the sampling pulses. More specifically, when the sampling pulses are inputted to the sampling switches, the sampling switches 1905 are turned on. The potential held by the video signals at this time is outputted to the respective source signal lines through the sampling switches.

[0432] Subsequently, the operation of the gate signal line driver circuit will be described. FIG. 19B shows the more detailed configuration of the first and second gate signal line driver circuits 1804 and 1805 shown in FIG. 18C. The first gate signal line driver circuit has a shift register circuit 1911, and a buffer 1912, which is driven in response to the clock signal (G-CLK1), the clock inverted signal (G-CLKb1), and the start pulse (G-SP1). The second gate signal line driver circuit 2405 may have a same configuration.

[0433] The operation from the shift register to the buffer is the same as that in the source signal line driver circuit. The selecting pulses amplified by the buffer select respective gate signal lines for them. The first gate signal line driver circuit sequentially selects first gate signal lines G.sub.11, G.sub.21, . . . and G.sub.m1, and the second gate signal line driver circuit sequentially selects second gate signal lines G.sub.12, G.sub.22, . . . and G.sub.m2. A third gate signal line driver circuit, not shown, is also the same as the first and second gate signal line driver circuits, sequentially selecting third gate signal lines G.sub.13, G.sub.23, . . . and G.sub.m3. In the selected row, video signals are written in the pixel to emit light according to the procedures described in the embodiment mode.

[0434] Note that, as one example of the shift register that formed of a plurality of D-flip-flops is shown here. However, such the configuration is acceptable that signal lines can be selected by a decoder and the like.

Embodiment 2

[0435] In this embodiment, a configuration of a light-emitting device in which digital video signals are used for video signals for display will be described. FIG. 20A shows a configuration example of the light-emitting device. The device has a pixel portion 2002 wherein a plurality of pixels is arranged in a matrix shape over a substrate 2001, and it has a source signal line driver circuit 2003, and first and second gate signal line driver circuits 2004 and 2005 around the pixel portion. In FIG. 20A, two couples of gate signal line driver circuits are used, which control first and second gate signal lines.

[0436] Signals inputted to the source signal line driver circuit 2003, and the first and fourth gate signal line driver circuits 2004 and 2005 are supplied from outside through a flexible printed circuit (FPC) 2006.

[0437] FIG. 20B shows a configuration example of the source signal line driver circuit. This is the source signal line driver circuit for using digital video signals for video signals for display, which has a shift register 2011, a first latch circuit 2012, a second latch circuit 2013, and a D/A converter circuit 2014. Not shown in the drawing particularly, but a level shifter may be added if necessary.

[0438] The first and second gate signal line driver circuits 2004 and 2005 can be same as those shown in Embodiment 1, thus omitting the illustration and description here.

[0439] The operation of the source signal line driver circuit will be described. FIG. 21A shows the more detailed configuration, thus referring to the drawing.

[0440] A shift register 2101 is formed of a plurality of flip-flop circuits (FF) 2110 or the like, to which the clock signal (S-CLK), the clock inverted signal (S-CLKb), and the start pulse (S-SP) are inputted. Sampling pulses are sequentially outputted in response to the timing of these signals.

[0441] The sampling pulses outputted from the shift register 2101 are inputted to first latch circuits 2102. Digital video signals are being inputted to the first latch circuits 2102. The digital video signals are held at each stage in response to the timing of inputting the sampling pulses, Here, the digital video signals are inputted by three bits. The video signals at each bit are held in the respective first latch circuits. Here, three first latch circuits are operated in parallel by one sampling pulse.

[0442] When the first latch circuits 2102 finish to hold the digital video signals up to the last stage, latch pulses are inputted to second latch circuits 2103 during the horizontal retrace period, and the digital video signals held in the first latch circuits 2102 are transferred to the second latch circuits 2103 all at once. After that, the digital video signals held in the second latch circuits 2103 for one row are inputted to D/A converter circuits 2104 simultaneously.

[0443] While the digital video signals held in the second latch circuits 2103 are being inputted to D/A converter circuits 2104, the shift register 2101 again outputs sampling pulses. Subsequent to this, the operation is repeated to process the video signals for one frame.

[0444] The D/A converter circuits 2104 convert the inputted digital video signals from digital to analog and output them to the source signal lines as the video signals having the analog voltage.

[0445] The operation described above is conducted throughout the stages during one horizontal period. Accordingly, the video signals are outputted to the entire source signal lines.

[0446] Note that, as described in the Embodiment 1, such the configuration is acceptable that a decoder or the like is used instead of the shift register to select signal lines.

Embodiment 3

[0447] In Embodiment 2, the digital video signal is subjected to digital-to-analog conversion by the D/A converting circuit and written into the pixel. The light-emitting device of the present invention can also conduct gradation representation by a time gradation method. In this case, as shown in FIG. 21B, the D/A converting circuit is not required and the gradation representation is controlled according to a length of a light emitting time of the EL element. Thus, it is unnecessary to parallel-process video signals of respective bits so that the first and second latch circuits each may also have one bit. At this time, with respect to the digital video signal, each bit is serially inputted, held in succession in the latch circuit, and written into the pixel. Of course. the latch circuit of the required number of bits may be provided in parallel.

Embodiment 4

[0448] In this embodiment, an example in which a light-emitting device is manufactured according to the present invention will be described using FIGS. 15A to 15C.

[0449] FIG. 15A is a top view of a light-emitting device produced by sealing an element substrate in which TFTs are formed with a sealing member. FIG. 15B is a cross sectional view along a line A-A′ in FIG. 15A. FIG. 15C is a cross sectional view along a line B-B′ in FIG. 15A.

[0450] A seal member 4009 is provided to surround a pixel portion 4002, a source signal line driver circuit 4003, and first and second gate signal line driver circuits 4004a and 4004b which are provided on a substrate 4001. In addition, a sealing member 4008 is provided over the pixel portion 4002, the source signal line driver circuit 4003, and the first and second gate signal line driver circuits 4004a and 4004. Thus, the pixel portion 4002, the source signal line driver circuit 4003, and the first and second gate signal line driver circuits 4004 a to and 4004b are sealed with the substrate 4001, the seal member 4009 and the sealing member 4008 and filled with a filling agent 4210.

[0451] Also, the pixel portion 4002, the source signal line driver circuit 4003, and the first and second gate signal line driver circuits 4004a and 4004b which are provided on the substrate 4001 each have a plurality of TFTs. In FIG. 15B, TFTs (note that an N-channel TFT and a P-channel TFT are shown here) 4201 included in the source signal line driver circuit 4003 and a TFT 4202 included in the pixel portion 4002, which are formed on a base film 4010 are typically shown.

[0452] An interlayer insulating film (planarization film) 4301 is formed on the TFTs 4201 and 4202, and a pixel electrode (anode) 4203 electrically connected with the drain of the TFT 4202 is formed thereon. A transparent conductive film having a large work function is used as the pixel electrode 4203. A compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used for the transparent conductive film. In addition, the transparent conductive film to which gallium is added may be used.

[0453] An insulating film 4302 is formed on the pixel electrode 4203. An opening portion is formed in the insulating film 4302 on the pixel electrode 4203. In the opening portion, an organic light-emitting layer 4204 is formed on the pixel electrode 4203. An organic light emitting material or an inorganic light emitting material that is known can be used as the organic light-emitting layer 4204. In addition, the organic light emitting material includes a low molecular weight based (monomer system) material and a high molecular weight based (polymer system) material, and any material may be used.

[0454] An evaporation technique or an applying method technique that is known is to preferably used as a method of forming the organic light-emitting layer 4204. In addition, a laminate structure or a single layer structure which is obtained by freely combining a hole injection layer, a hole transporting layer, a light emitting layer, an electron transporting layer, and an electron injection layer is preferably used as the structure of the organic light emitting layer.

[0455] A cathode 4205 made from a conductive film having a light shielding property (typically, a conductive film containing mainly aluminum, copper, or silver, or a laminate film of the conductive film and another conductive film) is formed on the organic light emitting layer 4204. In addition, it is desirable that moisture and oxygen that exist in an interface between the cathode 4205 and the organic light-emitting layer 4204 are minimized. Thus, a devise is required in which the organic light emitting layer 4204 is formed in a nitrogen atmosphere or a noble atmosphere and the cathode 4205 without being exposed to oxygen and moisture is formed. In this embodiment, the above film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus. A predetermined voltage is supplied to the cathode 4205.

[0456] By the above steps, a light-emitting element 4303 composed of the pixel electrode (anode) 4203, the organic light emitting layer 4204, and the cathode 4205 is formed. A protective film 4209 is formed on the insulating film 4302 so as to cover the light-emitting element 4303. The protective film 4209 is effective to prevent oxygen, moisture, and the like from penetrating the light-emitting element 4303.

[0457] Reference numeral 4005 a denotes a lead wiring connected with a power source, which i0s connected with a first electrode of the TFT 4202. The lead wiring 4005a is passed between the seal member 4009 and the substrate 4001 and electrically connected with an FPC wiring 4301 of an FPC 4006 through an anisotropic conductive film 4300.

[0458] A glass material, a metallic member (typically, a stainless member), a ceramic member, a plastic member (including a plastic film) can be used as the sealing member 4008. An FRP (fiberglass reinforced plastic) plate, a PVF (polyvinyl fluoride) film, a Mylar film, a polyester film, or an acrylic resin film can be used as the plastic member. In addition, a sheet having a structure in which aluminum foil is sandwiched by a PVF film and a Mylar film can be used.

[0459] Note that, it is required that the cover member is transparent to the light when the light generated at the light-emitting element is emitted through a cover member side. In this case, a transparent material such as a glass plate, a plastic plate, a polyester film, or acrylic film is used.

[0460] Also, in addition to an inert gas such as nitrogen or argon, ultraviolet curable resin or thermal curable resin can be used for the filling agent 4103. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicon resin, PVB (polyvinyl butvral), or EVA (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used for the filling agent.

[0461] Also, in order to expose the filling agent 4103 to a hygroscopic material (preferably barium oxide) or a material capable of absorbing oxygen, a concave portion 4007 is provided to the surface of the sealing member 4008 in the substrate 4001 side, and the hygroscopic material or the material capable of absorbing oxygen which is indicated by 4207 is located. In order to prevent the material 4207 having a hygroscopic property or being capable of absorbing oxygen from flying off, the material 4207 having a hygroscopic property or being capable of absorbing oxygen is held in the concave portion 4007 by a concave cover member 4208. Note that concave cover member 4208 is formed in a fine meshed shape and constructed such that it transmits air and moisture but does not transmit the material 4207 having a hygroscopic property or being capable of absorbing oxygen. When the material 4207 having a hygroscopic property or being capable of absorbing oxygen is provided, the deterioration of the light-emitting element 4303 can be suppressed.

[0462] As shown in FIG. 15C, a conductive film 4203a is formed on the lead wiring 4005a such that it is in contact with the lead wiring 4005a simultaneously with the formation of the pixel electrode 4203.

[0463] Also, the anisotropic conductive film 4300 has a conductive filler 4300a. When the substrate 4001 and the FPC 4006 are bonded to each other by thermal compression, the conductive film 4203a located over the substrate 4001 and the FPC wiring 4301 located on the FPC 4006 are electrically connected with each other through the conductive filler 4300a.

Embodiment 5

[0464] An example of manufacturing pixels actually by using the configuration shown in FIG. 1A is demonstrated with reference to FIG. 22. A portion surrounded by a dotted line frame 2200 represents one pixel. Another figure numbers are the same as those assigned in FIG. 1A.

[0465] A source signal line 101, a reset power source line 110, and a current supply line 111 are formed by using a same layer material for forming a gate electrode. First and second gate signal lines 102 and 103 are formed by using a wiring material.

[0466] The pixel electrode 120 serves as a transparent electrode here, and connects to a drain electrode of TFT 106. The pixel electrode 120 and the drain electrode of TFT 106 contact each other without through a contact hole by means of overlapping directly a to transparent conductive film forming a pixel electrode 120 and wiring materials. Of course, another method may be used to contact the drain electrode of TFT 106 and the pixel electrode 120.

[0467] Though a capacity device 108 and a retention capacity device 113 are formed at between the gate materials and the wiring materials, it is not especially limited to this type. For ease of illustration, a channel length L and a channel width W of TFTs 104 to 107 are not illustrated as to correspond to the actual sizes. It is possible that the desired size of L and W is determined at the designing phase and that each TFT differs in size.

Embodiment 6

[0468] A light-emitting device using a light-emitting element is a self light emission type.

[0469] Thus, such a light-emitting device has high visibility in a light place and a wide viewing angle, as compared with a liquid crystal display. Therefore, it can be used for a display portion of various electronic apparatuses.

[0470] As electronic apparatuses using the light-emitting device of the present invention, there are a video camera, a digital camera, a goggle type display (head mount display), a navigation system, a sound reproducing device (car audio system, audio component system, or the like), a laptop computer, a game machine, a portable information terminal (mobile computer, mobile telephone, portable game machine, an electric book, or the like), an image reproducing device including a recording medium (specifically, apparatus for reproducing an image from a recording medium such as a digital versatile disc (DVD), which includes a display capable of displaying the image), and the like. In particular, in the case of the portable information terminal in which a screen is viewed from an oblique direction in many to cases, it is important that a view angle is large. Thus, it is desirable that the light-emitting device is used. Concrete examples of those electronic apparatuses are shown in FIGS. 13A to 13H.

[0471] FIG. 13A shows a light emitting element display device which includes a cabinet 3001, a support base 3002, a display portion 3003, a speaker portion 3004, and a video input terminal 3005. The light-emitting device of the present invention can be used for the display portion 3003. The light-emitting device is a self light emission type and thus does not require a back light. Therefore, a thinner display portion than a liquid crystal display can be obtained. Note that the light-emitting element display device includes all display devices for information display such as personal computer, TV broadcast receiving, and advertisement display.

[0472] FIG. 13B is a digital still camera, which is composed of a main body 3101, a display portion 3102, an image-receiving portion 3103, operation keys 3104, external connection ports 3105, a shutter 3106, and the like. The light-emitting device of the present invention can be used in the display portion 3102.

[0473] FIG. 13C is a laptop computer, which is composed of a main body 3201, a frame 3202, a display portion 3203, a keyboard 3204, external connection ports 3205, a pointing mouse 3206, and the like. The light-emitting device of the present invention can be used in the display portion 3203.

[0474] FIG. 13D is a mobile computer, which is composed of a main body 3301, a display portion 3302, a switch 3303, operation keys 3304, an infrared port 3305, and the like. The light-emitting device of the present invention can be used in the display portion 3302.

[0475] FIG. 13E is a portable image reproducing device equipped with a recording medium (specifically, a DVD player), and is composed of a main body 3401, a frame 3402, a display portion A 3403, a display portion B 3404, a recording medium (such as a DVD) read-in portion 3405, operation keys 3406, a speaker portion 3407, and the like. The display portion A 3403 mainly displays image information, and the display portion B 3404 mainly displays character information, and the light-emitting device of the present invention can be used in the display portion A 3403 and in the display portion B 3404. Note that family game machines and the like are included in the category of image reproducing devices provided with a recording medium.

[0476] FIG. 13F is a goggle type display device (head mounted display), which is composed of a main body 3501, a display portion 3502, and an arm portion 3503. The light-emitting device of the present invention can be used in the display portion 3502.

[0477] FIG. 13G is a video camera, which is composed of a main body 3601, a display portion 3602, a frame 3603, external connection ports 3604, a remote control receiving portion 3605, an image receiving portion 3606, a battery 3607, an audio input portion 3608, operation keys 3609, and the like. The light-emitting device of the present invention can be used in the display portion 3602.

[0478] FIG. 13H is a mobile telephone, which is composed of a main body 3701, a frame 3702, a display portion 3703, an audio input portion 3704, an audio output portion 3705, operation keys 3706, external connection ports 3707, an antenna 3708, and the like. The light-emitting device of the present invention can be used in the display portion 3703. Note that white characters are displayed on a black background in the display portion 3703, and thus, the power consumption of the mobile telephone can be suppressed.

[0479] Note that, when a light emitting intensity of an organic light emitting material is increased in future, it can be used for a front type or a rear type projector for magnifying and to projecting outputted light including image information by a lens or the like.

[0480] Also, in the above electronic apparatuses, the number of cases where information distributed through an electronic communication line such as an Internet or a CATV (cable television) is displayed is increased. In particular, a chance in which moving image information is displayed is increased. A response speed of the organic light emitting is material is very high. Thus, the light-emitting device is preferable for moving image display.

[0481] Also, with respect to the light-emitting device, power is consumed in a portion that emits light. Thus, it is desirable that information is displayed so as to minimize an area of a light-emitting portion. Accordingly, when the light-emitting device is used for a display portion of, a portable information terminal, particularly, a mobile telephone or a sound reproducing device in which character information is mainly displayed, it is desirable that the light-emitting device is driven so as to use a non-light emitting portion as a background and produce character information in a light emitting portion.

[0482] As described above, an application area of the present invention is extremely wide and the light-emitting device can be used for electronic apparatuses in all fields. In addition, the light-emitting device having any structure described in Embodiments 1 to 7 may be used for the electronic apparatuses of this embodiment.

Embodiment 7

[0483] A phenomenon is used in the present invention as a method of correcting the threshold value of transistors by making a short circuit between the gate and the drain of a transistor used in correction, and letting electric current flow between the source and the drain in this diode state, thus making the voltage between the source and the drain equal to the threshold value. It is also possible to apply this phenomenon to driver circuits as well as to pixel portions as introduced by the present invention,

[0484] An electric current source circuit in a driver circuit for outputting electric current to pixels and the like can be given as an example. The electric current source circuit is a circuit in which a predetermined amount of electric current is output in accordance with an input voltage signal. A voltage signal is input to a gate electrode of an electric current source transistor within the electric current source circuit, and an electric current corresponding to the voltage between the gate and the source is output through the electric current source transistor. That is, the method of the present invention for correcting the threshold value is utilized in correcting the threshold value of the electric current source transistor.

[0485] An example of utilizing the electric current source circuit is shown in FIG. 23A. Sampling pulses are output in order from a shift register, and the sampling pulses are each input to electric current source circuits 9001. Sampling of an image signal is performed in accordance with the timing at which the sampling pulses are input to the electric current source circuits 9001. Sampling operations are performed in a dot sequential manner in this case.

[0486] A simple operation timing is shown in FIG. 23B. A period for selecting a number i gate signal line is divided into a period for performing sampling of an image signal, in which the sampling pulses are output from the shift register, and a retrace period. The threshold value correction operations of the present invention are performed in the retrace period. That is, operations for initializing the electric potential of each portion, and operations for obtaining the transistor threshold voltages are performed sequentially. In other words, operations for obtaining the threshold values can be performed per single horizontal period.

[0487] The structure of a driver circuit for outputting electric current to pixels, but which differs from the structure of FIGS. 23A and 23B, is shown in FIG. 24A. Differing from the case of FIGS. 23A and 23B, the electric current source circuits 9001, which are controlled by one stage of sampling pulses, become two electric current source circuits 9001A and 9001B, and both operations are selected by an electric current source control signal.

[0488] As shown in FIG. 24B, the electric current source control signal may be made to change every single horizontal period, for example. Operation of the electric current source circuits 9001A and 9001B is thus performed so that one of the two circuits performs electric current output to pixels and the like while the other circuit performs input of the image signal. These operations are switched every row. Sampling operations are thus performed in a line sequential manner in this case.

[0489] A driver circuit having another different structure is shown in FIG. 25A. The image signal type may be either digital or analog in FIGS. 23A and 23B, and FIGS. 24A and 24B, but a digital image signal is input with the structure of FIG. 25A. The input digital image signal is taken in by a first latch circuit in accordance with the output of sampling pulses, and is transferred to a second latch circuit after the input of one row portion of the image signal is complete. This is later input to the electric current source circuits 9001A and 9001B, and electric current source circuits 9001C. The amounts of electric current value output by the electric current source circuits 9001A to 9001C differ. For example, the ratio of the electric current values becomes 1:2:4. That is, n electric current source circuits may be disposed in parallel, the ratio of the electric current values of the circuits may be set as 1:2:4:2.sup.(n-1), and the amount of electric current values output can be changed linearly by combining the electric currents output from each of the electric current source circuits.

[0490] Operation timing is nearly the same as that shown in FIGS. 23A and 23B. Threshold value correction is performed in the electric current source circuits 9001 within the retrace period during which sampling operations are not performed, data stored in the latch circuits is transferred, and V-I conversion is performed in the electric current source circuits 9001 and electric current is output to pixels. The sampling operations are performed in a line sequential manner, similar to the structure shown in FIGS. 24A and 24B.

[0491] The structure of another driver circuit for outputting electric current to pixels and the like is shown in FIG. 26A. A digital image signal taken in by a latch circuit is transferred to a D/A converter circuit by the input of a latching signal with this structure, and the digital image signal is converted to an analog image signal. The analog image signal is input to each of the electric current source circuits 9001, which output electric current.

[0492] Further, other functions may also be given to this type of D/A converter circuit, such as gamma correction.

[0493] Threshold value correction and latch data transfer are performed within the retrace period as shown in FIG. 26B. V-I conversion of a certain row, and output of electric current to pixels and the like, are performed during a period for performing sampling operations of the next row. The sampling operations are performed in a line sequential manner, similar to the structure shown in FIGS. 24A and 24B.

[0494] The present invention is not limited to the structures discussed above, and it is possible to apply the threshold value correcting means of the present invention to the case of performing V-I correction by using an electric current source circuit. Further, a structure in which a plurality of electric current source circuits are disposed in parallel, like the structure shown in FIGS. 24A and 24B, and used by switching between the circuits may also be combined with other structures, such as those of FIGS. 25A and 25B, and those of FIGS. 26A and 26B.

[0495] Dispersion in the threshold values of TFTs can be corrected normally by the present invention, without being influenced by dispersion and the like in the capacitance values of capacitor means, etc. In addition, although operations are often performed within one horizontal period in the case of performing threshold value correction in accordance with the structures shown in FIGS. 10A and 10B, and FIGS. 11A to 11F, the present invention is based on a simple operating principle. The operation timing is also simple, and therefore high speed circuit operations become possible. In particular, it becomes possible to display a high quality image using an image signal having a very large number of bits when performing display by a method in which a digital gray scale method and a time gray scale method are combined.