EXTENDED JTAG CONTROLLER AND METHOD FOR FUNCTIONAL DEBUGGING USING THE EXTENDED JTAG CONTROLLER

Abstract

The invention discloses an extended joint test action group based controller and a method for functional debugging using the extended joint test action group based controller. The object of the invention to lower the power dissipation (dynamic and leakage) but providing the same functionality of the testing and debugging procedures at the same time will be solved by an extended joint test action group (JTAG) controller for testing flip-flops of a register of an integrated circuit (IC) using a design for testing scan infrastructure on the IC which comprises at least one scan chain, wherein an external debugger is connected to the design for testing scan infrastructure via the JTAG controller which is extended by a debug controller, whereas a feedback loop is formed from an output of the scan chain to an input multiplexer of the scan chain which is activated according to the extended JTAG controller.

Claims

1. An extended joint test action group (JTAG) controller for testing flip-flops of a register of an integrated circuit (IC) using a design for testing scan infrastructure on the IC, wherein the IC comprises at least one scan chain, and wherein: an external debugger is connected to the design for testing scan infrastructure via the JTAG controller, the JTAG controller is extended by a debug controller, and; a feedback loop is formed from an output of the scan chain to an input multiplexer of the scan chain which is activated according to the extended JTAG controller in order to directly test its functionality.

2. The extended JTAG controller according to claim 1, wherein all scan chains have a same number of flip-flops.

3. The extended JTAG controller according to claim 1, wherein a dummy flip-flop is inserted in a scan chain, if the number of flip-flops in that scan chain is different to the other scan chains.

4. The extended JTAG controller according to claim 1, wherein the outputs of the scan chains are connected to an output multiplexer transmitting the outputs of the scan chains to the extended JTAG controller.

5. The extended JTAG controller according to claim 1, wherein the external debugger observes the flip-flops states of the IC and replaces the flip-flop states via the extended JTAG controller.

6. The extended JTAG controller according to claim 1, wherein the extended JTAG controller comprises an event trigger.

7. The extended JTAG controller according to claim 1, wherein the last flip-flop of a specified scan chain is designed as a hardware breakpoint.

8. A method for functional debugging of registers of an IC using the extended joint action group controller according to claim 1, wherein in debugging mode a selected scan chain is connected to the JTAG controller, the selected scan chain is observed by the JTAG controller, the JTAG controller controls an output multiplexer multiplexing outputs of connected scan chains and the according input multiplexer of the selected scan chain, wherein the JTAG controller controls the number of shift clock cycles, and the selected scan chain is modified by the JTAG controller, wherein the selected scan chain is fed back from the JTAG controller to the input multiplexer of the selected scan chain while setting all other scan chains of the IC in a loop back mode.

9. The method for functional debugging of registers of an IC according to claim 8, wherein in the loop back mode the flip-flops states are fed back to the input multiplexer of the scan chain, respectively.

10. The method for functional debugging of registers of an IC according to claim 8, wherein the JTAG controller switches to the next scan chain if an external debugger is accessing the said scan chain.

11. The method for functional debugging of registers of an IC according to claim 8, wherein in design of testing mode the JTAG controller controls the input multiplexer, whereas a default value is routed through the scan chains.

12. The extended JTAG controller according to claim 2, wherein the outputs of the scan chains are connected to an output multiplexer transmitting the outputs of the scan chains to the extended JTAG controller.

13. The extended JTAG controller according to claim 4, wherein the external debugger observes the flip-flops states of the IC and replaces the flip-flop states via the extended JTAG controller.

14. The extended JTAG controller according to claim 5, wherein the extended JTAG controller comprises an event trigger.

15. The extended JTAG controller according to claim 6, wherein the last flip-flop of a specified scan chain is designed as a hardware breakpoint.

16. A method for functional debugging of registers of an IC using the extended joint action group (JTAG) controller according to claim 4, wherein in debugging mode a selected scan chain is connected to the JTAG controller, the selected scan chain is observed by the JTAG controller, the JTAG controller controls an output multiplexer multiplexing outputs of connected scan chains and the according input multiplexer of the selected scan chain, wherein the JTAG controller controls the number of shift clock cycles, and the selected scan chain is modified by the JTAG controller, wherein the selected scan chain is fed back from the JTAG controller to the input multiplexer of the selected scan chain while setting all other scan chains of the IC in a loop back mode.

17. The method for functional debugging of registers of an IC according to claim 16, wherein in the loop back mode the flip-flops states are fed back to the input multiplexer of the scan chain, respectively.

18. The method for functional debugging of registers of an IC according to claim 17, wherein the JTAG controller switches to the next scan chain if an external debugger is accessing the said scan chain.

19. The method for functional debugging of registers of an IC according to claim 18, wherein in design of testing mode the JTAG controller controls the input multiplexer, whereas a default value is routed through the scan chains.

20. A method for functional debugging of registers of an IC using the extended joint action group (JTAG) controller according to claim 7, wherein in debugging mode a selected scan chain is connected to the JTAG controller, the selected scan chain is observed by the JTAG controller, the JTAG controller controls an output multiplexer multiplexing outputs of connected scan chains and the according input multiplexer of the selected scan chain, wherein the JTAG controller controls the number of shift clock cycles, and the selected scan chain is modified by the JTAG controller, wherein the selected scan chain is fed back from the JTAG controller to the input multiplexer of the selected scan chain while setting all other scan chains of the IC in a loop back mode.

Description

[0027] The invention will be explained in more detail using exemplary embodiments.

[0028] The appended drawings show

[0029] FIG. 1 A common joint test action group based infrastructure in an IC (state-of-the-art);

[0030] FIG. 2 Common design for testing structure in an IC (state-of-the-art);

[0031] FIG. 3 Inventive merged infrastructure for testing and debugging with the extended JTAG controller;

[0032] FIG. 4 Inserted feedback loop in a scan chain due to the inventive extended JTAG controller;

[0033] FIG. 5 Detailed schematic view of the inventive JTAG controller inside an IC.

[0034] FIG. 3 shows the inventive extended JTAG controller 1 wherein an external debugger 12 is connected to the design for testing scan infrastructure via the JTAG controller which is extended by a debug controller 11. The design for testing scan infrastructure is merged with the debug infrastructure in order to save gates of the IC 3 and simultaneously to make all registers 2 of the IC 3 accessible to the external debugger 12 and hence lower the power dissipation.

[0035] All internal registers 2 are accessible to the external debugger 12 without accessing the internal bus on the one hand and without increasing the power consumption on the other hand. If the internal bus is blocked or in a dead lock state, it does not matter, because all registers 2 can be read and written via the scan chains 5.

[0036] FIG. 4 shows the inserted feedback loop 10 in a scan chain 5. Module 2 represents a register which consist of n flip-flop. FIG. 4 shows two registers with n+m flip-flops connected to a scan chain. The loop back is necessary to preserve the content of all flip-flops of this scan chain. Each scan chain 5 has the same number of flip-flops 6. If this is not the case a dummy flip-flop 7 will be inserted to have the same number of flip-flops in each scan chain 5. The reason is, in debugging mode, that the not selected scan chains 5 shift back their content in the feedback loop 10 to retain it until these scan chains 5 are debugged as well. In debug mode, the content of the selected scan chain 5 will be shifted through the merged extended JTAG controller 1 and fed back. The content of the scan chain 5 can be observed or replaced in the controller.

[0037] FIG. 5 shows a detailed schematic view of the inventive JTAG controller 1 inside an IC 3. With the reuse of a common JTAG controller for design for testing tasks as well as for functional debugging it is possible to lower the power dissipation by reducing the number of gate counts in the IC 3.

[0038] The merged joint test action group (JTAG) design for testing/debug controller fulfils the requirement of the IEEE 1149.1 standard (boundary scan) and IEEE 1500 standard (core wrapper test).

[0039] So, the design for test (DfT) feature set is the same as for a standard DfT control. The debug feature set in design for test mode controls the input multiplexers (imux's), whereas the default value is to route through the scan chain input.

[0040] In debug mode the selected scan chain is connected to the controller which controls the output multiplexer (omux) multiplexing outputs of the connected scan chains and the according input multiplexer (imux) of the selected scan chain. The JTAG controller sets all other scan chains in loop back mode and controls the number of shift clock cycles.

[0041] For realizing the new extended JTAG controller and method for functional debugging using the extended JTAG controller new JTAG op codes for debug mode, input multiplexer control, output multiplexer control, shift value and shift control of the clock network and the observation and replacement of shift content is needed.

[0042] The advantage of the invention is that no additional hardware is needed to read and/or modify all registers. With this new methodology, all registers can be recorded, which is not possible with the state-of-the-art methodology. In the state-of-the-art, all registers that are eligible for debugging must be connected to an internal bus in order to be accessible by the debug controller. The invention relies on the existing design for test (DfT) structure and requires only additional OP codes for the combined JTAG/debug controller, the input and output multiplexers as well as the control logic for the multiplexers and clock cycles. This hardware cost is very low compared to the state-of-the-art methodology of making each register accessible by a bus.

REFERENCE SIGNS

[0043] 1 extended joint action group (JTAG) controller [0044] 2 module, register [0045] 3 integrated circuit (IC) [0046] 4 design for testing infrastructure [0047] 5 scan chain [0048] 6 flip-flop [0049] 6l last flip-flop of a scan chain [0050] 7 dummy flip-flop [0051] 8 output multiplexer [0052] 9 input multiplexer [0053] 10 feedback loop, loop back [0054] 11 debug controller [0055] 12 external debugger