BARELY DOHERTY ET USING ET VCC MODULATION FOR BIAS CONTROL

Abstract

A power amplifier system is disclosed with a carrier amplifier having a carrier bias input and a carrier supply node and a peaking amplifier having a peaking bias input and a peaking supply node. Also included is an envelope tracking power supply having a modulated voltage supply output coupled to the peaking supply node. Further included is a peaking bias controller having a peaking bias control input coupled to the peaking supply node and a peaking bias control output coupled to the peaking bias input, wherein the peaking bias controller is configured to generate in response to a modulated peaking supply voltage generated by the envelope tracking power supply at the peaking supply node a modulated peaking bias signal that controls bias of the peaking amplifier.

Claims

1. A power amplifier system comprising: a carrier amplifier having a carrier bias input and a carrier supply node; a peaking amplifier having a peaking bias input and a peaking supply node; an envelope tracking power supply having a modulated voltage supply output coupled to the peaking supply node; and a peaking bias controller having a peaking bias control input coupled to the peaking supply node and a peaking bias control output coupled to the peaking bias input, wherein the peaking bias controller generates in response to a modulated peaking supply voltage generated by the envelope tracking power supply at the peaking supply node a modulated peaking bias signal that controls bias of the peaking amplifier.

2. The power amplifier system of claim 1 wherein the peaking bias controller comprises a peaking look-up table having direct current peaking bias values that correspond with instantaneous levels of the modulated peaking supply voltage.

3. The power amplifier system of claim 2 wherein the direct current peaking bias values correspond to the modulated peaking voltage nonlinearly.

4. The power amplifier system of claim 2 further comprising a peaking digital interface coupled to the peaking look-up table, wherein the peaking look-up table is programmable to receive new direct current peaking bias values over the peaking digital interface.

5. The power amplifier system of claim 4 wherein the peaking digital interface is coupled to a radio frequency front-end (RFFE) control interface.

6. The power amplifier system of claim 2 wherein the peaking bias controller comprises: a peaking analog-to-digital converter having a peaking analog input coupled to the peaking bias control input and a peaking digital output; the peaking look-up table having a peaking look-up input coupled to the peaking digital output and a peaking look-up output; and a peaking digital-to-analog converter having a peaking digital input coupled to the peaking look-up output and a peaking analog output coupled to the peaking bias control output.

7. The power amplifier system of claim 1 further comprising a carrier bias controller having a carrier bias control input coupled to the carrier supply node and a carrier bias control output coupled to the carrier bias input, wherein the carrier bias controller generates in response to a modulated carrier supply voltage generated by the envelope tracking power supply at the carrier supply node a modulated carrier bias signal that controls bias of the carrier amplifier.

8. The power amplifier system of claim 7 wherein the carrier bias controller comprises a carrier look-up table having direct current carrier bias values that correspond with instantaneous levels of the modulated carrier supply voltage.

9. The power amplifier system of claim 8 wherein the direct current carrier bias values correspond to the modulated carrier voltage nonlinearly.

10. The power amplifier system of claim 8 further comprising a carrier digital interface coupled to the carrier look-up table, wherein the carrier look-up table is programmable to receive new direct current carrier bias values over the carrier digital interface.

11. The power amplifier system of claim 10 wherein the carrier digital interface is coupled to the RFFE control interface.

12. The power amplifier system of claim 7 wherein the modulated peaking bias signal that controls bias of the peaking amplifier has a modulation bandwidth that is between 400 MHz and 500 MHz.

13. The power amplifier system of claim 7 wherein the carrier bias controller comprises: a carrier analog-to-digital converter having a carrier analog input coupled to the carrier bias control input and a carrier digital output; a carrier look-up table having a carrier look-up input coupled to the carrier digital output and a carrier look-up output; and a carrier digital-to-analog converter having a carrier digital input coupled to the carrier look-up output and a carrier analog output coupled to the carrier bias control output.

14. The power amplifier system of claim 1 wherein the peaking amplifier and the carrier amplifier are configured as differential amplifiers.

15. The power amplifier system of claim 1 wherein the envelope tracking power supply is configured to supply the carrier amplifier with an average power tracking (APT) modulated supply voltage.

16. The power amplifier system of claim 1 wherein the envelope tracking power supply is configured to supply the peaking amplifier with APT modulated supply voltage.

17. The power amplifier system of claim 1 wherein the envelope tracking power supply is configured to supply the carrier amplifier with instantaneous envelope tracking modulated voltage.

18. The power amplifier system of claim 1 wherein the envelope tracking power supply is configured to supply the peaking amplifier with instantaneous envelope tracking modulated voltage.

19. The power amplifier system of claim 19 further comprising a peaking direct current (DC) bias control coupled between the modulated voltage supply output and the peaking bias input, wherein the peaking DC bias control is configured to adjust DC bias of the peaking amplifier as a function of average output power of the peaking amplifier.

20. The power amplifier system of claim 19 further comprising a carrier direct current (DC) bias control coupled between the modulated voltage supply output and the carrier bias input, wherein the carrier DC bias control is configured to adjust DC bias of the carrier amplifier as a function of average output power of the carrier amplifier.

21. The power amplifier system of claim 19 further comprising a DC bias mapping look-up table coupled to the peaking DC bias, wherein the DC bias mapping look-up table is configured to adjust slope of the peaking bias control.

22. The power amplifier system of claim 21 wherein the DC bias mapping look-up table is programmable over the RFFE control interface.

23. The power amplifier system of claim 20 wherein the carrier DC bias control and the peaking DC bias control are configured to receive average power output values that are proportional to the combined power output of the carrier amplifier and the peaking amplifier, wherein the carrier DC bias control and the peaking DC bias control are configured to control the carrier DC bias and the peaking DC bias in response to the average power output values.

24. The power amplifier system of claim 24 wherein the average power output values are transmitted to the carrier DC bias control and the peaking DC bias control over the RFFE control interface.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0010] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0011] FIG. 1 is a block diagram of a related-art power amplifier system having an envelope tracking integrated circuit (ETIC) and a barely Doherty power amplifier.

[0012] FIG. 2 is a block diagram showing a related-art basic barely Doherty power amplifier.

[0013] FIG. 3 is a diagram showing related art of a bias control of the peaking amplifier.

[0014] FIG. 4 is a diagram showing an embodiment in which the peaking amplifier bias (t)=f(Vcc peaking (t)) with the power supply voltage (Vcc) peaking in an ET modulated supply.

[0015] FIG. 5 is a diagram showing another embodiment in which each amplifier uses the ET modulated supply to modulate also the bias.

[0016] FIG. 6 is a diagram showing a bias network that maps ET Vcc into a bias modulation that is made programmable.

[0017] FIG. 7 is a diagram showing both carrier and peaking amplifiers bias mapping to ET Vcc that are made programmable.

[0018] FIGS. 8A and 8B are diagrams showing the circuit topology of a barely Doherty ET differential amplifier using the modulated ET Vcc for peaking amplifier bias control.

[0019] FIG. 9 is a diagram showing a circuit topology of a barely Doherty ET differential amplifier using two independent ET Vccs, each applied also to its respective bias control.

[0020] FIG. 10 is a diagram showing a main embodiment showing direct current (DC) bias control, as a function of Pout, and modulated bias control using the modulated ET Vcc.

[0021] FIG. 11 is a diagram showing a main embodiment showing the two bias sums for the peaking amplifier.

[0022] FIG. 12 is a diagram showing a single DC bias programming and internal mapping to program the DC bias of the peaking amplifier from the carrier amplifier value.

[0023] FIG. 13 is a graph showing an example of peaking amplifier bias control represented by Ip/b relative to the modulated ET Vcc.

[0024] FIGS. 14 to 21 are graphs showing various ET barely Doherty signals.

DETAILED DESCRIPTION

[0025] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0026] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0027] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0028] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0031] Embodiments are described herein with reference to schematic illustrations of embodiments of the disclosure. As such, the actual dimensions of the layers and elements can be different, and variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are expected. For example, a region illustrated or described as square or rectangular can have rounded or curved features, and regions shown as straight lines may have some irregularity. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the disclosure. Additionally, sizes of structures or regions may be exaggerated relative to other structures or regions for illustrative purposes and, thus, are provided to illustrate the general structures of the present subject matter and may or may not be drawn to scale. Common elements between figures may be shown herein with common element numbers and may not be subsequently re-described.

[0032] The present disclosure relates to a method to control the peaking amplifier of a load modulation power amplifier for a full or barely Doherty envelope tracking (ET) power amplifier.

[0033] FIG. 1 is a schematic depicting a related-art power amplifier system 10 having an envelope tracking integrated circuit (ETIC) 12, a Doherty ET power amplifier 14, and a transceiver (XCVR) 16. The ETIC 12 is configured to supply the barely Doherty ET power amplifier 14 with modulated power that tracks the envelope of a radio frequency (RF) signal generated by the XCVR 16. An in-phase/quadrature digital pre-distortion (I/O DPD) 18 included in the XCVR 16 has a predistortion output 20 that is coupled to an RF input 22 of a hybrid coupler 24 included in the Doherty ET power amplifier 14. The RF signal generated by the XCVR 16 is pre-distorted by the I/O DPD 18 to improve linearity of an amplified version of the RF signal output from an RF output 26. A peaking amplifier 28 is coupled between a first coupler output 30 and the RF output 26. A carrier amplifier 32 is coupled in series between a second coupler output 34 and an impedance inverter 36 coupled to the RF output 26.

[0034] Tracker circuitry 38 included in the ETIC 12 receives an analog signal Vcctarget that is generated by a Vramp digital-to-analog (DAC) converter 40. Vramp is a digital signal that follows the envelope of the RF signal being amplified by the Doherty ET power amplifier 14. The tracker circuitry 38 incorporates a power inductor 42 to filter an envelope tracked supply voltage VCC_ET. A first RF front-end (RFFE) interface 44 of the XCVR 16 is coupled to a second RFFE interface 46 of the ETIC 12. The XCRV 16 is configured to send digital control signals and data between the first RFFE interface 44 and the second RFFE interface 46 to control the ETIC 12. The digital control signals include but are not limited to switching RF bands and controlling power levels.

[0035] FIG. 2 shows a basic simplified schematic of the related-art Doherty power amplifier 14 and defined baseband parameters. This simple model of the radio frequency (RF) voltages and currents of the Doherty power amplifier, which is of the load-line modulation type, includes the peaking amplifier 28 and the carrier amplifier 32. The envelope of the RF voltage across the carrier amplifier 32 is designated Vm, and the associated baseband current is designated Im. The envelope of the RF voltage across the peaking amplifier is designated Vp, and the associated baseband current is designated j*Ip, wherein j.sup.2=−1.

[0036] The impedance inverter 34 having an impedance inverter coefficient Ka is a block that makes Zin*ZL=−Ka.sup.2, with Ka=j*|Ka|, with |Ka|=2*ZL for the barely Doherty power amplifier 14, and Zin and ZL are the impedance at the RF input 22 and the RF output 26, respectively, of the impedance inverter 34. The impedance inverter coefficient Ka equals a value of characteristic impedance Z0 that provides impedance inversion between an input and an output of the impedance inverter 34.

[0037] In a related-art diagram of a load modulation mainly in average power tracking (APT) mode, FIG. 3 shows the related-art Doherty ET power amplifier 14 with dynamic power amplifier bias (DPAB) control circuitry 48 that is configured to control bias circuitry 50 of the peaking amplifier 28. In operation, the DPAB control circuitry 48 activates the bias circuitry 50 to bias the peaking amplifier 28 from one class of operation to another class of operation during the modulation envelope ET. The DPAB control circuitry 48 that responds to the detected envelope of the modulation envelope ET at a base of the carrier amplifier 32 and couples detected envelope to the bias circuitry 50 of the peaking amplifier 28 and thereby increasing or decreasing the class of operation of the peaking amplifier. The DPAB control circuitry 48 is also known as a fast bias-debias controller.

[0038] In a barely ET Doherty power amplifier, in related art, the circuit DPAB is disabled, and both the peaking amplifier 28 and the carrier amplifier 28 are operating in class AB, and no bias changes are done on the peaking amplifier 28. A third RFFE interface 52 is included to allow changes to amplifier parameters such as power level control during operation of the related-art Doherty ET power amplifier 14.

[0039] A method according to the present disclosure uses the modulated power supply voltage (Vcc) signal that changes vs. the modulation envelope for isogain operation, for example, to control the bias of the peaking amplifier where the modulated ET Vcc signal is adjusting and changing the class of operation of the peaking amplifier, and thus allowing improved efficiency and reduced memory effects without the need to detect wide modulation envelope. Basically, the peaking amplifier modulated bias is a function of the ET supply modulation signal, that is, peaking amplifier bias (t)=f (Vcc (t)). This allows the peaking amplifier to operate in Class C at low power level and quickly bias/debias when load modulation is applied using the same modulation ET Vcc signal, such that both ET Vcc and the bias modulation move at the same rate and change at the same time.

[0040] FIG. 4 shows an exemplary embodiment of a barely Doherty ET power amplifier 54 in which the peaking amplifier bias (t)=f(Vcc peaking (t)) with the Vcc peaking in an ET modulated supply. In this exemplary embodiment, the carrier amplifier 32 has traditional bias circuitry 56, while bias to the peaking amplifier 28 is controlled by a peaking bias controller 58. The peaking bias controller 58 has a peaking bias control input 60 coupled to a peaking supply node 62 and a peaking bias control output 64 coupled to a peaking bias input 65. In operation, the peaking bias controller 58 generates a modulated peaking bias signal that controls bias of the peaking amplifier 28 in response to a modulated peaking supply voltage at the peaking supply node 62.

[0041] FIG. 5 is a schematic of another exemplary embodiment of the barely Doherty power amplifier 54. In this embodiment, the barely Doherty power amplifier 54 includes a carrier bias controller 66 having a carrier bias control input 68 coupled to a carrier supply node 70 and a carrier bias control output 72 coupled to a carrier bias input 74. In operation, the carrier bias controller 66 generates a modulated carrier bias signal that controls bias of the carrier amplifier 32 in response to a modulated carrier supply voltage at the carrier supply node 70. As a result of this exemplary embodiment, the respective bias of both the carrier amplifier 32 and the peaking amplifier 28 are modulated by the modulated ET Vcc supply voltage.

[0042] The peaking bias controller 58 is made programmable to map a given ET Vcc voltage into a given bias response by way of a first programmable analog look-up table (LUT) 76, as shown in FIG. 6. This exemplary embodiment can be extended to control biases of both the carrier amplifier 32 and the peaking amplifier 28 by adding a second programmable analog LUT 78, as shown in FIG. 7. The second programmable analog LUT may also be referred to as a carrier look-up table.

[0043] FIG. 8A is a schematic of a exemplary embodiment of a differential barely ET Doherty amplifier 80 using the modulated ET Vcc for bias modulation. The differential barely Doherty power amplifier 80, which is of the load-line modulation type, includes a differential peaking amplifier 82 and a differential carrier amplifier 84. A 0°/90° hybrid coupler 86 has an RF input 88, first coupler input 90, and a second coupler output 92. The differential peaking amplifier 82 is coupled between the first coupler output 90 and a primary 94 of an RF transformer 96. The differential carrier amplifier 84 is coupled between the second coupler output 92 and a differential impedance inverter 98, which is coupled between the differential carrier amplifier 84 and the primary 94. A filter 100 and a load 102 are coupled across a secondary 104 of the RF transformer 96. A differential peaking bias controller 106 has a differential peaking bias control input 108 coupled to a primary tap 110 and a differential peaking bias control output 112 coupled to a differential peaking bias input 114. In operation, the peaking bias controller 106 generates a modulated peaking bias signal that controls bias of the differential peaking amplifier 82 in response to a modulated peaking supply voltage at the primary tap 110. In operation, the differential peaking bias controller 106 generates a modulated peaking bias signal that controls bias of the differential peaking amplifier 82 in response to a modulated peaking supply voltage Vcc (ET) at the primary tap 110.

[0044] FIG. 8B is a schematic of another version of the exemplary embodiment of the differential barely ET Doherty amplifier 80 using the modulated ET Vcc for bias modulation of the differential peaking amplifier 82. In this case, the differential peaking amplifier 82 is coupled to a peaking transformer 116 and the differential carrier amplifier 84 is coupled to a carrier transformer 118. Also, in this case, the impedance inverter 98 is coupled between a secondary 120 of the carrier transformer 118 and the filter 100. Furthermore, the differential peaking bias control input 108 is coupled to a common primary tap 122. A secondary 124 of the peaking transformer 116 is coupled across the filter 100 and the load 104. In operation, the differential peaking bias controller 106 generates a modulated peaking bias signal that controls bias of the differential peaking amplifier 82 in response to a modulated peaking supply voltage Vcc (ET) at the common primary tap 122.

[0045] FIG. 9 is a schematic showing an embodiment showing separate ET Vcc, one for the differential carrier amplifier 84 and one for the differential peaking amplifier 82, with bias control modulation using their respective ET Vcc modulations. In this case, a carrier bias controller 126 has a differential carrier bias control input 128 that is coupled to a carrier supply node labeled Vcc Carrier (ET/APT) and a differential carrier bias control output 130 coupled to a carrier bias input 132. Also, the differential peaking bias control input 108 is coupled to a peaking supply node labeled Vcc Peaking (ET/APT).

[0046] In operation, the differential peaking bias controller 106 generates a modulated peaking bias signal that controls bias of the differential peaking amplifier 82 in response to the modulated peaking supply voltage Vcc (ET/APT) at the common primary tap 122. Moreover, the differential carrier bias controller 116 generates a modulated peaking bias signal that controls bias of the differential carrier amplifier 84 in response to the modulated carrier supply voltage Vcc (ET).

[0047] FIG. 10 is schematic of another version of the exemplary embodiment of the differential barely ET Doherty amplifier 80 in which the peaking bias controller 106 includes a peaking DC bias input 134. The peaking bias controller 106 is further configured to add DC bias control to the differential peaking amplifier 82 as a function of average output power (Avg Pout). The carrier bias controller 126 includes a carrier DC bias input 136. The carrier bias controller 126 is further configured to control the bias of the differential carrier amplifier 84 as a function of average output power (Avg Pout).

[0048] FIG. 11 is schematic of a version of the exemplary embodiment of the differential barely ET Doherty amplifier 80 in which the peaking bias controller 106 is not configured to add DC bias control to the differential peaking amplifier 82. Instead, a separate peaking DC bias controller 140 having a DC bias input 142 is further configured to control the bias of the differential peaking amplifier 82 as a function of average output power (Avg Pout). The peaking amplifier bias control is thus the sum of a DC bias control programmed via the third RFFE interface 52 that is function of Pout and a modulated bias using the modulated ET Vcc, which slope can be also programmable via the third RFFE interface 52, as shown in FIG. 11.

[0049] One also may consider the embodiment in FIG. 12, in which the third RFFE interface 52 only programs one DC bias value that is a function of Pout and that is used to adjust the bias for the carrier amplifier, similar to any other type of power amplifier. Then internally, an analog or digital map to the corresponding DC bias value is made for the peaking amplifier using an analog or digital LUT stored within DC bias mapping 144, which can be adjustable via the third RFFE interface 52 if needed, and thus only requiring the programming versus total power control changes of one DC bias value and thus maintaining compatibility with all other types of power amplifiers, as shown in FIG. 12. Changes in DC bias corresponding to DC bias values selected from the DC bias mapping 144 are conveyed through the DC bias input 142. Selections of DC bias values are a function of peaking DC bias slope transmitted through a bias slope terminal input 146. Selections of DC bias values may also be made through an average output power input terminal 148.

[0050] FIG. 13 shows an example of peaking amplifier bias control represented by Ip/b relative to the modulated ET Vcc, which is labeled Vm in FIG. 13. FIGS. 14 to 21 show various ET barely Doherty signals.

[0051] An advantage of the disclosed embodiments is that the peaking amplifier bias control is based on two components: [0052] one DC bias control that is adjustable via the radio frequency front-end (RFFE) to adjust the DC bias versus average output power change, and [0053] a modulated bias control that uses the modulated ET Vcc, which relation relative to ET Vcc can be made programmable via RFFE programming. Note that the embodiments are configured to handle wide bandwidth modulation to avoid creating memory effects.

[0054] It is contemplated that any of the foregoing aspects, and/or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments unless indicated to the contrary herein.

[0055] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.