Power MOSFET Active Gate Drive Based on Negative Feedback Mechanism

Abstract

This invention introduces the negative feedback into the gate drive. It proposes a negative feedback active gate drive (NFAGD) for silicon carbide (SiC) and gallium nitride (GaN) semiconductor devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. An auxiliary P-channel MOSFET is introduced to construct a negative feedback control mechanism. Due to the negative feedback mechanism, the proposed drive can automatically attenuate the disturbance from the complementary device of the phase-leg. The negative feedback active gate drive (NFAGD) has a simple structure and easy to be realized using a push-pull drive circuit, a drive resistor, an auxiliary MOSFET and an auxiliary capacitor, without involving any additional logical circuits. Functionally, the negative feedback active gate drive (NFAGD) can automatically suppress the induced gate-source voltage and make the gate voltage of the MOSFET stable even during high-speed switching operation without sacrificing the switching speed of the MOSFET.

Claims

1. A power MOSFET gate drive based on negative feedback mechanism, for connecting a drive signal to turn on and off a controlled MOSFET, comprising: an auxiliary MOSFET, being a P-channel MOSFET, and having its source connected to a gate of the controlled MOSFET for creating a negative-feedback regulating mechanism, the auxiliary MOSFET having its drain connected to a drive voltage; the drive voltage being a voltage of a drive chip that has been filtered by a passive network; a first node, a second node, and a third node; a push-pull drive circuit, for providing a driving current to drive the controlled MOSFET, the drive signal being connected to the push-pull drive circuit, and the push-pull drive circuit and the third node being connected in series; and a drive resistor R, having one end connected in series with the push-pull drive circuit, and having an opposite end connected to the first node, for limiting a charging/discharging current applied to an auxiliary capacitor C by the push-pull drive circuit, and a voltage difference between the first node and a source of the controlled MOSFET being the drive voltage; the auxiliary capacitor C having one end connected to the first node and having an opposite end connected to the source of the controlled MOSFET through the third node, so as to work with the drive resistor R to form the passive network for regulating a switching speed of the controlled MOSFET; wherein the drain and the gate of the auxiliary MOSFET connect in series with the drive resistor R through the second node, and the source of the auxiliary MOSFET is connected to the gate of the controlled MOSFET for creating the negative-feedback regulating mechanism.

2. (canceled)

3. The power MOSFET gate drive based on negative feedback mechanism of claim 1, wherein the push-pull drive circuit comprises a MOSFET gate drive chip, an on-bias voltage V.sub.CC and an off-bias voltage V.sub.EE; the MOSFET gate drive chip having a positive supply terminal connected to a positive pole of the on-bias voltage V.sub.CC, the MOSFET gate drive chip having a negative supply terminal connected to a negative pole of the off-bias voltage V.sub.EE, the MOSFET gate drive chip having a drive output terminal connected to one end of the drive resistor R and having a drive input terminal connected to the drive signal; and a negative pole of the on-bias voltage V.sub.CC and a positive pole of the off-bias voltage V.sub.EE both being connected to the third node, whereby in terms of driving capability, a permissible output current of the MOSFET drive chip should not be smaller than (V.sub.CC−V.sub.EE)/R.sub.g.

4. The power MOSFET gate drive based on negative feedback mechanism of claim 1, wherein the auxiliary MOSFET has a drain-source breakdown voltage not smaller than V.sub.CC−V.sub.EE, and has a maximum permissible continuous drain current not smaller than (V.sub.CC−V.sub.EE)/R.sub.g.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The invention will be best understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings:

[0057] FIG. 1 is a circuit diagram of a negative feedback active gate drive (NFAGD) of the present invention;

[0058] FIG. 2 is a block diagram showing control of the negative feedback active gate drive (NFAGD) of the present invention;

[0059] FIG. 3 depicts a negative feedback active gate drive in a phase-leg structure according to one embodiment of the present invention;

[0060] FIG. 4a is a schematic waveform diagram during the turning on process of ¢.sub.H using the negative feedback active gate drive;

[0061] FIG. 4b is a schematic waveform diagram during the turning off process of ¢.sub.H using the negative feedback active gate drive;

[0062] FIG. 5a is a diagram of an experimental circuit with the conventional gate drive without suppression for comparison with one embodiment of the present invention;

[0063] FIG. 5b is a diagram of an experimental circuit with the conventional gate drive that used passive suppression for comparison with one embodiment of the present invention;

[0064] FIG. 5c is a diagram of an experimental circuit with one embodiment of the present invention;

[0065] FIG. 6a is the experimental waveform of one switching cycle of an experimental circuit with the conventional gate drive without suppression;

[0066] FIG. 6b is the enlarged rising edge of v.sub.DS2 of an experimental circuit with the conventional gate drive without suppression;

[0067] FIG. 6c is the enlarged falling edge of v.sub.DS2 of an experimental circuit with the conventional gate drive without suppression;

[0068] FIG. 7a is the experimental waveform of one switching cycle of an experimental circuit with the conventional gate drive that used passive suppression;

[0069] FIG. 7b is the enlarged rising edge of v.sub.DS2 of an experimental circuit with the conventional gate drive that used passive suppression;

[0070] FIG. 7c is the enlarged falling edge of v.sub.DS2 of an experimental circuit with the conventional gate drive that used passive suppression;

[0071] FIG. 8a is the experimental waveform of one switching cycle of an experimental circuit with one embodiment of the present invention;

[0072] FIG. 8b is the enlarged rising edge of v.sub.DS2 of an experimental circuit with one embodiment of the present invention;

[0073] FIG. 8c is the enlarged falling edge of v.sub.DS2 of an experimental circuit with one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0074] One mode for implementing the present invention is now described.

[0075] As shown in FIG. 1, a negative feedback active gate drive (NFAGD) is used to drive a MOSFET .sub.N. The output of a conventional gate MOSFET drive is connected to a network, constituted by the drive resistor R and the auxiliary capacitor C. The output of the RC network is also regarded as the drive reference vGS*. It then goes to the gate and source of controlled MOSFET through the auxiliary MOSFET. For building the negative feedback, the controlled MOSFET and auxiliary MOSFET should have a complementary channel characteristic. Usually, the controlled MOSFET is N-channel. Hence the auxiliary MOSFET is P-channel. Hereafter, this invention denotes the controlled MOSFET and the auxiliary MOSFET as QN and QP. The RC network is responsible for tunning the speed of switching. The gate voltage vGS would follow the drive reference vGS*, owing to the negative feedback control. Hence the speed of gate voltage vGS is similar to that of the drive reference vGS*.

[0076] FIG. 2 illustrates the negative feedback regulating mechanism possessed by the circuit of the present invention. The analysis bases on two simplifications to explain the mathematical nature of NFAGD for understanding. Firstly, the transconductance gain of the auxiliary MOSFET .sub.P is treated as a non-time-varying constant g.sub.m. The reverse transconductance gain of the parasitic body diode (the slope of the output characteristic curve) is also expressed by g.sub.m. Secondly, the reverse conducting threshold voltage of the auxiliary MOSFET .sub.P is equal to its forward conducting threshold voltage, and both are denoted V.sub.th. The close-loop transfer function of the NFAGD can be derived from the block diagram shown in FIG. 1, given as:

[00001]$\begin{array}{cc}\Phi \left(s\right)=\frac{v_{GS}\left(s\right)}{{v_{GS}}^{*}\left(s\right)}=\frac{G\left(s\right)}{1+G\left(s\right)}& \left(1\right)\end{array}$

[0077] Where G(s) is the open-loop transfer function of NFAGD, given as:

[00002]$\begin{array}{cc}G\left(s\right)=g_m\left(\frac{1}{s{C}_{\mathrm{iss}}}+R_g\right)=\frac{g_m}{C_{\mathrm{iss}}}\frac{{\mathrm{sR}}_g{C}_{\mathrm{iss}}+1}{s}& \left(2\right)\end{array}$

[0078] According to the system dynamic theory, the NFAGD is a unity-feedback type 1 control system. The open-loop gain is g.sub.m/C.sub.iss. Static velocity error constant can be expressed as:

[00003]$\begin{array}{cc}{K}_v=\underset{s.fwdarw.0}{\lim }sG\left(s\right)=\frac{g_m}{C_{\mathrm{iss}}}& \left(3\right)\end{array}$

[0079] In general, the input capacitance of controlled MOSFET (C.sub.iss) is about several nano-farads. Simultaneously, the transconductance gain of the auxiliary MOSFET (g.sub.m) is far larger than 1 Siemens, therefore under the international system of units, we can get g.sub.m>>C.sub.iss, so the static velocity error constant K.sub.v is large enough. Therefore, when the gate voltage v.sub.GS tracks the ramping drive reference v.sub.GS*, the deviation between them is small enough and does not affect the turn-on and turn-off of the controlled SiC MOSFET following the designer's request. Moreover, due to the large static velocity error constant K.sub.v, the suppression ratio of the disturbance n(s) is large enough to attenuate the induced spikes and oscillations on gate voltage v.sub.GS(s).

[0080] As shown in FIG. 3, the depicted embodiment shows a negative feedback active gate drive (NFAGD) used in a phase-leg structure. To facilitate the reader to understand the working principle, it demonstrates the controlled SiC MOSFETs (.sub.H and .sub.L) with the junction capacitors, representing the devices' dynamic characteristics. The meaning of each symbol in FIG. 3 is similar to that shown in FIG. 1. Only to distinguish upper and lower devices, adding marks “1” and “2” respectively, or marks “L” and “H”. R.sub.1 and R.sub.2 represent the drive resistor of the upper and lower devices, respectively. C.sub.1 and C.sub.2 represent the auxiliary capacitor of the upper and lower devices, respectively. .sub.P1 and .sub.P2 represent the auxiliary MOSFET of the upper and lower devices, respectively. As the active device in the phase-leg, .sub.H is turning on and off under the control of signal S.sub.1. .sub.L is the non-active device in the phase-leg, and its control signal S.sub.2 steady at a low level to keep the channel of .sub.L turning off and only its parasitic body diode is used for freewheeling.

[0081] The miller capacitance C.sub.gdH and C.sub.gdL of the controlled MOSFETs decrease with their drain voltage. For understanding, the analysis introduces the piecewise linearization curve to approximate the actual curve for simplification. When the drain voltage is larger than the gate voltage, the value of miller capacitance is C.sub.gd1. When the drain voltage is less than the gate voltage, the value of miller capacitance is C.sub.gd2. The output current at the midpoint of the phase-leg is approximately constant during the switching process and represented by I.sub.L.

[0082] FIG. 4a and FIG. 4b show theoretical waveforms of the circuit of FIG. 3 in the dynamic processes of turning on and off .sub.H, with the initial moments being the moment when S.sub.1 changes from the low level to the high level and the moment when S.sub.1 changes from the high level to the low level, respectively. The two dynamic processes each have 4 modes, which will be detailed below:

[0083] Turning on .sub.H, as shown in FIG. 4a

[0084] Turn-on mode 1: during the turn-on delay time t.sub.d(on). At t=0 time point, S.sub.1 changes from low level to high level. The driver IC charges C.sub.1 through R.sub.1. Hence, the drive voltage v.sub.GS1* increases, gradually rising from V.sub.EE1 to V.sub.CC1. Because of the negative feedback mechanism, the gate voltage v.sub.GS1 tracks v.sub.GS1* and also increases gradually. It should be noticed that, as mentioned above, the NFAGD system is a unity-feedback type 1 control system. There is some error in the tracking of the ramping drive reference v.sub.GS1*. The tracking error will not affect the regular operation due to the large value of the static velocity error constant. In this mode, since v.sub.GS1 is still less than the threshold voltage V.sub.GS,th, the channel of .sub.H is in the off-state, i.sub.D1=0 can be got. V.sub.DS1 stands still at V.sub.DC, and this mode ends when v.sub.GS1 reaches V.sub.GS,th.

[0085] Turn-on mode 2: during the current rise time t.sub.ri, v.sub.GS1 starts from the threshold voltage V.sub.GS,th, and rises to V.sub.GS,IL, which indicates the value of v.sub.GS1 that can maintain channel current at I.sub.L. V.sub.DS1 stands still at V.sub.DC. The current i.sub.D1 rises from 0 to I.sub.L. During this process, due to the decrease of the passive device's current i.sub.D2, the gate voltage of .sub.L v.sub.GS2 increases slightly but not large enough to trigger the conduction of .sub.P2. The mode ends at the moment when the current i.sub.D1 rises to I.sub.L.

[0086] Turn-on mode 3: during the first voltage decrease time t.sub.fv1, the gate voltage of .sub.H(v.sub.GS1) still tracks v.sub.GS1* as the negative feedback controls. The drive circuit continues to charge C.sub.gdH and C.sub.gsH through the active control of auxiliary MOSFET. This charging current weakens the influence of the miller effect on the gate voltage. The miller platform appears for a very short time, which is not apparent in the waveform. In this mode, v.sub.DS1 falls from V.sub.DC. Since the drain voltage is still larger than the gate voltage, the value of C.sub.gdH is still relatively small (C.sub.gd1). Therefore v.sub.DS1 falls at a relatively fast rate at this stage. .sub.L'S drain voltage (v.sub.DS2) rises rapidly, which induces .sub.L's gate voltage (v.sub.GS2) rises significantly. Due to the negative feedback mechanism, when the electric potential of S.sub.P2 is higher than that of D.sub.P2 and the electric potential difference exceeds the threshold voltage V.sub.th, leading to the conduct of .sub.P2. Then the drive IC discharges the input capacitance of .sub.L (C.sub.issL) through the channel of .sub.P2. Hence the .sub.L's gate voltage v.sub.GS2 decreases, returning to V.sub.EE2 and the disturbance is suppressed. This mode ends when v.sub.DS1 falls to a value equal to v.sub.GS1.

[0087] Turn-on mode 4: during the second voltage decrease time t.sub.fv2, due to the negative feedback mechanism, the gate voltage v.sub.GS1 still rises along with v.sub.GS1, instead of remaining unchanged at V.sub.GS,IL. v.sub.DS1 continues to fall. Since the drain voltage is less than the gate voltage, the value of C.sub.gdH is relatively large (C.sub.gd2), and the falling rate of v.sub.DS1 in this stage is relatively slow. This mode ends when v.sub.DS1 descends to V.sub.DS(on).

[0088] After the turn-on mode 4, due to the negative feedback mechanism, the gate voltage v.sub.GS1 still rises to the bias voltage V.sub.CC1, tracking its drive reference signal v.sub.GS1*. At this moment, the turn-on process is finally completed.

[0089] Turning off .sub.H, as shown in FIG. 4b

[0090] Turn-off mode 1: during the turn-off delay time t.sub.d(off). At t=0 time point, S.sub.1 changes from high level to low level. The driver IC discharges C.sub.1 through R.sub.1. Hence, the drive voltage v.sub.GS1* decreases, gradually falling from V.sub.CC1 to V.sub.EE1. Because of the negative feedback mechanism, the gate voltage v.sub.GS1 tracks v.sub.GS1* and also decreases gradually. It should be noticed that, as mentioned above, the NFAGD system is a unity-feedback type 1 control system. There is some error in the tracking of the ramping drive reference v.sub.GS1*. The tracking error will not affect the regular operation due to the large value of the static velocity error constant. In this mode, since v.sub.GS1 is still larger than the threshold voltage V.sub.GS,th, the channel of .sub.H is in the on-state, i.sub.D1=I.sub.L can be got. V.sub.DS1 stands still at V.sub.DS(on), and this mode ends when v.sub.GS1 reaches V.sub.GS,IL.

[0091] Turn-off mode 2: during the first voltage rise time t.sub.rv1, the gate voltage of .sub.H(v.sub.GS1) still tracks v.sub.GS1* as the negative feedback controls. The drive circuit continues to discharge C.sub.gdH and C.sub.gsH through the active control of auxiliary MOSFET. This charging current weakens the influence of the miller effect on the gate voltage. The miller platform appears for a very short time, which is not apparent in the waveform. In this mode, v.sub.DS1 rises from V.sub.DS(on). Since the drain voltage is still less than the gate voltage, the value of C.sub.gdH is still relatively large (C.sub.gd2). Therefore v.sub.DS1 rises at a relatively slow rate at this stage. This mode ends when v.sub.DS1 rises to a value equal to v.sub.GS1.

[0092] Turn-off mode 3: during the second voltage rise time t.sub.rv2, due to the negative feedback mechanism, the gate voltage v.sub.GS1 still decreases along with v.sub.GS1* v.sub.DS1 continues to increase. Since the drain voltage is larger than the gate voltage, the value of C.sub.gdH is relatively small (C.sub.gd1), and the rising rate of v.sub.DS1 in this stage is relatively fast. .sub.L's drain voltage (v.sub.DS2) falls rapidly, which induces .sub.L's gate voltage (v.sub.GS2) to fall significantly. Due to the negative feedback mechanism, when the electric potential of D.sub.P2 is higher than that of S.sub.P2 and the electric potential difference exceeds the threshold voltage of the parasitic body diode of .sub.P2. The drive IC charges the input capacitance of .sub.L (C.sub.issL) through the parasitic body diode of .sub.P2. Hence the L's gate voltage v.sub.GS2 increases, returning to V.sub.EE2 and the disturbance is suppressed. This mode ends when v.sub.DS1 rises to a value equal to V.sub.DC.

[0093] Turn-off mode 4: during the current fall time t.sub.fi, due to the negative feedback mechanism, the gate voltage v.sub.GS1 still falls along with v.sub.GS1* until it reaches V.sub.GS,th. In this mode, v.sub.DS1 remains unchanged in V.sub.DC. This mode ends when i.sub.D1 falls to 0.

[0094] After the turn-off mode 4, due to the negative feedback mechanism, the gate voltage v.sub.GS1 still falls to the bias voltage V.sub.EE1, tracking its drive reference signal v.sub.GS1*. At this moment, the turn-off process is finally completed.

[0095] The exemplary parameters for disclosed NFAGD are designed with the following considerations.

[0096] To better understand the combined operation mechanism based on negative feedback control in the drive-semiconductor system, this paper would also show the design principle of the negative feedback active gate drive (NFAGD).

A. Selection Principle for the Controlled SiC MOSFET

[0097] When adopting the NFAGD, the controlled SiC MOSFET should be determined according to the converters' operation condition, like the conventional semiconductor power device derived by other drive circuits. Generally, the SiC MOSFET is selected by the maximum working voltage and current of the device to ensure a safe operating area. For example, in this paper's experiment, the 1200V SiC MOSFET IMZ120R030M1H with high commercialization degree in high power conditions is selected as the controlled SiC MOSFET demonstrate and verify the technical feasibility of the proposed method. The maximum drain-source voltage is 1200V, the maximum drain current 56 A, and the internal gate resistance is 3Ω.

B. Drive IC Selection and Peripheral Circuit Design Principles

[0098] The proposed NFAGD has the effect of stabilizing the gate voltage, attenuating the interference effects from the pulse voltage and pulse current. However, it does not eliminate the gate instability problem once for all. Considering the low threshold voltage of the controlled SiC MOSFET (approximately 2˜4V), the negative turn-off bias voltage is critical. While the turn-on bias voltage usually relates to the on-state resistance, whose design should refer to a typical suggestion from the datasheet. This paper recommends the turn-on bias voltage V.sub.CC=15˜22V and turn-off bias voltage V.sub.EE=−5˜0V. Based on the above considerations, the bias voltages V.sub.CC=20V and V.sub.EE=−5V are adopted in the subsequent design.

[0099] This paper recommends the drive IC's isolation part has a common mode transient immunity CMTI≥100V/ns (within the full temperature range). The drive IC output current should be no less than (V.sub.CC−V.sub.EE)/R.sub.g, where R.sub.g is the internal gate resistance of the controlled SiC MOSFET. For example, the selected controlled SiC MOSFET (IMZ120R030M1H) internal gate resistance R.sub.g=3Ω, the bias voltages V.sub.CC=20V and V.sub.EE=−5V is adopted. In one implementation, the drive chip used is 1ED3124MU12H with an output current up to 14 A.

C. Selection Principle for the auxiliary MOSFET The auxiliary MOSFET is the P-channel MOSFET with a relatively low voltage rating in the drive circuit without flowing through a large current and endues large voltage. Meanwhile, to ensure the control accuracy, the transconductance gain (g.sub.m) of the auxiliary MOSFET should be larger than 1 Siemens. The auxiliary MOSFET bears a certain current and voltage during the switching transients of the controlled SiC MOSFET. Hence, the auxiliary MOSFET's maximum current and voltage should be designed according to the bias voltages V.sub.CC and V.sub.EE.

[0100] The auxiliary MOSFET is subjected to a certain level of voltage and current during the switching transients of the controlled SiC MOSFET. Hence the maximum voltage and current of the auxiliary MOSFET should be designed according to the bias voltages V.sub.CC and V.sub.EE. We recommend the maximum voltage should be no less than V.sub.CC−V.sub.EE, the maximum current should be no less than (V.sub.CC−V.sub.EE)/R.sub.g. Based on the above analysis, FDS9435A is used as the P-channel auxiliary MOSFET, with a drain-source breakdown voltage of 30(V), a maximum permissible continuous drain current of 25(A), and a transconductance gain of 10(S).

D. Design Principles for Auxiliary Capacitors and Drive Resistors

[0101] The auxiliary capacitor and the drive resistor (i.e., C and R in FIG. 1) connected to the output end of the push-pull drive circuit jointly determines the rising/falling speed of v.sub.GS. Generally, the input capacitance of the controlled MOSFET is about the nF level, and the transconductance gain of the auxiliary MOSFET is much greater than 1(S). Therefore, the open-loop gain of the gate negative feedback active MOSFET-driving circuit is large enough. When v.sub.GS tracks the ramp-rising (falling) v.sub.GS*, the deviation between the two is quite small, and v.sub.GS* and v.sub.GS have an approximately equal rising/falling speed. The auxiliary capacitor C also provides the function of decoupling, for shortening the “electrical circumference” of the loop composed of the output end of the push-pull drive circuit and the gates-sources of the auxiliary MOSFET and the controlled MOSFET. The recommended auxiliary capacitor Cat a site of the power loop of the phase-leg circuit having an undamped self-sustained oscillation frequency has an impedance not greater than 0.2Ω, that is:

[00004]$\frac{\sqrt{L_o{C}_{oss}}}{C}\le 0.2.Math.C\ge 5\sqrt{L_o{C}_{oss}}$

[0102] In this embodiment, the controlled MOSFET (IMZ120R030M1H) has an output capacitance of C.sub.oss=116 pF, and the stray inductance Lo of the power loop is estimated to be 50 nH. According to the foregoing equation, the auxiliary capacitor C should not be smaller than 12 nF. Engineeringly, the selected auxiliary capacitor C=20 nF so as to ensure that the impedance at the site of the power loop having the undamped self-sustained oscillation frequency has an impedance that is small enough.

[0103] After the auxiliary capacitor C is selected, design of the drive resistor R can be started. The product of the drive resistor R and the auxiliary capacitor C is τ=RC, being the charging/discharging time constant of the resistance-capacitance circuit. The charging/discharging time constant τ is inversely proportional to the rising/descending slope of the gate-source voltage. In other words, the larger the charging/discharging time constant τ is, the slower the gate-source voltage rises/falls, in turn leading to slower switching speed of the controlled MOSFET. That means if a higher switching speed of the controlled MOSFET is desired, such as when it is needed to reduce loss and enhance efficiency, a smaller charging/discharging time constant τ is preferable. However, additional functional concerns of the drive resistor R are current limits and protection it provides for the push-pull drive circuit. At the beginning of the switching operation, the current of the push-pull drive circuit charging/discharging the auxiliary capacitor C through the drive resistor R reaches the peak (V.sub.CC−V.sub.EE)/R. For making the most use of the loading budget of the drive chip selected to the present embodiment and realizing a relatively fast switching speed of the MOSFET, in the present embodiment, the charging/discharging current peak (V.sub.CC−V.sub.EE)/R is such designed that it is 70% of the peak output current of the drive chip. In particular, the 70% of the maximum output current of maximum output current of 1ED3124MU12H with the on voltage V.sub.CC=20V and the off voltage V.sub.EE=−5V is about 10 A. Therefore, the drive resistor R=2.5Ω, and the corresponding charging/discharging time constant τ=50 nS. It is to be noted that the described design of the drive resistor R is illustrative, and in various industrial applications, the drive resistor may be flexibly designed otherwise and adapted to practical needs in terms of efficiency, loss, and electromagnetic compatibility, together with the selection of the auxiliary capacitor.

[0104] It is to be noted that the described design of the drive resistor R is illustrative, and in various industrial applications, the drive resistor may be flexibly designed otherwise and adapted to practical needs in terms of efficiency, loss, and electromagnetic compatibility, together with the selection of the auxiliary capacitor.

[0105] FIG. 5a shows a diagram of an experimental circuit with the conventional gate drive without suppression for comparison with one embodiment of the present invention; FIG. 5b shows a diagram of an experimental circuit with the conventional gate drive that used passive suppression for comparison with one embodiment of the present invention; FIG. 5c shows a diagram of an experimental circuit with one embodiment of the present invention;

[0106] Each of these was provided with a drive pulse to drive the active MOSFET .sub.H and was provided with a negative voltage bias to turn off the passive MOSFET .sub.L. In the embodiment, three instances were set up to compare how the gate-source voltage v.sub.GS2 of the passive tube .sub.L could be interfered for demonstrating the effectiveness of the NFAGD in stabilizing the gate-source voltage.

[0107] FIG. 6a through FIG. 6c exhibit experimental waveforms of an experimental circuit with the conventional gate drive without suppression for comparison with one embodiment of the present invention. The drivers for the active tube .sub.H and the passive tube .sub.L were only each provided with a drive resistor. The corresponding drive resistors were both of 10Ω. As shown in FIG. 6a, the gate-source voltage v.sub.GS2 of the passive tube .sub.L was interfered and showed obvious oscillation, with a forward interference magnitude up to 7.9V, and a negative interference magnitude up to 7V As shown in FIG. 6b, in the process where the drain-source voltage v.sub.DS2 of the passive tube .sub.L rose, the rising slope of 100V-800V was about 43.7V/ns. As shown in FIG. 6c, in the process where the drain-source voltage v.sub.DS2 of the passive tube .sub.L fell, the descending slope of 800V-100V was about 51.25V/ns. It is clear that the drain-source voltage v.sub.DS2 of the passive tube .sub.L rose and fell faster, making the gate-source voltage v.sub.GS2 of .sub.L obviously instable.

[0108] FIG. 7a through 7c show experimental waveforms of an experimental circuit with the conventional gate drive that used passive suppression for comparison with one embodiment of the present invention. The driving circuit for the active tube .sub.H and for the passive tube .sub.L was realized using gate-source shunt auxiliary capacitors. The drive resistors R.sub.1, R.sub.2 were 10Ω, and the gate-source shunt auxiliary capacitors C.sub.a1, C.sub.a2 were 2 nF. As shown in FIG. 7a, the interference-induced oscillation at the gate-source voltage v.sub.GS2 of the passive tube .sub.L had a certain mitigate, with the forward interference magnitude being about 4V, and the negative interference magnitude being about 4V, too. As shown in FIG. 7b, in the process where the drain-source voltage v.sub.DS2 of the passive tube .sub.L rose, the rising slope of 100V-800V was about 42.5V/ns. As shown in FIG. 7c, in the process where the drain-source voltage v.sub.DS2 of the passive tube .sub.L fell, the descending slope of 800V-100V was about 9.6V/ns. Compared to the switching speed of the embodiment as shown in FIG. 6a through FIG. 6c significant decrease can be observed. It is thus clear that while passive gate oscillation suppression using gate-source shunt auxiliary capacitors effectively suppressed gate-source oscillation, the switching speed was sacrificed as a cost.

[0109] FIG. 8a through FIG. 8c show experimental waveforms of one embodiment of the present invention using the NFAGD. The driving circuits for the active tube .sub.H and for the passive tube .sub.L were both realized using NFAGD. As shown in FIG. 8a, interference-induced oscillation at the gate-source voltage v.sub.GS2 of the passive tube .sub.L was mitigated more significantly, with the forward interference magnitude being about 3V and the negative interference magnitude being about 3V, too. As shown in FIG. 8b, in the process where the drain-source voltage v.sub.DS2 of the passive tube .sub.L rose, the rising slope of 100V-800V was about 50V/ns. As shown in FIG. 8c, in the process where the drain-source voltage v.sub.DS2 of the passive tube .sub.L fell, the descending slope of 800V-100V was about 50V/ns. Compared to the passive suppression approach of the embodiment shown in FIG. 7a through FIG. 7c, the gate negative feedback active suppression circuit of the present invention provided more significant suppression of oscillation for the gate-source voltage, without sacrificing the switching speed. With the auxiliary capacitor (20 nF), compared to the switching speed of the embodiment as shown in FIG. 6a through FIG. 6c, the present invention improved the switching speed definitely.

[0110] An alternative mode for implementing the present invention will be given below.

[0111] As shown in FIG. 1, a negative feedback active gate drive (NFAGD), for connecting a drive signal to turn on and off a power MOSFET, i.e. the controlled MOSFET, comprises a push-pull drive circuit, a drive resistor, an auxiliary capacitor, and an auxiliary MOSFET.

[0112] The push-pull drive circuit, for generating a drive voltage v.sub.GS* that controls a wide bandgap semiconductor device such as a SiC MOSFET or a Gallium Nitride Transistor. In particular, it provides a driving current to drive the controlled MOSFET. The drive signal is connected to the push-pull drive circuit (usually composed by the conventional gate drive chip and its power supplies), and the push-pull drive circuit and the third node are connected in series.

[0113] The drive resistor R has its one end connected in series with the push-pull drive circuit and an opposite end connected to the first node, for limiting a charging/discharging current applied to an auxiliary capacitor C by the push-pull drive circuit, thereby providing current limits and protection. A voltage difference between the first node and a source of the controlled MOSFET is the drive voltage.

[0114] The auxiliary capacitor C has one end connected to the first node, and an opposite end connected to the source S of the controlled MOSFET through the third node, so as to work with the drive resistor R to form the passive network for regulating a switching speed of the controlled MOSFET.

[0115] The auxiliary MOSFET is a P-channel MOSFET. Its source connected to the gate of the controlled MOSFET for creating a negative-feedback regulating mechanism, and its drain is connected to a drive voltage. The drive voltage is a voltage of a push-pull drive circuit that has been filtered by a passive network. The drain D.sub.p and the gate G.sub.p of the P-channel MOSFET are connected in series with the drive resistor R through the second node. The source S.sub.p of the P-channel MOSFET is connected to the gate G of the controlled MOSFET, for creating a negative-feedback regulating mechanism, thereby realizing self-stability of the gate voltage.

[0116] The push-pull drive circuit usually comprises a conventional gate drive chip and its power supplies, denoted as an on-bias voltage V.sub.CC, and an off-bias voltage V.sub.EE. The conventional gate drive chip has an output power positive terminal connected to the positive pole of the on-bias voltage V.sub.CC. The conventional gate drive chip has an output power negative terminal connected to the negative pole of the off-bias voltage V.sub.EE. The conventional gate drive chip has a drive output terminal connected to one end of the drive resistor R and has a drive input terminal connected to the drive signal. The negative pole of the on-bias voltage V.sub.CC and the positive pole of the off-bias voltage V are both connected to the third node. The push-pull drive circuit can be simply realized using a conventional gate drive chip or a totem pole circuit for MOSFETs. The V.sub.CC is the on-bias voltage, and the recommended on-bias voltage value is 18˜22V The V.sub.EE is the off-bias voltage, and the recommended off-bias voltage value is −2.5˜−5V The recommended common-mode transient immunity (CMTI) for the drive chip is ≥100V/ns (over the full temperature range). In terms of driving capability, the chip output current should not be smaller than (V.sub.CC−V.sub.EE)/R.sub.g, where R.sub.g is the gate internal gate resistance of the controlled MOSFET.

[0117] Since the P-channel MOSFET has to bear certain levels of voltages and currents when the controlled MOSFET is switching, for ensuring its working safety, the levels of the voltages and currents of the auxiliary MOSFET have to be determined according to the on-bias voltage V.sub.CC and the off-bias voltage V.sub.EE of the designed push-pull drive circuit, and the gate properties of the controlled MOSFET. The recommended drain-source breakdown voltage is not smaller than V.sub.CC−V.sub.EE, and the recommended maximum permissible continuous drain current is not smaller than (V.sub.CC−V.sub.EE)/R.sub.g. Meanwhile, for ensuring the control precision, the transconductance gain of the P-channel auxiliary MOSFET should be much greater than 1(S).

[0118] Functionally, the auxiliary capacitor C not only regulates the switching speed of the controlled MOSFET, but also helps to minimize the area of the loop formed by the push-pull drive circuit, the auxiliary MOSFET, and the gate and source of the controlled MOSFET, realizing high-frequency decoupling of the drive loop.

[0119] The present invention has been described with reference to the preferred embodiments and it is understood that the embodiments are not intended to limit the scope of the present invention. Moreover, as the contents disclosed herein should be readily understood and can be implemented by a person skilled in the art, all equivalent changes or modifications which do not depart from the concept of the present invention should be encompassed by the appended claims.