ARTIFICIAL NEURAL NETWORK COMPRISING AN ANALOG ARRAY AND A DIGITAL ARRAY

Abstract

Numerous examples are described for providing an artificial neural network system comprising an analog array and a digital array. In certain examples, an analog array and a digital array are coupled to shared bit lines. In other examples, an analog array and a digital array are coupled to separate bit lines.

Claims

1. An artificial neural network system, comprising: an analog array of non-volatile memory cells arranged into rows and columns; a digital array of non-volatile memory cells arranged into rows and columns; and a plurality of bit lines, wherein each bit line in the plurality of bit lines is connected to a column of non-volatile memory cells in the analog array and a column of non-volatile memory cells in the digital array.

2. The artificial neural network system of claim 1, comprising: a first row decoder coupled to the analog array; and a first high voltage row decoder coupled to the analog array.

3. The artificial neural network system of claim 2, comprising: a second row decoder, separate from the first row decoder, coupled to the digital array; and a second high voltage row decoder, separate from the first high voltage row decoder coupled to the digital array.

4. The artificial neural network system of claim 3, wherein during a read of the analog array, the first row decoder and the first high voltage row decoder apply a first set of voltages to the analog array.

5. The artificial neural network system of claim 4, wherein during a read of the digital array, the second row decoder and the second high voltage row decoder apply a second set of voltages to the digital array, the second set of voltages different than the first set of voltages.

6. The artificial neural network system of claim 3, comprising a read circuit used during a read of the analog array and a read of the digital array.

7. The artificial neural network system of claim 6, wherein during a read of the digital array, the read circuit outputs a “1” if a majority of output bits generated by the read circuit are a “1” and outputs a “0” if less than a majority of output bits generated by the read circuit are a “1”.

8. The artificial neural network system of claim 1, wherein the digital array comprises a user data array and a system data array.

9. The artificial neural network system of claim 8, wherein a speed of one or more of a read, program, or erase for the system data array is slower than for the user data array.

10. The artificial neural network system of claim 8, wherein a speed of a read of the system data array is slower than for the user data array.

11. The artificial neural network system of claim 8, wherein an endurance of the system data array is less than an endurance of the user data array.

12. An artificial neural network system, comprising: an analog array of non-volatile memory cells arranged into rows and columns; a digital array of non-volatile memory cells arranged into rows and columns, the analog array and the digital array fabricated on a same semiconductor die; a first plurality of bit lines, wherein each bit line in the first plurality of bit lines is coupled to a column of non-volatile memory cells in the analog array; and a second plurality of bit lines, wherein each bit line in the second plurality of bit lines is coupled to a column of non-volatile memory cells in the digital array and the second plurality of bit lines are disconnected from the first plurality of bit lines.

13. The artificial neural network system of claim 12, comprising: a first row decoder coupled to the analog array; and a first high voltage row decoder coupled to the analog array.

14. The artificial neural network system of claim 13, comprising: a second row decoder, separate from the first row decoder, coupled to the digital array; and a second high voltage row decoder, separate from the first high voltage row decoder, coupled to the digital array.

15. The artificial neural network system of claim 14, wherein during a read of the analog array, the first row decoder and the first high voltage row decoder apply a first set of voltages to the analog array.

16. The artificial neural network system of claim 15, wherein during a read of the digital array, the second row decoder and the second high voltage row decoder apply a second set of voltages to the digital array, the second set of voltages different than the first set of voltages.

17. The artificial neural network system of claim 12, wherein the first plurality of bit lines and the second plurality of bit lines share a diffusion layer.

18. The artificial neural network system of claim 17, wherein the first plurality of bit lines and the second plurality of bit lines have different metal interconnects.

19. The artificial neural network system of claim 12, wherein the first plurality of bit lines and the second plurality of bit lines have different diffusion layers.

20. The artificial neural network system of claim 18, wherein the first plurality of bit lines and the second plurality of bit lines have different metal interconnects.

21. The artificial neural network system of claim 12, wherein the digital array comprises a system data array.

22. The artificial neural network system of claim 12, comprising a read circuit used during a read of the analog array and a read of the digital array.

23. The artificial neural network system of claim 21, wherein during a read of the digital array, a read circuit outputs a “1” if a majority of output bits generated by the read circuit are a “1” and outputs a “0” if less than a majority of output bits generated by the read circuit are a “1”.

24. The artificial neural network system of claim 12, comprising: a second digital array of non-volatile memory cells arranged into rows and columns.

25. The artificial neural network system of claim 24, wherein each bit line in the second plurality of bit lines is coupled to a column of non-volatile memory cells in the second digital array.

26. The artificial neural network system of claim 12 wherein the digital array of non-volatile memory cells comprises a user data array and a system data array.

27. The artificial neural network system of claim 26, wherein a speed of one or more of read, program, or erase operations for the system data array is slower than for the user data array.

28. The artificial neural network system of claim 26, wherein a speed of a read operation for the system data array is slower than for the user data array.

29. The artificial neural network system of claim 26, wherein an endurance of the system data array is less than an endurance of the user data array.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0092] FIG. 1 is a diagram that illustrates an artificial neural network.

[0093] FIG. 2 depicts a prior art split gate flash memory cell.

[0094] FIG. 3 depicts another prior art split gate flash memory cell.

[0095] FIG. 4 depicts another prior art split gate flash memory cell.

[0096] FIG. 5 depicts another prior art split gate flash memory cell.

[0097] FIG. 6 is a diagram illustrating the different levels of an example artificial neural network utilizing one or more non-volatile memory arrays.

[0098] FIG. 7 is a block diagram illustrating a VMM system.

[0099] FIG. 8 is a block diagram illustrates an example artificial neural network utilizing one or more VMM systems.

[0100] FIG. 9 depicts another example of a VMM system.

[0101] FIG. 10 depicts another example of a VMM system.

[0102] FIG. 11 depicts another example of a VMM system.

[0103] FIG. 12 depicts another example of a VMM system.

[0104] FIG. 13 depicts another example t of a VMM system.

[0105] FIG. 14 depicts a prior art long short-term memory system.

[0106] FIG. 15 depicts an example cell for use in a long short-term memory system.

[0107] FIG. 16 depicts an example implementation of the cell of FIG. 15.

[0108] FIG. 17 depicts another example implementation of the cell of FIG. 15.

[0109] FIG. 18 depicts a prior art gated recurrent unit system.

[0110] FIG. 19 depicts an example cell for use in a gated recurrent unit system.

[0111] FIG. 20 depicts an example implementation of the cell of FIG. 19.

[0112] FIG. 21 depicts another example implementation of the cell of FIG. 19.

[0113] FIG. 22 depicts another example of a VMM system.

[0114] FIG. 23 depicts another example of a VMM system.

[0115] FIG. 24 depicts another example of a VMM system.

[0116] FIG. 25 depicts another example of a VMM system.

[0117] FIG. 26 depicts another example of a VMM system.

[0118] FIG. 27 depicts another example of a VMM system.

[0119] FIG. 28 depicts another example of a VMM system.

[0120] FIG. 29 depicts another example of a VMM system.

[0121] FIG. 30 depicts another example of a VMM system.

[0122] FIG. 31 depicts another example of a VMM system.

[0123] FIG. 32 depicts another example of a VMM system.

[0124] FIG. 33 depicts another example of a VMM system.

[0125] FIG. 34 depicts an example of a VMM system comprising a digital array.

[0126] FIG. 35 depicts an example of a VMM system.

[0127] FIG. 36 depicts an example of a VMM system comprising a digital array.

[0128] FIG. 37 depicts an example of a VMM system comprising a digital array.

[0129] FIG. 38 depicts additional aspects of the VMM system of FIG. 37.

[0130] FIGS. 39A, 39B, and 39C depict example designs for VMM system of FIG. 37.

[0131] FIG. 40 depicts an example of a VMM system comprising a digital array.

[0132] FIG. 41 depicts an example of a digital array.

[0133] FIG. 42A depicts a differential current-to-voltage converter.

[0134] FIG. 42B depicts a differential successive address register analog-to-digital converter.

[0135] FIG. 43 depicts an example read operation of an analog array and a digital array.

DETAILED DESCRIPTION OF THE INVENTION

[0136] The artificial neural networks described herein utilize a combination of CMOS technology and non-volatile memory arrays.

VMM System Overview

[0137] FIG. 35 depicts a block diagram of VMM system 3500. VMM system 3500 comprises VMM array 3501, which includes analog memory cells as well as digital memory cells, row decoder 3502, high voltage decoder 3503, column decoders 3504, bit line drivers 3505, input circuit 3506, output circuit 3507, control logic 3508, and bias generator 3509. VMM system 3500 further comprises high voltage generation block 3510, which comprises charge pump 3511, charge pump regulator 3512, and high voltage analog precision level generator 3513. VMM system 3500 further comprises (program/erase, or weight tuning) algorithm controller 3514, analog circuitry 3515, control engine 3516 (which may perform functions such as arithmetic functions, activation functions, embedded microcontroller logic, without limitation), and test control logic 3517. The systems and methods described below can be implemented in VMM system 3500.

[0138] The input circuit 3506 may include circuits such as a DAC (digital to analog converter), DPC (digital to pulses converter, digital to time modulated pulse converter), AAC (analog to analog converter, such as a current to voltage converter, logarithmic converter), PAC (pulse to analog level converter), or any other type of converters. The input circuit 3506 may implement one or more of normalization, linear or non-linear up/down scaling functions, or arithmetic functions. The input circuit 3506 may implement a temperature compensation function for input levels. The input circuit 3506 may implement an activation function such as ReLU or sigmoid. The output circuit 3507 may include circuits such as an ADC (analog to digital converter, to convert neuron analog output to digital bits), AAC (analog to analog converter, such as a current to voltage converter, logarithmic converter), APC (analog to pulse(s) converter, analog to time modulated pulse converter), or any other type of converters. The output circuit 3507 may implement an activation function such as rectified linear activation function (ReLU) or sigmoid. The output circuit 3507 may implement one or more of statistic normalization, regularization, up/down scaling/gain functions, statistical rounding, or arithmetic functions (e.g., add, subtract, divide, multiply, shift, log) for neuron outputs. The output circuit 3507 may implement a temperature compensation function for neuron outputs or array outputs (such as bitline output) so as to keep power consumption of the array approximately constant or to improve precision of the array (neuron) outputs such as by keeping the IV slope approximately the same.

[0139] As discussed above, a neural network may comprise many different layers, and within each layer, many calculations may be performed involving stored weight values in one or more arrays within that layer. Some layers will be used more than other layers, and it can be appreciated that such layers are more important to the overall accuracy of the neural network based on their high frequency of use.

[0140] FIG. 36 depicts VMM system 3600, which comprises analog array 3601, row decoder 3602, high voltage decoder 3603, digital array 3604, row decoder 3605, and high voltage decoder 3606. Analog array 3601 and digital array 3604 share the same diffusion and metal interconnect bit lines. Unlike in the prior art, digital array 3604 has its own row decoder (row decoder 3605) and its own high voltage decoder (3606), which allows for a first set of voltages and a second set voltages to be applied concurrently to analog array 3601 and digital array 3604, respectively. Optionally, analog array 3601 and digital array 3604 are fabricated on the same semiconductor die.

[0141] Digital array 3604 optionally may include a first array, which can be referred to as user data array 3607, comprising rows for storing digital data stored and retrieved by external sources (such as user data or operating system code for a computer) and a second array, which can be referred to as system data array 3608 comprising rows for storing digital system data, i.e. data that is used by VMM system 3600 itself and is not stored and retrieved by external sources, which is sometimes referred to as digital non-volatile registers (NVRs) or information rows or an information array. Examples of data that might be stored in system data array 3608 include user ID, trim bits, configuration bits, manufacturing info, security codes, password, lock bit, and other system data. The performance of system data array 3608 may be relaxed compared to user data array 3607.

[0142] For example, the content of system data array 3608 may be read once at power up or at the beginning of a system operation and not read thereafter during operation. As another example, content of system data array 3608 may be erased or programmed only a few times throughout its lifetime usage. Thus, a read, program, or erase operation of system data array 3608 can occur at a slower speed than for the user data array without much performance loss since the system data array is used so rarely. This difference in speed can be implemented in the VMM system 3600, for example, to save power when operating on system data array 3608.

[0143] As another example, non-volatile memory cells have a characteristic referred to as endurance, which refers to the number of times the non-volatile memory cell may be programmed or erased before it degrades to the point of no longer being reliable or usable. Thus, system data array 3608 may be provided with non-volatile memory cells of a lower endurance than non-volatile memory cells of user data array 3607 since system data array 3608 will be used much less during operation than user data array 3607.

[0144] Table 9 depicts example operating voltages used in VMM system 3600, where CG-main, EG-main, BL-main, and SL-main are a first set of voltages applied to the control gate terminal, erase gate terminal, bit line terminal, and source line terminal, respectively, of one or more memory cells in analog array 3601, by row decoder 3702 and high voltage decoder 3703, and CG-DIG, EG-DIG, BL-DIG, and SL-DIG are a second set of voltages applied to a control gate terminal, erase gate terminal, bit line terminal, and source line terminal, respectively, of one or more cells in digital array 3604, by row decoder 3705 and high voltage decoder 3706:

TABLE-US-00009 TABLE No 9 Operating Voltages for VMM System 3600 in FIG. 36 CG- EG- BL- SL- CG- EG- BL- SL- Action main main main main DIG DIG DIG DIG Neural 1.5 V 0 V 0.6 V >=0 V 0 V 0 V 0.6 V >=0 V Read Digital 0 V 0 V 0.9 V 0 V 1.5 V-2.5 V 0 V-1.5 V 0.9 V 0 V Read

[0145] The ability to apply different sets of voltages to memory cells of analog array 3601 and memory cells of digital array 3604 enhances performance during neural read operations of analog array 3601 and digital read operations of digital array 3604, such as reducing leakage during read neural operations (caused by the ability to shut off the high current of the digital cells sharing the same bit lines as the analog cells) and higher speed for digital cells due to higher current levels.

[0146] FIG. 37 depicts an example VMM system 3700, which comprises analog array 3701, row decoder 3702, high voltage decoder 3703, digital array 3704 (optionally comprising user data array 3707 and system data array 3708), row decoder 3705, and high voltage decoder 3706. VMM system 3700 is similar to VMM system 3600, except that the bit lines coupled to analog array 3701 are disconnected from the bit lines coupled to digital array 3704, meaning that array 3701 and digital array 3704 have separate bit lines. However, the bitlines of analog array 3701 share the same diffusion layer as the bitlines of digital array 3704. In another example, the bitlines of analog array 3701 and the bitlines of digital array 3704 have different diffusion layers in addition to being disconnected. The diffusions may be disconnected between the analog and digital bit lines with one or more dummy rows. Optionally, analog array 3701 and digital array 3704 are fabricated on the same semiconductor die.

[0147] Table 10 depicts the operating voltages used in VMM system 3700, where CG-main, EG-main, BL-main, and SL-main are a first set of voltages applied to the control gate terminal, erase gate terminal, bit line terminal, and source line terminal, respectively, of one or more memory cells in analog array 3701 by row decoder 3702 and high voltage decoder 3703, and CG-IFR, EG-IFR, BL-IFR, and SL-IFR are a second set of voltages applied to a control gate terminal, erase gate terminal, bit line terminal, and source line terminal, respectively, of one or more memory cells in digital array 3704 by row decoder 3705 and high voltage decoder 3706.

TABLE-US-00010 TABLE No 10 Operating Voltages for VMM System 3700 in FIG. 37 EG- BL- CG- EG- BL- Action CG-main main main SL-main DIG DIG DIG SL-DIG Neural 1.5 V 0 V 0.6 V >=0 V 0 V 0 V 0 V 0 V Read Digital 0 V 0 V 0 V 0 V 2.5 V 1.5 V 0.9 V 0 V Read

[0148] FIG. 43 depicts an example read operation 4300 of an analog array (such as analog array 3601 and 3701 in FIGS. 36 and 37) and a digital array (such as digital array 3604 and 3704 in FIGS. 36 and 37). In operation 4301, during a read of an analog array, a first row decoder and a first voltage row decoder apply a first set of voltages to the analog array. In operation 4302, during a read of a digital array, a second row decoder and a second voltage row decoder apply a second set of voltages to the digital array, where the second set of voltages are different than the first set of voltages.

[0149] The ability to apply different sets of voltages to memory cells in analog array 3701 and memory cells in digital array 3704 enhances performance during neural read operations of analog array 3701 and digital read operations of digital array 3704, such as reducing leakage during read neural operations (caused by the ability to shut off the high current of the digital cells sharing the same bit lines as the analog cells) and higher speed for digital cells due to higher current levels.

[0150] FIG. 38 depicts additional aspects of VMM system 3700, which further comprises column decoder 3801 and column decoder 3802. Column decoder 3801 is coupled to bit lines BL0, . . . , BLn that are coupled to columns of analog array 3701. Column decoder 3802 is coupled to bit lines BLD0, . . . , BLDn that are coupled to columns of digital array 3704. Digital array 3704 optionally comprises user data array 3707 and system data array 3708. Thus, analog array 3701 and digital array 3704 have separate column decoders, further reducing leakage during read neural operations.

[0151] FIGS. 39A and 39B depict VMM systems 3901, 3902 respectively, which are example designs for VMM system 3700, and FIG. 39C depicts VMM system 3903 with is an example design for VMM system 3600.

[0152] In FIG. 39A, VMM system 3901 comprises analog array 3701 and digital array 3704. Example bit line BL0 is coupled to analog array 3701 and example bit line BLIFR0 is coupled to digital array 3704. The bit line BL0, coupled to analog array 3701, may be termed analog array bit line BL0, uses metal layers M1 to M4 in analog array 3701, and metal layers M2 to M4 also connect to peripheral circuitry (such as a column decoder), whereas bit line BLIFR0, coupled to digital array 3704, may be termed digital array bit line BLIFR0, uses metal layer M1 only. Analog array 3701 and digital array 3704 are part of the same physical array 3904. Physical array 3904 comprises substrate 3905 and diffusion layer 3906, which are both shared by analog array 3701 and digital array 3704. Physical array 3904 is partitioned by using disconnected metal interconnects for analog array 3701 and digital array 3704. For example, as can be seen, analog array bit line BL0 and digital array bit line BLIFR0 are disconnected from one another. Using the same physical array 3904 for both analog array 3701 and digital array 3704 reduces any physical effect from process uniformity and area overhead which would occur in the use of separate physical arrays.

[0153] In FIG. 39B, VMM system 3902 comprises analog array 3701 and digital array 3704. Example bit line BL0 is coupled to analog array 3701, and may be termed analog array bit line BL0, and example bit line BLIFR0 is coupled to digital array 3704, and may be termed digital array bit line BLIFR0. The analog array bit line B0 uses metal layers M1 to M4 in analog array 3701, and M2 to M4 also connect to peripheral circuitry (such as a column decoder), whereas digital array bit line BLIFR0 uses metal layer M1 only. Analog array 3701 and digital array 3704 are part of the same physical array 3907. Physical array 3907 comprises substrate 3908, diffusion layer 3909, and diffusion layer 3910. Substrate 3908 is shared by analog array 3701 and digital array 3704. Diffusion layer 3909 is part of analog array 3701 but not digital array 3704, and diffusion layer 3910 is part of digital array 3704 but not analog array 3701. Physical array 3907 is partitioned by using disconnected metal interconnects and separate diffusion layers for analog array 3701 and digital array 3704. For example, as can be seen, bit line BL0 serving analog array 3701 and bit line BLIFR0 serving digital array 3704 are disconnected from one another, and diffusion layer 3909 of analog array 3701 is separate from diffusion layer 3910 of digital array 3704. Using the same physical array 3907 for both analog array 3701 and digital array 3704 reduces any physical effect from process uniformity and area overhead which would occur in the use of separate physical arrays.

[0154] In FIG. 39C, VMM system 3903 comprises analog array 3601 and digital array 3604. Example bit line BL0 is coupled to analog array 3601 and example bit line BLIFR0 is coupled to digital array 3604. Here, bit line BL0 and bit line BLIFRO are the same bit line and both use metal layers M1 to M4. Metal layers M2 to M4 also connect to peripheral circuitry (such as a column decoder). Analog array 3601 and digital array 3604 are part of the same physical array 3911. Physical array 3911 comprises substrate 3912 and diffusion layer 3913, which are both shared by analog array 3601 and digital array 3604. Unlike physical arrays 3904 and 3907 in FIGS. 39A and 39B, physical array 3911 is not partitioned. For example, as can be seen, bit lines BL0 and BLIFR0 are the same and connect to analog array 3601 and digital array 3604. Using the same physical array 3911 for analog array 3601 and digital array 3604 reduces any physical effect from process uniformity and area overhead which would occur in the use of a separate physical arrays.

[0155] FIG. 40 depicts example VMM system 4000, which comprises analog array 4001, digital array 4002 (which optionally comprises user data array 4008 and system data array 4009), digital array 4003 (which optionally comprises user data array 4006 and system data array 4007), column decoder 4004, and column decoder 4005. Column decoder 4004 is coupled to bit lines BL0, . . . , BLn that are coupled to columns of analog array 4001. Column decoder 4005 is coupled to bit lines BLD0, . . . , BLDn that are coupled to columns of digital array 4002 and digital array 4003. Here, each of digital array 4003 and digital array 4002 can be used to store any type of digital data, including digital user data for a non-volatile storage operation. Analog array 4001 and digital arrays 4002, 4003 have separate column decoders, reducing leakage and enhancing performance (like faster speed). Optionally, two or more of analog array 4001, digital array 4003, and digital array 4002 are fabricated on the same semiconductor die.

[0156] FIG. 41 depicts digital array 4100, which can be any of digital arrays 3604, 3704, 4002, or 4003 discussed previously. In this example, digital array 4100 comprises user data array 4101 and system data array 4102. User data array 4101 and system data array 4102 can be accessed independently from one another, such that: (1) user data array 4101 is accessed at an average frequency f.sub.1 while system data array 4102 is accessed at an average frequency f.sub.2, where f.sub.1 and f.sub.2 can be different and f.sub.2 may be less than f.sub.1; (2) user data array 4101 has an access time of t.sub.1, while system data array 4102 has an access time of t.sub.2, where t.sub.1 and t.sub.2 can be different and t.sub.2 may be greater than t.sub.1, meaning that a read or write operation is slower for system data array 4102 than for user data array 4101; and (3) user data array 4101 has an endurance e.sub.1 while system data array 4102 has an endurance e.sub.2, where e.sub.1 and e.sub.2 can be different and e.sub.2 may be less than e.sub.1. This can allow for greater manufacturing tolerances and less power consumption for system data array 4102 compared to user data array 4101.

[0157] FIG. 42A depicts differential current-to-voltage converter 4201, which can read analog data from analog arrays 3601, 3701, and 4001 using a first set of voltages and read digital data from digital arrays 3604, 3704, 4002, and 4003 using a second set of voltages in VMM systems 3600, 3700, 4000, respectively.

[0158] Differential current-to-voltage converter 4201 comprises operational amplifier 4203; variable integrating resistors 4204 and 4205; and common mode circuit 4206 (which is used for a differential amplifier implementation of operational amplifier 4203). Differential current-to-voltage converter 4201 converts two current inputs, IBL+ and IBL−, into differential output voltages, VO+ and VO−, where the output voltages are proportional to the resistance of variable resistors 4204 and 4205. Input currents IBL+ and IBL− optionally are currents representing a positive weight and a negative weight. For example, IBL+ can be a current, Iw+ from a single cell or a bitline current that is the sum of currents from a plurality of w+ cells coupled to the bit line, and IBL− can be a current, Iw−, from a single cell or a bit line current that is the sum of currents from a plurality of w− cells coupled to the bit line. Such positive weights and negative weights can be used in a neural network to present a weight (W=W+−W−). In another example, the two input currents, IBL+ and IBL−, can represent a cell current (in which case, it is used to verify the cell current target in weight tuning, meaning program or erase cell to a target current) or bitline current from the array and a reference current.

[0159] Optionally, the bias current for operational amplifier 4203 and/or the common mode circuit 4206, can be set to a higher current level for a digital read than for an analog read.

[0160] Optionally the resistor 4204 and 4205 can be set to a different value for digital read versus for analog read. Optionally the resistor 4204 and 4205 can be set to a different value for when the converter 4201 is used for cell verify in a weight tuning operation (such as program or erase memory cell to a target current). FIG. 42B depicts differential successive-approximation register (SAR) analog-to-digital converter (ADC) 4202, which can read analog data from analog arrays 3601, 3701, and 4001 using a first set of voltages and to read digital data from digital arrays 3604, 3704, 4002, and 4003 or using a second set of voltages in VMM systems 3600, 3700, 4000, respectively.

[0161] Differential successive approximation register analog-to-digital converter 4202 converts an analog input or differential analog input into a digital output using a binary search through all possible quantization levels to identify the appropriate digital output.

[0162] Differential successive approximation register analog-to-digital converter 4202 comprises binary capacitive digital-to-analog converter (CDAC) 4207, binary CDAC 4208 (complementary to CDAC 4207), comparator 4209, and SAR logic and registers 4210.

[0163] Differential successive approximation register analog-to-digital converter (SAR ADC) 4202 receives a differential voltage inputs, Vinp and Vinn, which are for example provided by the differential current-to-voltage converter 4201. SAR logic and registers 4210 cycle through all possible digital bit combinations, which in turn control switches in CDAC 4207 and 4208 to couple voltage sources to capacitors. When the output of comparator 4209 flips, then the digital bit combination in SAR logic and registers 4210 is output as Digital Outputs. Optionally, SAR logic and registers 4210 generates an additional 1-bit digital output, DMAJ, in Digital Outputs which is a “1” if a majority of the bits in the digital value are a “1”, and a “0” if a majority of the bits in the corresponding digital value are not “1.”

[0164] Optionally, resistors 4204 and 4205 can be set to different resistance values for a digital read operation than for an analog read operation.

[0165] It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed therebetween) and “indirectly on” (intermediate materials, elements or space disposed therebetween). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed therebetween) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.