Phase locked loop arrangement, transmitter and receiver and method for adjusting the phase between oscillator signals

Abstract

A phase locked loop arrangement (1) beamforming comprises two or more phase locked loops. The loops include a phase comparator (21, 22) and an adjustable charge pump arrangement (31, 32) having a loop filter (51, 52) and charge pump current source (41, 42) with an adjustment input (ϕ.sub.adj) connected to the loop filter (51, 52) to inject an adjustable charge pump current into the loop filter. A constant current source (71, 72) is configured to inject a first predetermined charge current into the loop filter (51, 52). The adjustable charge pump arrangements (31, 32) are connected to the respective phase comparators (21, 22) to provide a voltage control signal (vctrl) to an oscillator (61, 62) of the respective phase adjustable phase locked loop (11, 12) in response to the respective control signal (up, down) and to generate a phase deviation between the first and one of the at least one second oscillator signals (f.sub.osc1, f.sub.osc2) based on an adjustment signal applied to the adjustment input (ϕ.sub.adj).

Claims

1. A phase locked loop arrangement for a beamforming system, comprising: a plurality of phase-adjustable phase locked loops, each configured to provide a respective oscillator signal and each comprising: a frequency divider to provide a frequency divided signal based on the oscillator signal; a phase comparator configured to output a respective control signal in response to a detection of a phase deviation between a common reference signal and the frequency divided signal; an adjustable charge pump arrangement having a loop filter, and a charge pump with an adjustment input, wherein the charge pump is connected to the loop filter to inject an adjustable charge pump current into the loop filter; and a constant current source configured to inject a first predetermined charge current into the loop filter; wherein the adjustable charge pump arrangement is connected to the phase comparator to provide a voltage control signal to an oscillator of the phase-adjustable phase locked loop in response to the control signal and to generate a phase deviation between the oscillator signal of the phase-adjustable phase locked loop and an oscillator signal of at least one other phase-adjustable phase locked loop of the plurality of phase-adjustable phase locked loops, based on the charge pump comprising a current-mirror circuit that adjusts the adjustable charge pump current output by the charge pump into the loop filter in dependence on the value of an adjustment signal applied to the adjustment input; and wherein the current-mirror circuit comprises a reference current side configured to receive a fixed reference current and generate an adjustable reference current responsive to the value of the adjustment signal, the adjustable reference current mirrored to an output side of the current-mirror circuit and output as the adjustable charge pump current.

2. The phase locked loop arrangement according to claim 1, wherein the loop filter comprises a capacitor configured to output the voltage control signal based on an amount of charge accumulated on the capacitor.

3. The phase locked loop arrangement according to claim 1, wherein the reference current side comprises at least two selectively switchable current paths, and wherein the value of the adjustment signal determines which one or ones of the at least two selectively switchable current paths are enabled, which in turn adjusts the adjustable charge pump current output by the charge pump.

4. The phase locked loop arrangement according to claim 1, wherein the current mirror has a non-linearly adjustable transfer ratio between its input side and its output side.

5. The phase locked loop arrangement according to claim 1, wherein the reference current side comprises a first transistor and at least one second transistor arranged in parallel to the first transistor, both transistors selectively switchable responsive to the value of the adjustment signal, to conduct a programmable portion of the fixed reference current, wherein the programmable portion of the fixed reference current controls adjustment of the adjustable charge pump current output by the charge pump.

6. The phase locked loop arrangement according to claim 5, wherein a transistor length and/or transistor width of the at least one second transistor is 2 times a transistor length and/or transistor width of the first transistor.

7. The phase locked loop arrangement according to claim 1, wherein the charge pump comprises a source path to provide a charge current and a drain path to provide a discharge current, and wherein the charge pump is configured to provide the charge current as the adjustable charge pump current.

8. The phase locked loop arrangement according to claim 1, wherein the constant current source comprises a further current mirror circuit, and wherein a same biasing transistor biases the current mirror circuit comprising the charge pump and the further current mirror circuit.

9. The phase locked loop arrangement according to claim 1, wherein the frequency divider is adjustable and operatively arranged between an output of the oscillator and an input of the phase comparator to provide the frequency divided signal to the phase comparator based on the oscillator signal and a frequency control word.

10. The phase locked loop arrangement according to claim 1, further comprising a reference signal generator configured to provide the common reference signal to each of the phase-adjustable phase locked loops.

11. A transmitter arrangement, comprising: a phase locked loop arrangement according to claim 1; and an antenna array having a plurality of antenna elements, wherein each of the antenna elements is in operative connection to a respective one of the phase-adjustable phase locked loops to receive an individual signal for transmission derived from the respective oscillator signal thereof.

12. A receiver arrangement, comprising: a phase locked loop arrangement according to claim 1; and an antenna array having a plurality of antenna elements, wherein each of the antenna elements is coupled to a respective one of the phase-adjustable phase locked loops to downconvert a received signal with the respective oscillator signal thereof.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Further aspect, embodiments and advantages of the present disclosure will become apparent in the following detailed description accompanying the following drawings, in which

(2) FIG. 1 illustrates a first embodiment of a phase locked loop arrangement for a beamforming system;

(3) FIG. 2 shows a second detailed embodiment of a phase locked loop arrangement for a beamforming system;

(4) FIG. 3 illustrates the charge-phase relationship in accordance with aspects of the present disclosure;

(5) FIG. 4 illustrates a transceiver in accordance with aspects of the present disclosure;

(6) FIG. 5 shows an example of a transceiver element including transmitter and receiver in accordance with some aspect of the present disclosure;

(7) FIG. 6 illustrates an embodiment of a phase comparator;

(8) FIG. 7 shows a visual representation between the injected charge current and the corresponding phase shift;

(9) FIG. 8 illustrates an embodiment for a linearization using a current mirror in a charge pump;

(10) FIG. 9 illustrates more detailed view of an embodiment of a charge pump arrangement according to the present disclosure;

(11) FIG. 10 shows another example of a charge pump arrangement according to the present disclosure;

(12) FIG. 11 illustrates a method to adjust the phase between oscillator signals in accordance with the disclosure.

ABBREVIATIONS

(13) OFDM Orthogonal Frequency Division Multiplex

(14) PLL Phase locked loop

(15) LO Local oscillator

(16) VCO Voltage Controlled Oscillator

(17) DIV Divider

(18) LPF Low Pass Filter

(19) PFD Phase Frequency Detector

(20) DC Direct Current

(21) W Width of a transistor

(22) L Length of a transistor

(23) LSB Least Significant Bit

(24) MSB Most significant Bit

DETAILED DESCRIPTION

(25) In this regard the term “reference frequency” shall refer to a reference signal having a predetermined frequency. As the reference signal is commonly applied to all phase locked loops (except otherwise noted), the frequency of said signal applied to the loops shall be the same. The term “Common” in this regard means that in operation each phase comparator is applied with the same reference signal. Due to different reference signal propagation, the reference signal may have different phases at the respective input terminals of the phase locked loops. By choosing appropriate designs or other measures these phase deviations can be compensated. Alternatively, one may make use of those differences as the shift in between the respective loops is known and depends inter alia from the different length of the signal lines. The term “frequency” or “phase adjustment signal” shall include any kind of analogue adjustment signal, but also any digital frequency or phase adjustment word. Such words include parallel and serial signals. A digital word can be applied directly, wherein the respective bit values are applied directly to switches and the like, but also be converted to analogue voltage or current signals using digital-analogue-converters and the like. The terms “phase shift” and “phase skew” shall mean the same for the purpose of this disclosure. The term transistors shall include field-effect transistors and/or bipolar transistors except where otherwise stated. The terms “phase comparator”, “phase detector” and “phase-frequency” detector shall refer to the same element except otherwise stated.

(26) It is foreseeable that the next generation of cellular systems and wireless communication will use frequencies in the higher GHz frequency range, that is above 15 GHz and up to 60 GHz. Outdoors in rural and urban areas the signal echoes will have longer delays than indoors, so longer prefixes resulting in closer sub-spacing in the proposed underlying OFDM modulation is required compared to indoor only systems. Consequently, phase noise and other requirement concerning the signal quality are increased to achieve a reliable data transmission enabling high data throughput. Furthermore, the signal attenuation at these frequencies will be high in a cellular system, which can be mitigated using beamforming systems. Such beamforming systems include a large number of antenna elements in an array, being able to transmit or receive in a dedicated direction. To control the beam or receiving direction, a dedicated phase shift of the signal must be applied to each respective antenna element. In a key implementation it has been proposed to establish such phase shift in the local oscillator signal provided by a PLL coupled to the respective antenna element.

(27) In addition, the phase locked loop comprises a feedback path, normally including a programmable frequency divider circuit dividing the output oscillator signal by a pre-determined ratio and feeding the frequency-divided signal back to the phase comparator. As a result, the phase comparator using a common reference signal, the output signals of the PLLs will lock in different well defined phase relations. Regardless of scheme used for the frequency division, integer-N or fractional-N, there is a need to control the phase of the output signal of the different PLLs.

(28) A solution for generating the local oscillator signals with some control for its phase is for example illustrated in A. Axholt, H. Sjöland, “A PLL based 12 GHz LO generator with digital phase control in 90 nm CMOS”, Analog Integrated Circuits and Signal Processing, Vol. 67, No. 3, pp. 309-318, 2011. Another example is shown in A. Axholt and H. Sjöland, “A 60 GHz Receiver Front-End with PLL based Phase Controlled LO Generation for Phased-Arrays”, IEEE Proc. Asia Pacific Microwave Conference, APMC 2011, APMC 2011, December 2011, Melbourne, Australia. In both cases, an additional adjustable current source injects a current into the loop filters of each local PLL, which will produce a phase shift of the output signal. In equilibrium, the loop becomes frequency and phase locked and will strive to return in case of deviations, so the loop reacts to the “disturbance” caused by the injected current by a proportional phase-skew between the reference signal and the feedback signal at the input of the phase detector.

(29) In the examples shown in prior art, a phase-skew of one output cycle-, that is 360° phase at the frequency of the output signal-, between the reference signal and the feedback signal corresponds to a charge-pump charge pulse of I.sub.CHP*(1/f.sub.osc). The current injected by the current source that corresponds to this charge pulse is transferred over (or “smeared out” over) the whole signal period of the reference signal f.sub.ref. As a result, the ratio between the charge pulse current and the current injected by the current source becomes dependant from the divider ratio N within the feedback path of the phase lock loop:
I.sub.CHP*(1/f.sub.OSC)=I.sub.DC*(1/f.sub.REF)
I.sub.DC=I.sub.CHP*(f.sub.REF/f.sub.OSC)=I.sub.CHP/N

(30) For a 1-degree phase change, the required injected current becomes
I.sub.DC=I.sub.CHP/(N*360)  (1)

(31) As the output frequency of the oscillator signal is in the range of 20 GHz, while the reference frequency is about 300 MHz, one can assume under normal circumstances a divider ratio N between 50 and 100. If one assumes a divider ratio of N=70, the injected I.sub.DC current charge for a 1-degree phase skew becomes about 25000 times smaller than the charge pump current. As the accuracy of current ratios is typically limited by the matching properties, designs of current sources with good matching at such ratios are needed. It is difficult to realize current sources with this enormous ratio while maintaining good matching accuracy, for instance the technique of using unit current sources of equal design would require 25000 units for each current source. Hence, the solutions as stated above will call for a trade-off resulting in either phase control with bad accuracy or large chip area.

(32) The solution proposes to control the phases of a plurality of oscillator output signal of phase locked loops in a phase locked loop arrangement by instead changing the charge pump pulse current. By changing the charge pump pulse current, the respective phase locked loop will compensate by changing the pulse duration, so that the total pulse charge remains constant. For this purpose a further small dedicated and constant DC current is injected which will set the average current pulse that the charge pump must provide in the steady state.

(33) FIG. 3 illustrates the relationship between the charge current injected into the loop filter and the phase skew as an output thereof. In the area of the zero phase region, marked by the circle, the transfer function is highly non-linear due to timing errors when producing ultra-short pulses in the phase comparator. Particular for small phase deviation, the phase comparator may not provide a well-defined control signal resulting either in noise or in non-linearities when switching on or off the respective charge pumps. Injecting a small DC current has the additional benefit of shifting the transfer function from the zero phase region.

(34) As a result and as illustrated in FIG. 7, the charge pump produces pulses (straight line) of a certain length M to remain in equilibrium. The charge pump current is set to I.sub.CHP. By shifting the transfer function as shown in FIG. 3, one of the pumps of the charge pump has to be used in the state when the PLL is locked, preferably the least noisy. The length M is chosen to be a couple of periods of the oscillators output signals, i.e. long enough that the dynamics of any variable divider in the feedback path fits and that still only one of the pumps need to be in use when the PLL is locked. In this way the transfer function of the phase comparator and charge pump is kept linear.

(35) In the steady state situation, in which the charge pump current is set to a certain value to compensate for the injected DC current, the average charge transfer, the area below the straight or dotted line in FIG. 7, given by the pulse length from the phase comparator must correspond to the injected DC current according to the following equation:

(36) $\begin{array}{cc}M.Math.\frac{1}{f_{\mathrm{VCO}}}.Math.I_{\mathrm{CHP}}=\left(I_{\mathrm{CHP}}-\frac{I_{\mathrm{CHP}}}{X}\right).Math.\left(M+\frac{\mathrm{\Delta \Phi }}{360}\right).Math.\frac{1}{f_{\mathrm{VCO}}}& \left(2\right)\end{array}$

(37) M is the pulse length and set in periods of the output signal of the oscillator of the phase locked loop, the phase skew ΔΦ is the phase deviation of the output VCO signal introduced by the change in charge pump current from I.sub.CHP to I.sub.CHP*(1−(1/X)). Equation (2) can be re-written into

(38) $\begin{array}{cc}\frac{I_{\mathrm{CHP}}}{X}\left(M+\frac{\mathrm{\Delta \Phi }}{360}\right)=I_{\mathrm{CHP}}.Math.\frac{\mathrm{\Delta \Phi }}{360}X=360.Math.\frac{M}{\mathrm{\Delta \Phi }}+1& \left(3\right)\end{array}$

(39) As 1/X corresponds to a portion of the charge current being adjusted, the charge pump current I.sub.CHP required to produce a phase shift of ΔΦ becomes:

(40) $\frac{I_{\mathrm{CHP}}}{X}=I_{\mathrm{CHP}}.Math.\frac{\frac{\mathrm{\Delta \Phi }}{360}}{M+\frac{\mathrm{\Delta \Phi }}{360}}$

(41) and for a 1 degree phase shift this simplifies to

(42) $\begin{array}{cc}\frac{I_{\mathrm{CHP}}}{X}=\frac{I_{\mathrm{CHP}}}{M*360+1}& \left(4\right)\end{array}$

(43) As the product of pulse length and charge pump current stays the same in steady state, one can obtain the necessary charge pump current I.sub.CHP−I.sub.CHP/X to obtain a phase skew between the reference signal f.sub.ref and the feedback signal f.sub.feedback corresponding to a phase deviation ΔΦ of the output VCO signal, given by

(44) $\begin{array}{cc}{I}_{\mathrm{ref},\mathrm{\Delta \Phi }}=I_{\mathrm{CHP}}-\frac{I_{\mathrm{CHP}}}{X}=I_{\mathrm{CHP}}.Math.\left(\frac{M}{M+\frac{\mathrm{\Delta \Phi }}{360}}\right)& \left(5\right)\end{array}$

(45) Using equation (4) and under the assumption of a nominal pulse length of M=4, equal to 4 periods of the oscillator's output signal the ratio between I.sub.CHP and I.sub.CHP/X becomes about 1440. As a result phase control using a current injection by the charge pump requires a different ratio compared to the ratio of equation (1). Such current ratio is simpler to implement with high accuracy by proper design of the current sources.

(46) FIG. 1 illustrates an embodiment of a phase locked loop arrangement 1 in accordance with some aspects of the present disclosure. The arrangement comprises a plurality of phase locked loops 11, 12, 13 to 1M. Although 4 phase locked loops are shown herein, the number of phase locked loops is not restricted to this number. As each phase locked loop supports an antenna element of an antenna array the number of phase locked loops is in relation to the number of antenna elements. Each phase locked loop 11 to 1M is connected to a reference signal generator 15 providing a common reference signal f.sub.ref to all phase locked loops. Further, each of the phase locked loops provides a respective oscillator signal f.sub.osc-1 to f.sub.osc-M, having a dedicated frequency which is adjusted and selected by a frequency control word f.sub.adj applied to the respective phase locked loop. In case the frequency control word f.sub.adj of two phase locked loops is the same, the respective output signal f.sub.osc will have the same frequency due to the common reference signal f.sub.ref applied thereto. However, each phase locked loop 11 to 1M also comprises an input for a phase adjustment word ϕ.sub.adj. Each phase locked loop is configured to set the phase of its output signal f.sub.osc relative to a nominal reference phase. In case of the above example, wherein the frequency of respective output signals f.sub.osc of two or more phase locked loops are the same, the phase adjustment enables each phase locked loop to skew its phase. As a result, any phase deviation can be set between two or more output signals f.sub.osc.

(47) FIG. 2 shows a more detailed view of an arrangement 1 having two phase locked loops 11 and 12. Each phase locked loop 11, 12 is implemented in the same way, so only one of the phase locked loops will be described in greater detail. Phase locked loop 11 comprises a forward path having a phase-frequency comparator 21, —short “phase comparator”,— a charge pump arrangement 31 connected downstream phase comparator 21 and an oscillator 61 connected to charge pump arrangement 31. The charge pump arrangement 31 provides and adjustable voltage control signal v.sub.ctrl. Oscillator 61 receives the voltage control signal v.sub.ctrl from charge pump arrangement 31 to adjust its output frequency and/or phase.

(48) The output signal is also applied to a feedback path having an adjustable frequency divider 91 and coupled between oscillator 61 and a feedback input of phase comparator 21. The oscillator 61 provides the output signal f.sub.osc1 with a frequency of several GHz, for example between 10 and 30 GHz of phase locked loop 11. Those frequencies can be processed by the divider 91. Higher frequencies can be achieved by a multiplication unit (not shown) arranged downstream to the oscillator. The frequency divider 91 is implemented as an adjustable integral or fractional frequency divider having an adjustment input, at which the divider ratio can be set using a respective frequency control word. With the adjustable divider ratio, phase locked loop 11 can achieve different desired output frequencies in a given range.

(49) Phase comparator 21 in the forward path compares the phase of the frequency divided signal f.sub.div from the feedback path with the phase from the common reference signal f.sub.ref and output a control signal up, down corresponding to the phase difference or phase deviation. An embodiment of a phase comparator is illustrated with respect to FIG. 6. The phase comparator 21 comprises two positive-edge triggered D-Flip-flops FF1 and FF2, wherein their respective signal inputs D are put to HIGH-state. At the clock inputs the reference signal f.sub.ref and the feedback signal f.sub.div are applied. Data output Q of flip-flop FF1 is connected to inverter I1 and to an input of a logic AND-gate L1. Output of inverter I1 is connected to a gate of switch 811 of a switch 81 of the charge pump arrangement. Output Q of flip-flop FF2 is connected to the other input of logic gate L1 and to gate of switch 812 of the charge pump arrangement. Both switches 811, 812 are coupled to a common output. Output of logic Gate L1 is coupled via delay element D to the reset inputs CLR of the two flip-flops. When both outputs Q are high, gate L1 will disable the FF1 and FF2 after some delay, causing a reset pulse. Without delay element D, the disablement of flip-flops FF1 and FF2 may cause the outputs Q to a high impedance state, stopping the phase comparator from working by producing neither positive nor negative current pulses. In case of phase or frequency deviation between the reference signals and the feedback signal, one of the flip-flops FF1, FF2 produce a respective longer control signal up or down.

(50) Said control signal is applied to the charge pump arrangement 31 and more particular to switch 81 of arrangement 31. Charge pump arrangement 31 comprise a charge pump 41 with two current sources 411 and 411a and a switching circuitry 81 coupled to a loop filter 51. Loop filter 51 comprises a capacitor 510 accumulating charge provided by the charge pumps 41. Loop filter 51 may also comprise further elements Z, like resistors and capacitors to improve loop phase margin and better supress reference frequency modulation of the oscillator.

(51) In case of a phase deviation between f.sub.div and f.sub.ref, primarily one of the switches 81 is operated coupling one of the charge pump current sources to the loop filter. The charge pump applies a dedicated current I.sub.CHP to the loop filter charging or discharging its capacitors, thereby changing the control signal V.sub.crtl to the oscillator 61. In accordance with the disclosure, charge pump arrangement 31 also comprises a constant current source 71 injecting a constant current into loop filter 51. In this example current source is connected between loop filter and ground, thus effectively discharging the capacitors of loop filter 51. In steady state, to compensate this current, phase comparator 21 activates switch 81 for current source 411a to inject a corresponding average charge pump current into the loop filter. The pulse length of said charge pump current pulse is such that the resulting charge equals the charge injection by DC current source 71. As a result, the charge pump injecting pulses of a certain length corresponds to a proportional phase difference at the phase comparator input, corresponding to an output signal phase skew. Furthermore as an additional beneficial side effect, the transfer function is shifted from the nonlinear zero-phase region to a linear region as illustrated in FIG. 3.

(52) Optionally, charge pump arrangement 31 comprises a reference current source 410 connected to the charge pump current source 411 and 411a to provide a reference current from which the charge pump current is derived. To control the skew of the phase of the output signal f.sub.osc, arrangement 31 comprises a phase adjustment input for a phase adjustment word ϕ.sub.adj and the charge pump current I.sub.CHP is adjustable in response thereto. Particular, the reference current source is implemented as an adjustable current source and the phase adjustment word applied to the reference current source accordingly. The adjustment is made such that it compensates the non-linear relation between the phase shift Δϕ and the charge pump current I.sub.ref, Δϕ shown in equation (5).

(53) For example, such adjustment can be achieved by removing a portion of the reference current from which the charge pump current is derived. As the relationship between I.sub.ref,ΔΦ and Δϕ is nonlinear, the change of a desired phase shift will also become non-linear. For example to achieve a phase shift of 2*Δϕ, one has to subtract a current I.sub.ref,2ΔΦ≠2*I.sub.ref,ΔΦ in accordance with equation (5). To obtain a linear phase control, the present disclosure proposes to add or subtract some of the charge pump current I.sub.CHP by using transistors. One way to achieve this is using a specifically designed current mirror, wherein the reference current side is adjusted and the adjusted reference current is mirrored into the output side of the current mirror. Such current mirror and its implementation principle are illustrated in FIG. 8.

(54) FIG. 8 shows a portion of a current mirror, namely the mirror side having a plurality of tapping transistors switchable arranged in parallel between terminals 418 and 419, respectively. The transistors RCT1 to RCTN are diode connected, i.e. their gates are coupled to their respective drains. Transistor RM is the mirror transistor and also connected with its gate to its drain, but also to the output transistor (not shown) of the current mirror.

(55) As the output current of a current mirror is substantially depending on current through the mirror transistor and the geometry ratio between the respective mirror and output transistors, the output current can be adjusted by varying the mirror transistor current, I.sub.ref. By switching in tapping transistors, current is subtracted from I.sub.ref making it less than I.sub.total. This gives an equation (6) similar to equation (5) as above, wherein the two nonlinearities cancel each other out and we get a linear relation between the amount of “tapped-in” transistors and phase of the output signal. Thus, we are introducing a non-linearity to cancel the non-linearity described above.

(56) $\begin{array}{cc}{I}_{\mathrm{ref}}=I_{\mathrm{total}}.Math.\left(\frac{W_{\mathrm{ref}}}{W_{\mathrm{tot}}}\right)=I_{\mathrm{total}}.Math.\left(\frac{W_{\mathrm{ref}}}{W_{\mathrm{ref}}+W_{\mathrm{tap}}}\right)& \left(6\right)\end{array}$

(57) The ratio between W.sub.ref and W.sub.tot in equation (6) is the measure on how much of the biasing current I.sub.total in FIG. 8 reaches the transistor RM that biases the UP-output-transistor of the charge pump. If W.sub.tot equals W.sub.ref, i.e. W.sub.tap=0, no tapping transistors are switched in, then I.sub.ref equals I.sub.total. In case a different phase shift is desired, one or more of the transistors RCT1 to RCT2 are switched into the current path in accordance with the phase adjustment signal (LSB, LSB+1). Under the assumption that all transistors comprise the same length and a width as stated in the Figure, another way of deriving equation (6) is to regard I.sub.total as the input current to a current mirror with an effective transistor width of W.sub.tot=W.sub.ref+W.sub.tap. If more tapping transistors RCT are tapped in, the overall width changes to W.sub.tot=W.sub.ref+X*W.sub.tap,LSB, wherein x is the weighted amount of transistors tapped-in. Such additional tapping results in a non-linear behaviour, The more tapping transistors with its weighted width W are tapped-in the less impact on the current I.sub.ref occurs, but the “length-impact”, i.e. change on the charge pump pulse length will be linear.

(58) If the transistors width W.sub.ref of Transistor RM in equation (6) has a specific ratio to M in equation (5), then one has to design the width W.sub.tap of the tapping transistors with the same ratio to (ΔΦ/360) to a certain phase of the output signal. Setting W.sub.ref to M*k and W.sub.tap to Δϕ*k/360 provides a linear control of the phase with the phase being proportional to a binary control word for the tapping transistors. The factor k is a design factor of the transistors.

(59) Turning now to FIG. 9, a more detailed view of a charge pump arrangement in accordance with the present disclosure is presented. The charge pump current source 411a coupled to switch 81 is realized as an output transistor of a current mirror, whose input side is adjustable to provide a varying reference current I.sub.ref. The input side corresponds to current adjustment circuit 410. It comprises a plurality of binary weighted tapping transistors RCT1 to RCTn arranged in parallel. In this example the transistors are implemented as p-channel field-effect transistors. Each of the tapping transistors RCT1 to RCTn is connected via a respective switch to node 419. The respective switches are controlled by a phase adjustment word ϕ.sub.adj. The tapping transistor RCT1 to RCTn each comprise a certain length L and width W. While length L of the tapping transistors are the same, their respective width can be binary weighted as well. In case of binary weighting, the tapping transistor RCT1 corresponding to the least significant bit has the smallest width, with doubling the width W with each tapping transistor. The tapping transistor of bit n comprises a width W corresponding to 2.sup.n*W.sub.tab,LSB, where n=0 is the lease significant bit LSB. Mirror transistor RM1 comprises the same length L and a width W.sub.ref setting the ratio of the output current to the reference current of the current mirror, W.sub.out/W.sub.ref. The current I.sub.total flowing through the mirror transistor RM1 and the tapping transistors is set by the bias transistor TB1, which is coupled with its gate to mirror transistor RM2. Said transistor RM2 also provides the bias signal V.sub.biasN for charge pump current source transistor 411. Under the assumption that the phase adjustment range shall cover 360° and binary weighted tapping transistors, the resolution is limited by the number of tapping transistors to 360/2.sup.N, wherein N is the number of tapping transistors. For N=8 the resolution is limited to about 1.4°.

(60) In addition, the DC current source 71 also comprises a plurality of switchable current paths to inject a constant but adjusted DC current based on the bias signal V.sub.biasN. The discharge current is controlled by a digital DC.sub.leak control word. Current source 71 comprises a plurality of n-channel field effect transistors TCS connected as switchable current sources arranged in parallel. A first switch is coupling a gate of each transistor to the bias signal V.sub.biasN. A second switch is arranged between the gate and the source terminal of the respective transistor and coupled via an inverter to an adjustment input to be controlled in response to the DC.sub.leak control word. The plurality of transistors TCS can be binary weighted in a similar manner as the tapping transistors. Their respective length and width may be of course different from the tapping transistors.

(61) The benefit of using the current mirror transistor RM2 for biasing both charge pumps 411, 411a and the DC current source 71 lies in the matching behaviour. Any change in the output current of the charge pump due to process or temperature variations will result in a change in the injection current I.sub.DC,inject by the same ratio phase of the output signal will be stable versus variations

(62) FIG. 10 shows a similar arrangement for a charge pump arrangement. However, the amount of tapping transistors is reduced due to the use of a ΔΣ modulator to generate and apply the phase adjustment word. The reference source 410 comprises in this example three tapping transistors RCT1 to RCT3 having the same length and a binary weighted width. In FIG. 10, the switchable diode-connected transistors are sized to correspond to different phases according to the table.

(63) TABLE-US-00001 Word Phase ° 000 0 001 45 010 90 011 135 100 180 101 225 110 270 111 315

(64) The final phase of the PLL output signal is given by the average of a ΔΣ phase adjustment signal. For example, the sequence 000, 000, 010, 001, 000, 000, 001, 001, 000, will give an average phase of 22.5°. To increase accuracy the switching between different phase control values are done between the charge-pump pulses when the charge pump current to the loop filter is off.

(65) FIG. 4 illustrates an application of the phase locked loop arrangement in a transceiver device. The term transceiver shall include not only a device able to transmit and receive signals, but also contain a pure transmitter or pure receiver. The transceiver herein is implemented as a beamforming system and comprises an antenna array 8 with a plurality of antenna elements 8A to 8Z. Each of the antenna elements may located at a different position in space and also point to a different direction. The antenna array may extend over a large area and several elements 8A to 8Z are separated and spaced apart from each other. For example an antenna array may cover an area from a few square centimetres up to several square meters and comprise up to hundreds of individual antenna elements located in that area. In one aspect, the antenna elements are in a fixed position with respect to each other. Each antenna element 8A to 8Z of the antenna array 8 is coupled to a respective RF front-end 9A to 9Z. The RF front-ends are configured to transmit signals to the respective elements, and also receive signals from it. Similar antenna arrays can be used in connection with pure transmitter or pure receiver devices. In accordance with aspects of the present disclosure, signals transmitted from the RF front-ends comprise—despite being modulated-different dedicated phase skews. These phase skews result in control of the direction of the signals being transmitted over the antenna array 8. This can be used to increase the signal strength in a receiver for demodulation. Likewise, any signal received via the antenna elements 9A to 9Z is processed in the respective RF front-end using phase shifted signals. Signals from a specific direction are constructively amplified or combined, while signal form a different direction not corresponding to the respective phase shifted signal are suppressed. Such processing is further illustrated in FIG. 5 showing an exemplary embodiment of an individual RF front-end 9Z.

(66) Each of the RF front-ends is divided into a transmitter path for a transmission signal f.sub.trans and a reception path for processing a received signal frec. Each path comprises an up-mixer 93Z and down-mixer 94Z, respectively. The mixers are using a local oscillator signal foscT and foscR provided by a phase locked loop 11Z. In the transmission path, mixer 93Z is used to frequency up-convert or to modulate the data to be transmitted to the transmission signal ftrans. In this regard, the mixer units 93Z can be a classical mixer, a modulator of some sort, i.e. a quadrature modulator, any combination thereof or any other device using the oscillator signal f.sub.oscT to generate the transmission signal ftrans therefrom. The transmission signal is then amplified using amplifier 91Z and fed to antenna element 8Z connected thereto. Likewise a received signal frec is amplified using a low-noise amplification stage 92Z and then converted to a lower frequency using the oscillator signal foscR. The phase locked loop 11Z providing the oscillator signals is part of the phase locked loop arrangement as discussed previously. Accordingly, it comprises a frequency and phase adjustment input to adjust the frequency and phase of the oscillator signals f.sub.oscT and f.sub.oscR. The phase locked loop 11Z may in some cases, like in a frequency division duplex (FDD) system, consist of two separate PLLs generating different frequencies for f.sub.oscT and f.sub.oscR.

(67) FIG. 11 shows a method as it is for example used in an embodiment according to the previous figures. In the first steps S101 a common reference signal having a common reference frequency is generated. In steps S102 and S103 the first and at least one second oscillator signals are generated. They may have the same nominal frequency. The oscillator signals are then frequency divided in steps S102a and S103a, respectively. For phase and frequency locking the method continues with step S104, wherein respective control signals responsive to a phase deviation between the common reference signal and each of the first oscillator signal and the at least one second oscillator signal are generated. From these control signals respective charge current pulses are generated in step S105, which are transformed to control signals to change frequency and/or phase of the respective oscillator signals. The charge current pulses comprises in accordance with the disclosure a specified length responsive to a respective one of the control signals to control the frequency of the respective first and at least one second oscillator signal and a charge current. In step S106 a constant current is injected into the loop filter. This creates a phase skew of the output signal. In step S107 the phase skew is controlled by adjusting the current pulse amplitudes.

(68) The present disclosure provides a phase locked loop arrangement with a plurality of phase locked loops with individually selectable phase values of its output signals. This selectable phase skew between two oscillator signals or between an oscillator signal and a nominal phase is achieved by injecting a constant current into the loop filter, and then controlling the charge pump current used for injecting charge pulses into the loop filter. By choosing a nonlinear control of the charge pump current the non-linear relation between the phase skew and the charge pump current is compensated resulting in an overall linear control of the phase skew. As a consequence the ratio between the phase control current and the total charge pump current becomes larger compared to tuning the injected constant current, which enables not only a good matching and high accuracy, but also reduces the chip area required for the adjustable current sources.