LOW-COST PASSIVATED CONTACT FULL-BACK ELECTRODE SOLAR CELL AND PREPARATION METHOD THEREOF

Abstract

A preparation method of a low-cost passivated contact full-back electrode solar cell includes: performing alkali polishing on a Si wafer; performing RCA cleaning and HF cleaning; growing a tunnel SiO.sub.x film layer, an in-situ doped amorphous Si film layer, and a texturing mask layer on the back of the Si wafer; performing annealing activation on the amorphous Si film layer to form a polycrystalline Si film layer; etching the texturing mask layer; performing double-sided texturing on the Si wafer; performing HF cleaning to remove the texturing mask layer; depositing an AlO.sub.x film on the front and back of the Si wafer; depositing a SiN.sub.x passivation film on the front and back of the Si wafer; ablating a part of the AlO.sub.x film and a part of the SiN.sub.x passivation film on the back of the Si wafer; and performing screen-printing and sintering on the back of the Si wafer.

Claims

1. A preparation method for a low-cost passivated contact full-back electrode solar cell, comprising following sequential steps: S1: configuring a P-type monocrystalline silicon (Si) wafer as a Si substrate and performing an alkali polishing on the Si substrate; S2: after performing the alkali polishing, performing a Radio Cooperation of America (RCA) cleaning and a hydrogen fluoride (HF) cleaning; S3: growing a tunnel silicon oxide (SiO.sub.x) film layer, an in-situ doped amorphous Si film layer, and a texturing mask layer on a back of the P-type monocrystalline Si wafer; S4: performing an annealing activation on the in-situ doped amorphous Si film layer, so that the in-situ doped amorphous Si film layer is transformed into a polycrystalline Si film layer; S5: etching the texturing mask layer on the back of the P-type monocrystalline Si wafer by a laser; S6: performing a double-sided texturing on the P-type monocrystalline Si wafer; S7: after performing the double-sided texturing, performing the HF cleaning to completely remove the texturing mask layer; S8: simultaneously depositing an aluminum oxide (AlO.sub.x) film on a front and the back of the P-type monocrystalline Si wafer; S9: depositing a silicon nitride (SiN.sub.x) passivation film or a silicon nitride/silicon oxynitride (SiN.sub.x/SiON.sub.x) laminated passivation film on the front and the back of the P-type monocrystalline Si wafer; S10: ablating, by the laser, a part of the AlO.sub.x film and a part of the SiN.sub.x passivation film or the SiN.sub.x/SiON.sub.x laminated passivation film on the back of the P-type monocrystalline Si wafer; and S11: performing a screen-printing and a sintering on the back of the P-type monocrystalline Si wafer, wherein a silver paste is used in a passivated contact area, and an aluminum paste is used in a backfield area.

2. The preparation method according to claim 1, wherein in step S1, the P-type monocrystalline Si wafer is configured as the Si substrate, wherein the P-type monocrystalline Si wafer has a resistivity of 0.5 ohm-cm to 5 ohm-cm and a thickness of 120 μm-200 μm; and the alkali polishing is performed on the Si substrate by a 15 wt %-30 wt % potassium hydroxide (KOH) solution at 75° C.-85° C.

3. The preparation method according to claim 1, wherein in step S3, a tubular or platelike plasma-enhanced chemical vapor deposition (PECVD) device configured for single-sided deposition is configured to perform a three-in-one multi-layer film deposition on the back of the P-type monocrystalline Si wafer to grow the tunnel SiO.sub.x film layer, the in-situ doped amorphous Si film layer, and the texturing mask layer; wherein a thickness of the tunnel SiO.sub.x film layer is less than 2 nm, the in-situ doped amorphous Si film layer is an in-situ phosphorus-doped film with a thickness of 50 nm-200 nm, and the texturing mask layer is made of SiON.sub.x, SiO.sub.x, or SiN.sub.x with a thickness of 50 nm-100 nm.

4. The preparation method according to claim 1, wherein in step S4, the annealing activation is performed on the in-situ doped amorphous Si film layer, so that the in-situ doped amorphous Si film layer is transformed into the polycrystalline Si film layer with a sheet resistance controlled at 50 ohm/sq-100 ohm/sq; wherein the annealing activation is performed by a tubular oxidation furnace; a process temperature is 700° C.-900° C., a time for the annealing activation is 1 h-2 h, and a doping concentration after activation is 1e.sup.18 cm.sup.−3-5e.sup.20 cm.sup.−3.

5. The preparation method according to claim 1, wherein in step S6, the double-sided texturing is performed on the P-type monocrystalline Si wafer using a KOH or tetramethylammonium hydroxide (TMAH) solution to form a light-trapping textured structure.

6. The preparation method according to claim 1, wherein in step S7, after performing the double-sided texturing, cleaning is performed by a 5 wt %-20 wt % HF solution to completely remove the texturing mask layer.

7. The preparation method according to claim 1, wherein in step S8, the AlO.sub.x film is simultaneously deposited on the front and the back of the P-type monocrystalline Si wafer by a tubular or platelike atomic layer deposition (ALD) device configured for double-sided deposition, wherein the AlO.sub.x film has a thickness of 2 nm-20 nm.

8. The preparation method according to claim 1, wherein in step S9, the SiN.sub.x passivation film or the SiN.sub.x/SiON.sub.x laminated passivation film is deposited on the front and the back of the P-type monocrystalline Si wafer by a tubular or platelike PECVD device, respectively, wherein the SiN.sub.x passivation film or the SiN.sub.x/SiON.sub.x laminated passivation film has a thickness of 50 nm-100 nm and a refractive index of 1.9-2.4.

9. The preparation method according to claim 1, wherein in step S11, a sintering temperature is controlled at 700° C.-900° C.

10. A low-cost passivated contact full-back electrode solar cell, prepared by the preparation method according to claim 1, comprising: the P-type monocrystalline Si wafer, a front passivation film layer located on the front of the P-type monocrystalline Si wafer, the polycrystalline Si film layer, an Al-back surface field (BSF) layer and a back passivation film layer, wherein the polycrystalline Si film layer, the Al-BSF layer and the back passivation film layer are located on the back of the P-type monocrystalline Si wafer, a first electrode located under the polycrystalline Si film layer, and a second electrode located under the Al-BSF layer.

11. The low-cost passivated contact full-back electrode solar cell according to claim 10, wherein in the preparation method, in step S1, the P-type monocrystalline Si wafer is configured as the Si substrate, wherein the P-type monocrystalline Si wafer has a resistivity of 0.5 ohm-cm to 5 ohm-cm and a thickness of 120 μm-200 μm; and the alkali polishing is performed on the Si substrate by a 15 wt %-30 wt % potassium hydroxide (KOH) solution at 75° C.-85° C.

12. The low-cost passivated contact full-back electrode solar cell according to claim 10, wherein in the preparation method, in step S3, a tubular or platelike plasma-enhanced chemical vapor deposition (PECVD) device configured for single-sided deposition is configured to perform a three-in-one multi-layer film deposition on the back of the P-type monocrystalline Si wafer to grow the tunnel SiO.sub.x film layer, the in-situ doped amorphous Si film layer, and the texturing mask layer; wherein a thickness of the tunnel SiO.sub.x film layer is less than 2 nm, the in-situ doped amorphous Si film layer is an in-situ phosphorus-doped film with a thickness of 50 nm-200 nm, and the texturing mask layer is made of SiON.sub.x, SiO.sub.x, or SiN.sub.x with a thickness of 50 nm-100 nm.

13. The low-cost passivated contact full-back electrode solar cell according to claim 10, wherein in the preparation method, in step S4, the annealing activation is performed on the in-situ doped amorphous Si film layer, so that the in-situ doped amorphous Si film layer is transformed into the polycrystalline Si film layer with a sheet resistance controlled at 50 ohm/sq-100 ohm/sq; wherein the annealing activation is performed by a tubular oxidation furnace; a process temperature is 700° C.-900° C., a time for the annealing activation is 1 h-2 h, and a doping concentration after activation is 1e.sup.18 cm.sup.−3-5e.sup.20 cm.sup.−3.

14. The low-cost passivated contact full-back electrode solar cell according to claim 10, wherein in the preparation method, in step S6, the double-sided texturing is performed on the P-type monocrystalline Si wafer using a KOH or tetramethylammonium hydroxide (TMAH) solution to form a light-trapping textured structure.

15. The low-cost passivated contact full-back electrode solar cell according to claim 10, wherein in the preparation method, in step S7, after performing the double-sided texturing, cleaning is performed by a 5 wt %-20 wt % HF solution to completely remove the texturing mask layer.

16. The low-cost passivated contact full-back electrode solar cell according to claim 10, wherein in the preparation method, in step S8, the AlO.sub.x film is simultaneously deposited on the front and the back of the P-type monocrystalline Si wafer by a tubular or platelike atomic layer deposition (ALD) device configured for double-sided deposition, wherein the AlO.sub.x film has a thickness of 2 nm-20 nm.

17. The low-cost passivated contact full-back electrode solar cell according to claim 10, wherein in the preparation method, in step S9, the SiN.sub.x passivation film or the SiN.sub.x/SiON.sub.x laminated passivation film is deposited on the front and the back of the P-type monocrystalline Si wafer by a tubular or platelike PECVD device, respectively, wherein the SiN.sub.x passivation film or the SiN.sub.x/SiON.sub.x laminated passivation film has a thickness of 50 nm-100 nm and a refractive index of 1.9-2.4.

18. The low-cost passivated contact full-back electrode solar cell according to claim 10, wherein in the preparation method, in step S11, a sintering temperature is controlled at 700° C.-900° C.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0046] To describe the technical solutions in the embodiments of the present invention more clearly, the accompanying drawings required for describing the embodiments are briefly described below. Obviously, the accompanying drawings in the following description show merely some embodiments of the present invention, and a person of ordinary skill in the art would also be able to derive other drawings from these accompanying drawings without creative efforts.

[0047] The FIGURE a schematic diagram showing the structure of a low-cost passivated contact full-back electrode solar cell prepared by the present invention.

[0048] Reference numerals: 1. front passivation film layer; 2. P-type monocrystalline Si wafer; 3. polycrystalline Si film layer; 4. Al-BSF layer; 5. back passivation film layer; 6. first electrode; and 7. second electrode.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0049] The following clearly and completely describes the technical solutions in the embodiments of the present invention by referring to the accompanying drawings. It will be apparent that the described embodiments are merely a part, rather than all, of the embodiments of the present invention. The following description of at least one exemplary embodiment is merely illustrative and not intended to limit the present invention and application or use thereof in any way. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

Embodiment 1

[0050] S1: A P-type monocrystalline Si wafer is configured as a Si substrate, where the Si wafer has a resistivity of 0.5 ohm-cm to 5 ohm-cm and a thickness of 120 μm-200 μm. Alkali polishing is then performed on the Si substrate using a 15 wt %-30 wt % KOH solution at 75° C.-85° C. [0051] S2: After performing the alkali polishing, RCA cleaning and HF cleaning for high cleanliness are performed. [0052] S3: A single-sided deposition is performed by a tubular or platelike PECVD device, that is, three-in-one multi-layer film deposition is performed on the back of the P-type monocrystalline Si wafer to grow a tunnel SiO.sub.x film layer, an in-situ doped amorphous Si film layer (TOPCon layer), and a texturing mask layer. The thickness of the tunnel SiO.sub.x film layer is less than 2 nm. The amorphous Si film layer is an in-situ phosphorus-doped film with a thickness of 50 nm-200 nm. The texturing mask layer is made of SiN.sub.x with a thickness of 50 nm-100 nm. Specifically, the TOPCon layer is produced by the in-situ doping deposition process of phosphine, silane, and hydrogen, and the texturing mask layer is configured to resist the corrosion of KOH or TMAH solution during the subsequent double-sided texturing process. [0053] S4: An annealing activation is performed on the amorphous Si film mentioned above by a tubular oxidation furnace to activate the in-situ doped phosphorus atoms. Simultaneously, the amorphous Si film layer deposited by PECVD is transformed into a polycrystalline Si film layer with a sheet resistance controlled at 50 ohm/sq-100 ohm/sq. In addition, during the high-temperature process, the hydrogen atoms in the film layer are diffused to the SiO.sub.2/Si interface to saturate the surface dangling bonds and increase the passivation effect. The process temperature of the annealing activation of this step is 700° C.-900° C., the time for the annealing activation is 1 h-2 h, and the doping concentration after activation is 1e.sup.18 CM.sup.−3-5e.sup.20 cm.sup.−3. [0054] S5: The texturing mask layer on the back of the Si wafer is etched by laser. Slots are created by the laser on a certain area (BSF area) on the back of the Si wafer of the cell, and a part of the texturing mask layer deposited in step S3 is ablated. [0055] S6: Subsequently, a double-sided texturing is performed on the P-type monocrystalline Si wafer using the KOH or TMAH solution (the polycrystalline Si film layer deposited in step S3 is protected by the texturing mask layer) to form a textured structure having a front pyramid and a back BSF pyramid. Before texturing, the Si wafer needs to be pre-cleaned using HF to remove the oxide layer formed on the front of the Si wafer and reduce the impact on the uniformity of texturing. [0056] S7: After performing the texturing, cleaning is performed by a 5 wt %-20 wt % HF solution to completely remove the residual texturing mask layer on the back of the Si wafer. [0057] S8: An AlO.sub.x film with a thickness of 2 nm-20 nm is simultaneously deposited on the front and back of the Si wafer by a tubular or platelike ALD device configured for double-sided deposition. Negatively charged AlO.sub.x forms a good field passivation effect on the P-type Si without affecting the TOPCon layer. [0058] S9: A SiN.sub.x passivation film or a SiN.sub.x/SiON.sub.x laminated passivation film are deposited on the front and back of the Si wafer by a tubular or platelike PECVD device, respectively, where the passivation film has a thickness of 50 nm-100 nm and a refractive index of 1.9-2.4. [0059] S10: A part of the AlO.sub.x film and a part of the SiN.sub.x passivation film or the SiN.sub.x/SiON.sub.x laminated passivation film on the back of the Si wafer are ablated by the laser. That is, the slotting process is performed by the laser on a certain area (BSF area) on the back of the Si wafer of the cell to ablate a part of the AlO.sub.x/SiN.sub.x/SiON.sub.x film layer deposited in step S9 so that the Al paste electrode and the Si surface are in direct contact, and the Al-BSF layer is formed in the sintering process. [0060] S11: An Ag electrode and an Al electrode are screen-printed in the TOPCon area and the BSF area, respectively, and the final sintering process is performed using a conventional sintering furnace of the PERC production line. The sintering temperature is controlled at 700° C.-900° C. The P-type full-back electrode solar cell is completely prepared.

[0061] As shown in the FIGURE, the low-cost P-type Si wafer passivated contact full-back electrode crystalline Si solar cell prepared by the present invention includes the P-type monocrystalline Si wafer 2, and the front passivation film layer 1 located on the front of the P-type monocrystalline Si wafer 2, as well as the polycrystalline Si film layer 3, the Al-BSF layer 4 and the back passivation film layer 5 that are located on the back of the P-type monocrystalline Si wafer 2, the first electrode 6 located under the polycrystalline Si film layer 3, and the second electrode 7 located under the Al-BSF layer 4.

[0062] The design solution of the present invention can produce solar cells with better cost performance and higher efficiency through less upgrading on the prior PERC production line. The P-type full-back electrode solar cell prepared by the present invention has the advantages of good process compatibility, high photoelectric conversion efficiency, and low preparation cost, which is of great significance to promote the large-scale production of low-cost and high-performance solar cells.

[0063] The preferred embodiments of the present invention are merely intended to explain the present invention rather than to limit the present invention. Any obvious changes or modifications made to the technical solution of the present invention should fall within the protection scope of the present invention.