CIRCUIT ASSEMBLY FOR LIMITING THE GATE CURRENT AT A FIELD-EFFECT TRANSISTOR

Abstract

A circuit arrangement for limiting the gate current at a field effect transistor, FET, comprises a first FET and a DC supply network connected to a gate terminal of the first FET; ¬wherein the supply network provides a voltage Vgg to the gate terminal of the first FET via a first connection comprising a high impedance resistor R1 and a second FET connected in series therewith and having a gate terminal; the second FET having an ON state at a gate-source voltage of 0 V and having its gate terminal also connected to the gate terminal of the first FET via a second connection in parallel with the resistor R1; wherein a voltage drop occurring across the resistor R1 results in increasing blocking of the second FET.

Claims

1. A circuit arrangement for limiting the gate current on a field effect transistor, FET, comprising a first FET and a DC supply network connected to a gate terminal of the first FET; the supply network providing a voltage V.sub.gg to the gate terminal of the first FET via a first connection comprising a high impedance resistor R.sub.1 and a second FET connected in series therewith and having a gate terminal; the second FET having an ON state at a gate-source voltage of 0 V and having its gate terminal also connected to the gate terminal of the first FET via a second connection in parallel with the resistor R.sub.1; wherein a voltage drop occurring across the resistor R.sub.1 results in increasing blocking of the second FET.

2. The circuit arrangement according to claim 1, wherein for RF decoupling in the second connection a second high-impedance resistor R.sub.2 is connected in parallel with the high-impedance resistor R.sub.1.

3. The circuit arrangement according to claim 1, wherein for RF decoupling the first connection and the second connection are connected to the gate terminal of the first FET via a common inductance L.

4. The circuit arrangement according to claim 1, wherein the first FET is a GaN or GaAs RF power HEMT-.

5. The circuit arrangement according to claim 1, wherein the first FET and the second FET are monolithically integrated on one chip-.

6. The circuit arrangement according to claim 1, wherein the first FET and the second FET are arranged on different chips.

7. The circuit arrangement according to claim 1, wherein the supply network does not comprise diodes or Zener diodes for limiting the gate current at the first FET.

8. An amplifier circuit, comprising a circuit arrangement according to claim 1, wherein an input power P.sub.in to be amplified is fed into the first FET via a third connection connected to the gate terminal of the first FET.

9. An apparatus for receiving microwave signals, comprising an amplifier circuit according to claim 8.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The invention is explained below in embodiment examples with reference to the accompanying drawing. It shows:

[0027] FIG. 1 a schematic representation of a conventional circuit arrangement for limiting the gate current in an amplifier circuit,

[0028] FIG. 2 a schematic representation of a first embodiment of a circuit arrangement according to the invention for limiting the gate current in an amplifier circuit,

[0029] FIG. 3 a schematic representation of a second embodiment of a circuit arrangement according to the invention for limiting the gate current in an amplifier circuit,

[0030] FIG. 4 a schematic representation of a third embodiment of a circuit arrangement according to the invention for limiting the gate current in an amplifier circuit, and

[0031] FIG. 5 various characteristic curves for comparing a conventional current limiter circuit and a current limiter circuit according to the invention.

DETAILED DESCRIPTION OF THE DRAWINGS

[0032] FIG. 1 shows a schematic diagram of a conventional circuit arrangement for limiting the gate current in an amplifier circuit. This comprises a FET 10 to be limited in its gate current and a DC supply network 20 connected to a gate terminal 12 of the FET 10; the supply network 20 providing a voltage V.sub.gg at the gate terminal 12 of the FET 10 via a connection 22 which comprises a high-impedance resistor R 220; a voltage drop occurring at the resistor R 220 leading to an increasing reduction in the gate current at the FET 10. In the exemplary amplifier circuit shown, an input power P.sub.in to be amplified is supplied to the first FET 10 via a third connection 30 connected to the gate terminal 12 of the first FET 10.

[0033] However, at high input powers P.sub.in, the voltage amplitudes at the input of the FET 10 are so large that a forward current occurs at the gate terminal 12. This is particularly detrimental to the robustness or lifetime of the FET 10 and is reduced by the high resistance R 220 in the supply network 20. The voltage dropped across resistor R 220 by the flowing current is thereby poled to produce more negative voltages at gate terminal 12, which in turn drive FET 10 further into pinch-off, thereby protecting it from high gate currents at the expense of increased negative reverse voltages. However, this method does not allow the gate current to be controlled, only reduced. Thus, as input powers P.sub.in increase, the forward current at gate terminal 12 continues to increase.

[0034] FIG. 2 shows a schematic representation of a first embodiment of a circuit arrangement according to the invention for limiting the gate current in an amplifier circuit. This comprises a first FET 10 to be limited in its gate current and a DC supply network 20 connected to a gate terminal 12 of the first FET 10; wherein the supply network 20 provides a voltage V.sub.gg at the gate terminal 12 of the first FET 10 via a first connection 22, which comprises a high-impedance resistor R.sub.1 220 and a second FET 222 connected in series therewith and having a gate terminal 224; the second FET 222 having an ON state at a gate-source voltage of 0 V and having its gate terminal 224 connected to the gate terminal 12 of the first FET 10 via a second connection 24 in parallel with the resistor R.sub.1 220 also; wherein a voltage drop occurring across the resistor R.sub.1 220 results in increasing blocking of the second FET 222. In the exemplary amplifier circuit shown in accordance with the invention, an input power P.sub.in to be amplified is fed into the first FET 10 via a third connection 30, which is connected to the gate terminal 12 of the first FET 10.

[0035] A control voltage is generated via the voltage dropping across the first resistor R.sub.1 220 when the gate current flows, which increasingly blocks the FET (depletion mode, normal-AN) connected in series. This can be compared to a variable resistor in the supply network, the value of which increases steadily as the gate current increases, thus providing an effective limit to the current, which is largely independent of the applied input power P.sub.in. In particular, the first FET 10 may be a GaN RF power HEMT, and the first FET 10 and the second FET 222 may be monolithically integrated on a single chip.

[0036] FIG. 3 shows a schematic representation of a second embodiment of a circuit arrangement for limiting the gate current according to the invention. The basic circuit structure corresponds to the embodiment shown in FIG. 2. Therefore, the reference signs and their respective assignment to the individual features apply accordingly. However, for RF decoupling, a second high-impedance resistor R.sub.2 240 is connected in parallel with the high-impedance resistor R.sub.1 220 in the second connection 24. Thus, according to the invention, RF decoupling in limiting the gate current takes place via two high-impedance resistors R.sub.1 220 and R.sub.2 240, whereby a voltage is dropped at the resistor R.sub.1 220 connected in series with the second FET 222, which increasingly blocks the second FET 222 and thereby limits the gate current of the first FET 10.

[0037] FIG. 4 shows a schematic representation of a third embodiment of a circuit arrangement for limiting the gate current according to the invention. The basic circuit structure corresponds to the embodiment shown in FIG. 2. Therefore, the reference signs and their respective assignment to the individual features apply accordingly. However, for RF decoupling, the first connection 22 and the second connection 24 are connected to the gate terminal of the first FET 10 via a common inductor L 26. Thus, according to the invention, RF decoupling when limiting the gate current is performed via an inductance L connected to the gate terminal 12 of the first FET 10. The resistor R.sub.1 is used here only to generate a negative reverse voltage at the gate source of the second FET 222 located in the supply network 20.

[0038] FIG. 5 shows various characteristic curves for comparing a conventional current limiter circuit and a current limiter circuit according to the invention.

[0039] Figure a) shows a linear and figure b) a logarithmically scaled comparison between the gate current (in amperes (A)) in a conventional resistor circuit for limiting the gate current according to FIG. 1 (interrupted curve) and a circuit arrangement according to the invention as shown in FIG. 3 (continuous curve), in each case as a function of the input power P.sub.in (in decibels milliwatts (dBm)). It can be clearly seen that in the embodiment according to the invention, extensive regulation of the gate current is made possible, whereby the maximum permissible gate current can be selected by adjusting the first resistor R.sub.1.

[0040] Figures c) and d) show respectively the reverse voltage at the gate of the first FET and the voltage drop across the first resistor R.sub.1 in a conventional resistor circuit for limiting the gate current according to FIG. 1 (interrupted curve) and a circuit arrangement according to the invention according to FIG. 3 (continuous curve), in each case as a function of the input power P.sub.in (in decibels milliwatts (dBm)). The voltage drop across the first resistor R.sub.1 in the conventional circuit is no different from the voltage across the first FET (V.sub.ds) and therefore poses no challenge for GaN technology in particular.

TABLE-US-00001 List of reference signs 10 First FET 12 Gate terminal (first FET) 20 Supply network 22 First connection 220 high resistance R.sub.1 222 second FET 224 Gate terminal (second FET) 24 second connection 240 second high impedance resistor R.sub.2 26 Inductance L 30 Third connection