SEMICONDUCTOR DIE HAVING A SODIUM STOPPER IN AN INSULATION LAYER GROOVE AND METHOD OF MANUFACTURING THE SAME

Abstract

The application relates to a semiconductor die having a semiconductor body including an active region, an insulation layer on the semiconductor body, and a sodium stopper formed in the insulation layer. The sodium stopper is arranged in an insulation layer groove which intersects the insulation layer vertically and extends around the active region. The sodium stopper is formed of a tungsten material that at least partly fills the insulation layer groove. Both the insulation layer groove and the tungsten material extend into the semiconductor body.

Claims

1. A semiconductor die, comprising: a semiconductor body comprising an active region and an edge termination region; an insulation layer on the semiconductor body; and a sodium stopper formed in the insulation layer, wherein the sodium stopper is arranged in an insulation layer groove which intersects the insulation layer vertically and extends around the active region, wherein the sodium stopper is formed of a tungsten material that at least partly fills the insulation layer groove, wherein both the insulation layer groove and the tungsten material extend into the semiconductor body.

2. The semiconductor die of claim 1, further comprising: a metallization layer on a frontside of the insulation layer, wherein the metallization layer covers at least a section of the insulation layer groove and is formed of a tungsten material.

3. The semiconductor die of claim 2, further comprising: a passivation layer covering the metallization layer.

4. The semiconductor die of claim 1, wherein the tungsten material that at least partly fills the insulation layer groove also forms a drain contact electrically connected to a drain region formed at least in the active region of the semiconductor body.

5. The semiconductor die of claim 1, further comprising: a channel stopper in a channel stopper trench extending vertically into the semiconductor body, wherein the channel stopper is arranged laterally between the sodium stopper and a lateral edge of the semiconductor die.

6. The semiconductor die of claim 1, further comprising: a chipping stopper in a chipping stopper trench extending vertically into the semiconductor body.

7. The semiconductor die of claim 6, wherein the chipping stopper trench is filled with an electrically conductive material and serves also as a channel stopper.

8. The semiconductor die of claim 6, further comprising: a vertical groove intersecting the insulation layer above the chipping stopper trench, wherein the vertical groove serves as an oxide peeling stopper.

9. The semiconductor die of claim 1, further comprising: a channel stopper in a channel stopper trench extending vertically into the semiconductor body; and a chipping stopper in a chipping stopper trench extending vertically into the semiconductor body, wherein the channel stopper is arranged laterally between the sodium stopper and a lateral edge of the semiconductor die.

10. The semiconductor die of claim 9, wherein the chipping stopper trench extends deeper into the semiconductor body than the channel stopper trench.

11. The semiconductor die of claim 9, wherein the chipping stopper trench is filled with an electrically conductive material and serves also as a channel stopper.

12. The semiconductor die of claim 1, wherein the sodium stopper forms a contact with the semiconductor body.

13. The semiconductor die of claim 1, wherein the sodium stopper is covered and contacted by a passivation layer.

14. The semiconductor die of claim 1, wherein the tungsten material only partly fills the insulation layer groove.

15. A semiconductor wafer, comprising: a semiconductor body comprising a first active region and a second active region; an insulation layer on the semiconductor body; a dicing region formed laterally between the first active region and the second active region; a first sodium stopper and a second sodium stopper formed in the insulation layer, wherein the first sodium stopper is arranged in a first insulation layer groove which intersects the insulation layer vertically and extends around the first active region, wherein the second sodium stopper is arranged in a second insulation layer groove which intersects the insulation layer vertically and extends around the second active region, wherein the first sodium stopper is formed of a tungsten material that at least partly fills the first insulation layer groove, wherein the second sodium stopper is formed of a tungsten material that at least partly fills the second insulation layer groove, wherein both the first insulation layer groove and the tungsten material that at least partly fills the first insulation layer groove extend into the semiconductor body, wherein both the second insulation layer groove and the tungsten material that at least partly fills the second insulation layer groove extend into the semiconductor body.

16. The semiconductor wafer of claim 15, further comprising: a first trench and a second trench arranged in the dicing region, wherein the first trench extends deeper into the semiconductor body than the second trench.

17. The semiconductor wafer of claim 16, wherein the first trench has the same depth as field electrode trenches formed in the first active region and the second active region, and wherein the second trench has the same depth as gate trenches formed in the first active region and the second active region.

18. The semiconductor wafer of claim 16, wherein the first trench is a needle trench and the second trench is a longitudinal trench surrounding the needle trench.

19. A method for manufacturing a semiconductor die, the method comprising: forming an active region in a semiconductor body; forming an insulation layer on the semiconductor body; and forming a sodium stopper in the insulation layer, wherein forming the sodium stopper comprises: etching an insulation layer groove into the insulation layer such that the insulation layer groove intersects the insulation layer vertically and extends around the active region; and at least partly filling the insulation layer groove with a tungsten material, wherein both the insulation layer groove and the tungsten material extend into the semiconductor body.

20. The method of claim 19, further comprising: etching a chipping stopper trench as a longitudinal trench that extends vertically into the semiconductor body in a same process step used to form needle trenches in the active region.

21. A method for manufacturing a semiconductor wafer, the method comprising: forming a first active region and a second active region in a semiconductor body; forming an insulation layer on the semiconductor body; forming a dicing region laterally between the first active region and the second active region; forming a first sodium stopper and a second sodium stopper in the insulation layer, wherein forming the first sodium stopper and the second sodium stopper comprises: etching a first insulation layer groove into the insulation layer such that the first insulation layer groove intersects the insulation layer vertically and extends around the first active region; etching a second insulation layer groove into the insulation layer such that the second insulation layer groove intersects the insulation layer vertically and extends around the second active region; and at least partly filling the first insulation layer groove and the second insulation layer groove with a tungsten material, wherein both the first insulation layer groove and the tungsten material that at least partly fills the first insulation layer groove extend into the semiconductor body, wherein both the second insulation layer groove and the tungsten material that at least partly fills the second insulation layer groove extend into the semiconductor body.

22. The method of claim 21, further comprising: forming a first trench and a second trench in the dicing region, wherein the first trench extends deeper into the semiconductor body than the second trench.

23. The method of claim 22, wherein the first trench has the same depth as field electrode trenches formed in the first active region and the second active region, and wherein the second trench has the same depth as gate trenches formed in the first active region and the second active region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Below, the semiconductor die or wafer and the manufacturing of the same are explained in further detail by means of exemplary embodiments. Therein, the individual features can also be relevant for the invention in a different combination.

[0036] FIG. 1 shows a portion of a semiconductor die in a vertical cross-section illustrating an edge termination region;

[0037] FIG. 2 shows a detailed view of the edge termination region of FIG. 1;

[0038] FIG. 3 shows a portion of a wafer in a cross-sectional view illustrating the edge termination region and a dicing region;

[0039] FIG. 4 shows a portion of a wafer in a top view illustrating the edge termination region at the corner and the dicing region;

[0040] FIG. 5 shows a portion of a wafer in a schematic top view illustrating a plurality of active regions;

[0041] FIG. 6 shows a vertical cross-section of a transistor cell formed in an active region of a wafer or die; and

[0042] FIG. 7 illustrates the manufacturing of a semiconductor die or wafer in a block diagram.

DETAILED DESCRIPTION

[0043] FIG. 1 shows a portion of a semiconductor die 1 in a vertical cross-section. The sectional plane lies at a corner of the die 1, see FIG. 4 for illustration. The die 1 comprises a semiconductor body 2 with an active region 3 (see FIGS. 5 and 6 in detail). On the semiconductor body 2, an insulation layer 4 is formed, namely a BPSG layer in the embodiment here. The insulation layer 4 is interrupted by a sodium stopper 5 preventing a sodium diffusion in the insulation layer 4 into the active region 3. The sodium stopper 5 is formed of a tungsten material 15, which can allow for a compact design. On a frontside 4.1 of the insulation layer 4, a metallization layer 21 is arranged, which is also made of tungsten material 15. A passivation layer 25 is deposited directly onto the metallization layer 21, made of imide in this example.

[0044] In the following, reference is also made to the enlarged view of FIG. 2. The metallization layer 21 has a vertical thickness 10 of about 100-200 nm, which can enable a precise structuring. An insulation layer groove 20, in which the tungsten material 15 of the sodium stopper 5 is arranged, intersects the insulation layer 4 vertically. It extends even further down into the semiconductor body 2, forming a drain contact 16 there. To improve the electrical connection, it intersects a doped region 17.

[0045] In the edge termination region 18, in which the sodium stopper 5 is formed, further etch termination structures are provided. A channel stopper 30 in a channel stopper trench 31 can be electrically contacted via the metallization layer 21. Applying an electrical potential to the channel stopper 30 can for instance prevent ions from entering into the active region 3. Furthermore, chipping stoppers 35 are formed in the semiconductor body 2 in respective chipping stopper trenches 36. The sodium stopper 5 is arranged laterally in between two chipping stoppers 35. In this example, the chipping stopper trenches 36 are respectively filled with an electrically conductive material 38 contacted via the metallization layer 21, the chipping stoppers 35 serving also as channel stoppers 37. They are on the same electrical potential as the channel stopper 30, the sodium stopper 5 and the drain contact 16.

[0046] Laterally between the sodium stopper 30 and an edge 32 of the die 1, further chipping stoppers 40 in further chipping stopper trenches 41 are formed (four in total, two of them being shown in FIG. 2). In contrast to the chipping stopper trenches 36, the further chipping stopper trenches 41 are not connected to the metallization layer 21. Nevertheless, a respective vertical groove 42 is formed in the insulation layer 4 above each further chipping stopper trench 41, the grooves 42 acting as oxide peeling stoppers 43. In this example, each groove 20, 42 or interconnect 19 formed in the insulation layer 4 is filled with tungsten material 15.

[0047] FIG. 3 shows a portion of a wafer 50 in a vertical cross-section, the cross-sectional plane lying not at a die corner in contrast to FIGS. 1 and 2 (see FIG. 4). In addition to the active region 3 and the edge termination region 18, a dicing region 55 is visible. The dicing region 55 is arranged in between active regions, which belong to separate dies after the separation process, e. g. laser dicing. A comparison between FIGS. 2 and 3 illustrates, that the metallization layer 15 connecting and contacting the different edge termination structures is only formed at the corner of the die. However, the sodium stopper 5 extends over the whole circumference around the active region 3, the same applies for the channel/chipping and oxide peeling stoppers 30, 35, 37, 40, 43. As mentioned above, two further combined chipping and oxide peeling stoppers 40, 43 are arranged between the die edge 32 or dicing region 55 and the active region 3.

[0048] In the dicing region 55, first trenches 61 and second trenches 62 are formed. The first trenches 61 extend deeper into the semiconductor body 2 than the second trenches 62. In this example, the first trenches 61 have the same depth like the chipping stopper trenches 36 and the further chipping stopper trenches 41, and the second trenches 62 have the same depth as the channel stopper trench 31. For orientation, a vertical direction 57 and a lateral direction 58 are shown.

[0049] FIG. 4 illustrates a portion of the wafer 50 in a top view showing a corner 65 of the die 1 and the dicing regions 55 formed there (the die 1 is not separated from the wafer 50 yet). The first trenches 61 are needle trenches 71. They are arranged in a grid 66 formed by the second trenches 62 which are elongated trenches 72. In this example, the elongated trenches 72 form quadratic cells 75, wherein a needle trench 71 is arranged centrally in each cell 75. Furthermore, the top view illustrates the lateral extension of the die edge termination structures discussed above, in the top and in the cross-sectional view the same reference numerals are used for the same structure, respectively. For illustration, the sectional planes A-A of FIGS. 1/2 and B-B of FIG. 3 are indicated.

[0050] FIG. 5 is a schematic top view of a larger portion of the wafer 50. A first active region 3.1 and a second active region 3.2 are shown, furthermore dicing regions 55 extending along the active regions 3.1, 3.2 are illustrated. Regarding their setup in detail, reference is made to FIGS. 3 and 4. After separating the wafer 5 along the dicing regions 55, the active regions 3.1, 3.2 are arranged in separate dies 1.1, 1.2. The schematic top view illustrates also a first sodium stopper 5.1 which surrounds the first active region 3.1 in a first groove 20.1 over a whole circumference as a closed line, and a second sodium stopper 5.2 surrounding the second active region 3.2 in a second groove 20.2. The other die edge structures discussed above are not shown in this schematic drawing, which applies also for the first and second trenches 61, 62 formed in the dicing regions 55.

[0051] FIG. 6 shows a vertical cross-section of a semiconductor transistor device 80 that can be formed in an active region 3. It comprises a source region 81, a body region 82, and a drift region 83 formed vertically between the body region 82 and the drain region 17. Further, it comprises a gate region 84 laterally aside the body region 82. In the gate region 84, a gate electrode 84.1 is arranged, separated from the body region 82 by an interlayer dielectric 84.2. By applying a voltage to the gate electrode 84.1, a channel formation in the body region 82 can be controlled.

[0052] The source and the body region 81, 82 are electrically contacted by the same frontside metallization 85. In this example, the source region 81, the drift region 83 and the drain region 17 are n-type, wherein the body region 82 is p-type. The frontside metallization 85 contacts further a field electrode 86.1 separated from the body and the drift region 82, 83 by a field dielectric 86.2. The field electrode 86.1 and the field dielectric 86.2 form a field electrode region 86. The field electrode region 86 is arranged in a field electrode trench 87, and the gate region 84 is arranged in a gate trench 88. In FIG. 5 the lateral arrangement of these trenches 87, 88 is shown (in a portion of the active region 3.1), the gate trenches 88 are longitudinal trenches 90 forming a grid 89 defining cells 91, wherein in each cell 91 a field electrode trench 87 formed as a needle trench 92 is arranged.

[0053] FIG. 7 illustrates some manufacturing steps 100 in a flow diagram. To obtain a trench structure discussed above, the channel stopper trench 31, second trenches 62 and gate trenches 88 are etched 101 into the semiconductor body 2. In a different process step 100.1 before or thereafter, the chipping stopper trenches 36, the further chipping stopper trenches 41, the first trenches 61, and the field electrode trenches 87 are etched 102. Therein, the longitudinal chipping stopper trenches 36 and the further chipping stopper trenches 41 are etched 101 in the same process step 100.1 like the needle trenches 92 in the active region 3 and the needle trenches 71 in the dicing region 55. After forming the insulation layer 4 on the semiconductor body 3, the insulation layer groove 20 is etched 104 into the insulation layer 4. Subsequently, the insulation layer groove 20 is filled 105 with the tungsten material 15, partly or in particular as a whole. Thereafter, the metallization layer 21 can be deposited 106, and the passivation layer 25 can be deposited 107 directly onto the metallization layer 21. The frontside metallization 80 formed in the active region, e.g. AlCu, can be deposited after the deposition 106 of the metallization layer 21 and before the deposition 107 of the passivation layer 25. In case that a solderable frontside is requested, a further metallization can be deposited onto the frontside metallization 80 after the deposition 107 of the passivation layer 25, e.g. TiW/Cu, for instance with a thickness of several micrometers (e.g. 5 μm).

[0054] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.