HETEROEPITAXIAL STRUCTURE WITH A DIAMOND HEAT SINK

Abstract

A heteroexpitaxial structure comprises a substrate having a silicon-on-insulator structure. Applied to one surface of a layer of single-crystal silicon having a (111) surface orientation is a layer of polycrystalline diamond. Formed on the other surface of said layer of (111) surface orientation single-crystal silicon of the silicon-on-insulator structure from which layers of a dielectric and another single-crystal silicon layer are first removed is an epitaxial structure of a semiconductor device based on wide-bandgap III-nitrides.

Claims

1. A method for manufacturing a heteroepitaxial structure with a diamond heat sink for semiconductor devices, in which a polycrystalline diamond and a semiconductor epitaxial structure based on wide bandgap III-nitrides are grown on a base multilayer substrate, and part of the base substrate layers is removed up to the base layer, wherein a multilayer substrate of a SOI structure is used as a base substrate, on one surface of the single-crystal silicon layer with (111) surface orientation of the SOI structure, a polycrystalline diamond layer is grown, another single-crystal silicon layer and the silicon dioxide layer of the SOI structure are removed after the deposition of the polycrystalline diamond layer, while the semiconductor epitaxial structure based on wide bandgap III-nitrides is formed on the other surface of the single-crystal silicon layer with (111) surface orientation.

2. The method of claim 1, wherein a 200-1,200 .Math.m single-crystal silicon (c-Si) with (111) surface orientation, or (110) or (100) is used as one of the base substrate layers of the SOI structure, and it is removed by etching silicon in xenon difluoride vapor or by liquid etching.

3. The method of claim 1, wherein a silicon dioxide structure with a thickness of no more than 500 nm is used as a dielectric layer, and it is removed by liquid etching in hydrofluoric acid solutions or by plasma-chemical etching in carbon tetrafluoride and oxygen mixture (CF.sub.4/O.sub.2).

4. The method of claim 1, wherein the preferred thickness of the polycrystalline diamond layer is not less than 50 .Math.m.

5. The method of claim 1, wherein the polycrystalline diamond layer is formed after the deposition of a monolayer of 5-10 nm diamond nanoparticles on the surface of silicon with (111) surface orientation.

6. The method of claim 1, wherein the monolayer of diamond nanoparticles is deposited on the surface of silicon (111) in an ultrasonic bath of modified 3% (w/w) aqueous suspension of diamond nanoparticles.

7. The method of claim 1, wherein the temperature of the base substrate during the growth of the polycrystalline diamond layer is maintained within 750-1,000° C.

8. The method of claim 1, wherein the thickness of the single-crystal silicon layer with (111) surface orientation is reduced up to least 0.2 .Math.m after the application of polycrystalline diamond.

9. The method of claim 1, wherein the epitaxial semiconductor structure is formed on the basis of wide bandgap III-nitrides in the form of Al.sub.xGa.sub.l-xN/GaN/Al.sub.xGa.sub.l-xN (where 0≤x≤1).

10. The method of claim 9, wherein the GaN layer in the semiconductor epitaxial structure based on wide bandgap III-nitrides is doped with a p-type impurity.

11. The method of claim 9, wherein the semiconductor epitaxial structure is formed on a silicon layer with (111) surface orientation by forming Al.sub.xGa.sub.1-XN buffer layers (where 0<x<1) and growing a gallium nitride (GaN) layer on the buffer layers, followed by the deposition of AIN or Al.sub.xGa.sub.1-xN barrier layers (where 0.2≤x≤1).

12. The heteroepitaxial structure with a diamond heat sink for semiconductor devices, containing a base substrate, a polycrystalline diamond layer and a semiconductor epitaxial structure based on wide bandgap III-nitrides, wherein the base substrate is based on a SOI structure, a polycrystalline diamond layer is deposited on one surface of the single-crystal silicon layer with (111) surface orientation of the SOI structure, and the semiconductor epitaxial structure based on wide bandgap III-nitrides is applied on the other surface of the single-crystal silicon layer with (111) surface orientation of the SOI structure with previously removed dielectric layer and the other single-crystal silicon layer.

13. The heteroepitaxial structure of claim 12, wherein the thickness of the polycrystalline diamond layer is not less than 50 .Math.m.

14. The heteroepitaxial structure of claim 12, wherein the epitaxial semiconductor structure is formed on the basis of wide bandgap III-nitrides in the form of Al.sub.xGa.sub.l-.sub.xN/GaN/Al.sub.xGa.sub.l-xN (where 0≤x≤1).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Claimed method and device is illustrated by the following drawings:

[0047] FIG. 1 illustrates a base substrate of the SOI structure;

[0048] FIG. 2 illustrates a base substrate of the SOI structure with a deposited polycrystalline diamond layer;

[0049] FIG. 3 illustrates the final epitaxial structure with a diamond heat sink.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0050] A SOI (silicon-on-insulator) substrate of the structure illustrated in FIG. 1, is used as a base substrate on which a polycrystalline diamond layer and subsequently a heteroepitaxial structure are formed. Layer 1 is single-crystal silicon (c-Si) with (111) surface orientation or (110) or (100). Layer 2 is silicon dioxide (SiO.sub.2); Layer 3 is single-crystal silicon with (111) surface orientation.

[0051] A polycrystalline diamond layer (Layer 4) is deposited on Layer 3 of the base substrate by plasma-enhanced chemical vapor deposition (PECVD) (FIG. 2).

[0052] A heteroepitaxial structure based on wide bandgap III-nitrides such as AlGaN/GaN (Layer 5), which serves as the basis for the future semiconductor device, is grown on the surface of silicon with (111) surface orientation (Layer 3) (FIG. 3).

[0053] A SOI (silicon-on-insulator) structure is used as a base substrate on which a polycrystalline diamond layer and subsequently a heteroepitaxial structure are formed. Layer 1 is single-crystal silicon (c-Si) with (111) surface orientation or (110) or (100) and with a thickness of 200-1,200 .Math.m. Layer 2 is silicon dioxide (SiO.sub.2) with a thickness of less than 500 nm (optimal thickness - 300 nm). Layer 3 is single-crystal silicon with (111) surface orientation and with a thickness of less than 2 .Math.m (optimal thickness - 500 nm).

[0054] A polycrystalline diamond layer (Layer 4) with a thickness of at least 50 .Math.m is deposited on Layer 3 of the base substrate by plasma-enhanced chemical vapor deposition (PECVD). The polycrystalline diamond layer is grown in two main steps: creating nucleation centers and synthesizing a diamond film in a microwave reactor. Prior to loading the substrate into the microwave reactor, it is seeded with diamond particles. Diamond nanoparticles are deposited on the silicon surface in order to create nucleation sites. In order to obtain a homogeneous film, it is necessary that diamond nanoparticles are uniformly distributed across the substrate surface. For this purpose, aqueous or alcoholic suspensions of ultra-dispersed (detonation) diamond with 5-50 nm diamond nanoparticles are used. The substrate is immersed in said suspension and placed in an ultrasonic bath for 15 minutes. Said processing provides high nucleation density (number of diamond particles per unit area) on the order of 10.sup.9-10.sup.10 cm.sup.-2 and good uniformity of particle distribution across the surface. Said substrate is then placed in a microwave plasma chemical reactor in which the diamond film is synthesized in methane-hydrogen mixture. Gases H.sub.2 (99.99999%) and CH.sub.4 (99.995%) are used. Polycrystalline diamond films are synthesized at a microwave power of 2.5-3.5 kW, chamber pressure of 50-70 torr, H.sub.2 flow rate of 300-500 cm.sup.3/min, CH.sub.4 flow rate of 2 to 20 cm.sup.3/min and substrate temperature of 750-1,000° C.

[0055] After the polycrystalline diamond layer is grown, the single-crystal silicon layer (Layer 1) and the silicon dioxide layer (Layer 2) are removed. Layer 1 is removed by etching silicon in xenon difluoride vapor (XeF.sub.2), which has high silicon etching selectivity with respect to most standard semiconductor materials. XeF.sub.2 with 99.999% purity is used for etching. Silicon was etched by the pulse method (the time of one pulse is 20-120 seconds) at a XeF2 vapor pressure of 2,000-3,000 mTorr. Under said conditions, the etching rate is about 270 nm/min for a 4-inch substrate. The total etching time and the number of etching cycles are selected depending on the thickness of Layer 1 for its complete removal.

[0056] Layer 2 is removed by well-known liquid etching techniques in hydrofluoric acid solutions or dry plasma-chemical etching in fluorine plasma. For example, a chemically pure buffer solution can be used to remove silicon dioxide by liquid etching (HF:NH.sub.4F=12.5:87.5%). The etching rate of silicon dioxide in said solution was 80-100 nm/min. The etching time is selected depending on the thickness of Layer 2 for its complete removal. Also, the silicon dioxide layer can be removed using the plasma-chemical method, by etching in plasma containing CF.sub.4/O.sub.2 gas mixture. The purity of both carbon tetrafluoride (CF.sub.4) and oxygen is 99.999%. Etching is performed at a pressure of 30 mTorr, CF.sub.4 flow rate of 20 standard cm.sup.3/min, O.sub.2 flow rate of 2 standard cm.sup.3/min, and power of 75 W. Under said conditions, the etching rate of silicon dioxide is 30-50 nm/min. The etching time is selected depending on the thickness of Layer 2 for its complete removal.

[0057] At the next process step, a heteroepitaxial structure based on wide bandgap III-nitrides, such as AlGaN/GaN (Layer 5), which serves as the basis for the future semiconductor device, is grown on the surface of silicon with (111) surface orientation (Layer 3). The heteroepitaxial structure is most often obtained by molecular beam epitaxy method or chemical vapor deposition.

[0058] In order to obtain an AlGaN/GaN heterostructure by molecular beam epitaxy, Ga (99.9995%) and Al (99.999%) sources, as well as ammonia NH.sub.3 (99.99995%) are used. The formation of the structure begins with the growth of Al.sub.xGa.sub.1-xN buffer layers, where 0≤x≤1, with a total thickness of 0.2-1.4 .Math.m on the surface of the silicon substrate. The buffer layers are grown at a temperature gradient of 1,150 to 800° C. During the growth of the buffer layers, the pressure is maintained in the range of 5.Math.10.sup.-5 to 3.Math.10.sup.-3 Pa. A 0.1-5 .Math.m gallium nitride (GaN) layer is then grown at a temperature of 800° C. and pressure of no more than 3.Math.10.sup.-3 Pa. Next, 2-30 nm thick AlN or Al.sub.xGa.sub.1-xN barrier layers (where 0.2<x<1) are grown at 800° C. A dielectric SiO.sub.2 or Si.sub.3N.sub.4 layer with a thickness of 3-10 nm can be then deposited at 800° C.

[0059] In order to obtain a heterostructure by gas-phase epitaxy, trimethylaluminum (99.999%), trimethylgallium (99.999%) and ammonia (99.9999%) are used as precursors. Hydrogen (99.9999%) is used as a carrier gas. 0.2-1.4 .Math.m thick Al.sub.xGa.sub.1-xN buffer layers (where 0≤x≤1) are first grown on the silicon substrate at 795-925° C. During the growth of the buffer layers, the pressure is maintained at 5 kPa. Then, a 0.1-5 .Math.m thick GaN layer is formed at 930° C. and 10 kPa. 2-30 nm AlN or Al.sub.xGa.sub.1-xN barrier layers (where 0.2<x<1) are then deposited at 900-930° C. Finally, a dielectric SiO.sub.2 or Si.sub.3N.sub.4 layer with a thickness of 3-10 nm can be deposited at 800° C.

[0060] The thermal conductivity of the resulting heterostructure will substantially depend on the thickness and composition of its layers. In this case, there will be no significant dependence of the thermal conductivity of the heterostructure on the manufacturing method.

[0061] The result is a heteroepitaxial structure with a high-quality polycrystalline diamond layer, grown on high-purity single-crystal silicon layer of low thickness (not less than 200 nm), which makes it possible to significantly increase the heat removal from the heteroepitaxial structure, because the thermal conductivity of said silicon layer corresponds to the thermal conductivity of bulk material (148 W/(m*K)), while the thermal contact resistance of the silicon/diamond transition is 7-20 m.sup.2*K/GW. The growth surface of polycrystalline diamond then can be used to mount the resulting semiconductor structure to a device package (e.g., a transistor). In addition, the high crystalline quality of all layers of the semiconductor structure with a diamond heat sink increases the yield of semiconductor devices.

[0062] The manufacturing method described above can easily be scaled up to manufacture substrates of different diameters up to 300 mm.

Embodiments of the Invention

Embodiment 1.

[0063] Using an experimental setup for plasma-enhanced chemical vapor deposition, 200 .Math.m thick polycrystalline diamond was grown on a silicon substrate with a 0.1 .Math.m thick AlN base epitaxial layer. Said diamond was grown in a microwave discharge using reaction mixture CH.sub.4(10%)/H.sub.2(88.5%)/O.sub.2(1.5%) according to the disclosed prototype method. The deposition conditions were as follows: chamber pressure — 95 Torr, hydrogen flow rate —0.531/min, input microwave power— 4.6 kW, substrate temperature — 940° C.

[0064] After the polycrystalline diamond layer is formed, the silicon substrate was removed, and an epitaxial heterostructure based on III-nitrides was grown on the other side of the AlN base layer using the prior art methods.

[0065] As a result, due to a high concentration of defects in the AlN layer and their subsequent translation into both the layers of the heteroepitaxial structure and the diamond layer, the thermal conductivity of the heterostructure with a diamond heat sink formed according to the prototype was 190 W/(m*K), while the thermal resistance was 395 m.sup.2*K/GW.

Embodiment 2.

[0066] A SOI structure was used as a base substrate. It comprised a 200 .Math.m thick single-crystal silicon (c-Si) with (111) surface orientation as Layer 1, a 300 nm thick silicon dioxide (SiO.sub.2) as Layer 2 and a 500 nm thick single-crystal silicon with (111) surface orientation as Layer 3.

[0067] A 50 .Math.m thick polycrystalline diamond layer (Layer 4) was applied to Layer 3 of the base substrate by plasma-enhanced chemical vapor deposition (PECVD). The polycrystalline diamond layer was grown in two main steps: creating nucleation centers and synthesizing a diamond film in a microwave reactor. Prior to loading the substrate into the microwave reactor, it was seeded with diamond nanoparticles. The substrate was then placed in a microwave plasma chemical reactor in which the diamond film was synthesized in methane-hydrogen mixture using H.sub.2 (99.99999%) and CH.sub.4 (99.995%) gases. The polycrystalline diamond film was synthesized at a microwave power of 3.5 kW, chamber pressure of 70 Torr, H.sub.2 flow rate of 400 cm.sup.3/min, CH.sub.4 flow rate of 10 cm.sup.3/min and substrate temperature of 800° C.

[0068] After the polycrystalline diamond layer was deposited, the single-crystal silicon layer (Layer 1) and the silicon dioxide layer (Layer 2) were removed. Layer 1 was removed by etching silicon in xenon difluoride vapor (XeF.sub.2) with 99.999% purity using the pulse method (time of one pulse - 60 seconds) at a XeF.sub.2 vapor pressure of 3,000 mTorr. The etching rate was about 270 nm/min for a 4-inch substrate. The etching time and the number of etching cycles were selected so that Layer 1 could be completely removed. Layer 2 was removed by liquid etching using a chemically pure buffer solution (HF:NH4F=12.5:87.5%). The etching rate of silicon dioxide in said solution was 90 nm/min. The etching time was selected so that Layer 2 could be completely removed.

[0069] Next, a heteroepitaxial structure based on wide bandgap III-nitrides, such as AlGaN/GaN (Layer 5), was grown on the surface of silicon with (111) surface orientation (Layer 3). The heteroepitaxial structure was formed by molecular beam epitaxy using Ga (99.9995%) and Al (99.999%) sources, as well as ammonia NH.sub.3 (99.99995%). The formation of the structure began with the growth of Al.sub.xGa.sub.1-xN buffer layers (where 0≤x≤1) with a total thickness of 0.2 .Math.m on the surface of the silicon substrate. The buffer layers were grown at a temperature gradient of 1,150 to 800° C. During the growth of the buffer layers, the pressure is maintained in the range of 5.Math.10.sup.-5 to 3.10.sup.-3 Pa. Then, a 0.1 .Math.m thick gallium nitride (GaN) layer was grown at a temperature of 800° C. and pressure of no more than 3.10.sup.-3 Pa. Next, 2 nm thick AlN or Al.sub.xGa.sub.1-xN barrier layers (where 0.2<x<1) were formed at 800° C. A 3 nm thick SiO.sub.2 dielectric layer was then deposited at 800° C.

[0070] The result was the heteroepitaxial structure with a diamond heat sink having a thermal conductivity of 315 W/(m*K) and thermal resistance of 165 m.sup.2*K/GW.

Embodiment 3.

[0071] The polycrystalline diamond layer and heteroepitaxial structure were formed as described in Embodiment 2, but using the following methods and under the following operating conditions.

[0072] A SOI structure was used as a base substrate. It comprised a 1,200 .Math.m thick single-crystal silicon (c-Si) with (110) surface orientation as Layer 1, a 500 nm thick silicon dioxide (SiO.sub.2) as Layer 2 and a 2 .Math.m thick single-crystal silicon with (111) surface orientation as Layer 3.

[0073] A 50 .Math.m thick polycrystalline diamond layer (Layer 4) was deposited on Layer 3 of the base substrate by plasma-enhanced chemical vapor deposition (PECVD).

[0074] After the polycrystalline diamond layer was grown, the single-crystal silicon layer (Layer 1) and the silicon dioxide layer (Layer 2) were removed. Layer 1 was removed by etching silicon in xenon difluoride vapor (XeF.sub.2) with 99.999% purity using the pulse method (time of one pulse - 60 seconds) at a XeF.sub.2 vapor pressure of 3,000 mTorr. Under these conditions, the etching rate was about 270 nm/min for a 4-inch substrate. The etching time and the number of etching cycles were selected so that Layer 1 could be completely removed. Layer 2 was removed using the plasma-chemical method by etching in plasma containing CF.sub.4/O.sub.2 gas mixture. The purity of both carbon tetrafluoride (CF.sub.4) and oxygen was 99.999%. Etching was performed at a pressure of 30 mTorr, CF.sub.4 flow rate of 20 standard cm.sup.3/min, O.sub.2 flow rate of 2 standard cm.sup.3/min, and power of 75 W. The etching rate of silicon dioxide was 50 nm/min. The etching time was selected so that Layer 2 could be completely removed.

[0075] Next, a heteroepitaxial structure based on wide bandgap III-nitrides such as AlGaN/GaN (Layer 5) was grown on the surface of silicon with (111) surface orientation (Layer 3). The heteroepitaxial structure was formed by molecular beam epitaxy using Ga (99.9995%) and Al (99.999%) sources, as well as ammonia NH.sub.3 (99.99995%). The formation of the structure began with the growth of Al.sub.xGa.sub.1-xN buffer layers (where 0≤x≤1) with a total thickness of 1.4 .Math.m on the surface of the silicon substrate. The buffer layers were grown at a temperature gradient of 1,150 to 800° C. During the growth of the buffer layers, the pressure is maintained in the range of 5.Math.10.sup.-5 to 3.Math.10.sup.-3 Pa. A 5 .Math.m thick gallium nitride (GaN) layer was grown at a temperature of 800° C. and pressure of no more than 3.Math.10.sup.-3 Pa. Next, 30 nm AlN barrier layer were deposited at 800° C. Then, a 10 nm thick Si.sub.3N.sub.4 dielectric layer was deposited at 800° C.

[0076] The result is the heteroepitaxial structure with a diamond heat sink having a thermal conductivity of 277 W/(m*K) and thermal resistance of 290 m.sup.2*K/GW.

Embodiment 4.

[0077] The polycrystalline diamond layer was obtained as described in Embodiment 2, but using the following methods and under the following operating conditions.

[0078] A SOI structure was used as a base substrate. It contained 500 .Math.m thick single-crystal silicon (c-Si) with (100) surface orientation as Layer 1, 300 nm thick silicon dioxide (SiO.sub.2) as Layer 2 and 500 nm thick single-crystal silicon with (111) surface orientation as Layer 3.

[0079] A 200 .Math.m thick polycrystalline diamond layer (Layer 4) was deposited on Layer 3 of the base substrate by plasma-enhanced chemical vapor deposition (PECVD).

[0080] After the polycrystalline diamond layer was deposited, the single-crystal silicon layer (Layer 1) and the silicon dioxide layer (Layer 2) were removed. Layer 1 was removed by etching silicon in xenon difluoride vapor (XeF.sub.2) with 99.999% purity using the pulse method (time of one pulse - 60 seconds) at a XeF.sub.2 vapor pressure of 3,000 mTorr. The etching rate was about 270 nm/min for a 4-inch substrate. The etching time and the number of etching cycles were selected so that Layer 1 could be completely removed. Layer 2 was removed by liquid etching using a chemically pure buffer solution (HF:NH.sub.4F=12.5:87.5%). The etching rate of silicon dioxide in said solution was 90 nm/min. The etching time was selected for the complete removal of Layer 2.

[0081] Layer 3 was then thinned to a thickness of 200 nm by mechanical grinding/polishing of silicon.

[0082] In order to obtain a heterostructure by gas-phase epitaxy, trimethylaluminum (99.999%), trimethylgallium (99.999%) and ammonia (99.9999%) were used as precursors. Hydrogen (99.999%) was used as a carrier gas. Al.sub.xGa.sub.1-xN buffer layers (where 0≤x≤1) with a thickness of 1 .Math.m were first grown on the silicon substrate at 795-925 C. During the growth of the buffer layers, the pressure was maintained at 5 kPa. A 5 .Math.m GaN layer was then formed at 930° C. and 10 kPa. AlN or Al.sub.xGa.sub.1-xN barrier layers (where 0.2<x<1) with a thickness of 30 nm are then grown at 900° C. Finally, a 10 nm thick SiO.sub.2 dielectric layer was deposited at 900° C.

[0083] The result was the heteroepitaxial structure with a diamond heat sink having a thermal conductivity of 514 W/(m*K) and thermal resistance of 201 m.sup.2*K/GW.

[0084] The claimed group of inventions can be widely used in semiconductor technology for manufacturing microwave devices and power electronic devices such as high-electron-mobility transistors (HEMT), bipolar junction transistors (BJT), heterojunction bipolar transistors (HBT), PIN diodes, Schottky diodes, rectifiers, etc., by improving heat removal from semiconductor structures. This allows improve the performance of semiconductor devices and to scale up the manufacturing process based on the subject method to substrates of different diameters up to 300 mm.

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