CAPACITOR STRUCTURE WITH VIA EMBEDDED IN POROUS MEDIUM

Abstract

A capacitor structure that includes a substrate; a conductive layer above the substrate; and a porous layer, above the conductive layer, having pores that extend perpendicularly from a top surface of the porous layer toward the conductive layer. The porous layer comprises a first region in which pores conductive wires are disposed, and a second region in which pores a metal-insulator-metal (MIM) structure is disposed. The first region may be used as a via to contact a bottom electrode of the capacitor structure.

Claims

1. A capacitor structure, comprising: a substrate; a first conductive layer above the substrate; and a porous layer made of anodic aluminum oxide, above the first conductive layer, having pores that extend perpendicularly from a top surface of the porous layer toward the first conductive layer, wherein the porous layer comprises a first region in which pores conductive wires are disposed, the bottom ends of the conductive wires contacting the first conductive layer at the bottom of the pores of the first region and the top ends of the conductive wires contacting a second conductive layer on the top surface of the porous layer in the first region, whereby the conductive wires constitute a conductive via through the porous layer, the conductive via interconnecting the first and second conductive layers, and the porous layer comprises a second region in which pores of a metal-insulator-metal structure is disposed.

2. The capacitor structure of claim 1, wherein the porous layer comprises a third region having empty pores, the third region separating the first region and the second region.

3. The capacitor structure of claim 2, wherein the third region is immediately adjacent to the first region and immediately adjacent to the second region.

4. The capacitor structure of claim 1, wherein the metal-insulator-metal structure disposed in the pores of the second region comprises a first metal layer, disposed conformally into the second region, an insulator layer disposed conformally over the first metal layer, and a second metal layer disposed conformally over the insulator layer, and wherein the first metal layer contacts the conductive layer at the bottom of each pore of the second region.

5. The capacitor structure of claim 1, wherein the first conductive layer comprises a first layer and a second layer, the second layer disposed between the first layer and the porous layer.

6. The capacitor structure of claim 5, wherein the first layer is made of aluminum and the second layer is made of tungsten.

7. The capacitor structure of claim 5, wherein the second layer is discontinuous and open under the first region and/or the second region of the porous layer.

8. The capacitor structure of claim 1, further comprising: a metal layer, above the conductive layer, surrounding the porous layer from the sides.

9. The capacitor structure of claim 1, further comprising: an additional conductive layer in contact with the metal-insulator-metal structure; wherein the second conductive layer is isolated from the first conductive layer.

10. A method of fabricating a capacitor structure, the method comprising: forming a porous layer made of anodic aluminum oxide above a first conductive layer, the porous layer having pores that extend perpendicularly from a top surface of the porous layer toward the conductive layer; forming conductive wires in the pores of a first region of the porous layer, the bottom ends of the conductive wires contacting the first conductive layer at the bottoms of the pores of the first region, the conductive wires extending to the top of the porous layer; forming a second conductive layer on the top surface of the porous layer in the first region, the top ends of the conductive wires contacting the second conductive layer whereby the conductive wires comprise a conductive via through the porous layer, the conductive via interconnecting the first and second conductive layers; and forming a metal-insulator-metal structure in the pores of a second region of the porous layer.

11. The method of claim 10, wherein forming the conductive wires in the pores of the first region comprises: depositing a first hard mask over the porous layer, the first hard mask being open over the first region; and growing the conductive wires in the pores of the first region by electro-chemical deposition.

12. The method of claim 11, wherein forming the metal-insulator-metal structure in the pores of the second region comprises: removing the first hard mask; depositing a second hard mask covering the first region and an adjacent third region of the porous layer; and depositing the metal-insulator-metal structure into the porous layer and over the second hard mask.

13. The method of claim 12, further comprising: forming an additional first conductive layer over the metal-insulator-metal structure; etching the metal-insulator-metal structure and the second hard mask over a section of the first region to expose the first region in the section; forming an insulation layer over the additional conductive layer, the insulator layer fully covering the additional conductive layer; and forming a second conductive layer over the exposed section of the first region and at least a portion of the insulation layer, the second conductive layer in contact with the top ends of the at least some of the conductive wires.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Further features and advantages of the present invention will become apparent from the following description of certain embodiments thereof, given by way of illustration only, not limitation, with reference to the accompanying drawings in which:

[0050] FIG. 1 illustrates in a cross-section view a conventional layout for embedding a capacitor structure into a porous template;

[0051] FIG. 2 illustrates in a cross-section view the effective structure resulting from the conventional structure of FIG. 1;

[0052] FIG. 3 shows an enlarged view of a section of the effective structure of FIG. 2;

[0053] FIG. 4 shows in a cross-section view a via formed in the effective structure of FIG. 2;

[0054] FIG. 5 is a top view illustrates the effective capacitance area resulting from the conventional structure of FIG. 1;

[0055] FIG. 6 illustrates the ratio of the effective capacitance area to the total area as a function of capacitor surface area for the convention structure of FIG. 1;

[0056] FIGS. 7A-7C illustrate in a cross-section view a proposed layout for embedding a capacitor structure into a porous template according to an embodiment;

[0057] FIG. 8 illustrates the effective capacitance area resulting from the proposed layout according to an environment;

[0058] FIG. 9 illustrates the impact of the proposed layout on the ratio of net to raw capacitance;

[0059] FIGS. 10A-10K illustrate a process for producing a capacitor structure in accordance with the proposed layout, according to an embodiment;

[0060] FIG. 11 illustrates an example capacitor structure according to an environment.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0061] FIG. 7A illustrates in a cross-section view a proposed layout 700 for embedding a capacitor structure into a porous region according to an embodiment. As above, the underlying structure is assumed to include a substrate 102, a conductive layer 104 above the substrate 102, and a metal layer 106 above the conductive layer 104.

[0062] As shown in FIG. 7A, rather than defining, within the metal layer 106, interleaving anodized and non-anodized regions, the metal layer 106 may be anodized to form a continuous porous layer 702.

[0063] In an embodiment, the continuous porous layer 702 may be designed to extend over the entirety of the wafer surface. For example, in one implementation, a wafer-level anodization may be used to obtain the porous layer 702. Such an embodiment may be suitable in the case that a uniform anodization across the wafer can be ensured. This can be done by selecting the layer 104 such that it enables a uniform charge distribution across the wafer. In an example experiment, uniform charge distribution across the wafer was obtained using a layer of tungsten of 300 nm as the layer 104.

[0064] In another embodiment, as shown in FIG. 7A, certain regions 106a of the metal layer 106 may be left non-anodized. Regions 106a may be located at the edges of the die and/or in the dicing street (beyond the edge of the die or at the edge of the wafer).

[0065] In another environment, the metal layer 106 may be left non-anodized in a few islands within the porous layer 702. The non-anodized metal islands may be in the form of a sparse metal grid within the porous layer 702. Such an embodiment may be suitable in the case that the die is isolated (e.g. by a field oxide) from the wafer backside. The non-anodized metal islands help ensure that the anodic voltage is provided in a uniform manner across the wafer.

[0066] As shown in FIG. 7B, the porous layer 702 is then partitioned between regions 702a designed for receiving capacitive structures, and regions 702b designed for serving as electrical vias in the capacitor structure. In the regions 702a, a MIM stack may be deposited into the pores. In the regions 702b, conductive wires may be formed in the pores to provide the electrical vias vertically through the structure. In an embodiment, the conductive wires may be grown using electrochemical deposition (ECD) inside the pores of the regions 702b.

[0067] By using the layout 700, the effective utilization of the wafer area is increased substantially. Indeed, as a porous to non-porous transition is no longer needed to implement an electrical via, the via can now be placed much closer to an adjacent functional MIM structure. As such, the lateral footprint of a via can be reduced significantly.

[0068] In practice, some isolation may be needed between regions 702a and 702b, for example due to process overlay rules. In an embodiment, as shown in FIG. 7C, when a region 702a is adjacent to a region 702b in which a via is to be built, a small portion 702c of region 702a (e.g., 5-10 microns) may be designated as an isolation region. In the isolation region, neither a MIM structure nor conductive wires are built. In an embodiment, the pores of the region 702c may be left empty.

[0069] However, the lateral footprint of a via remains very small. In experiments, the inventors have observed that an electric via with an effective width of 15 microns may require a lateral footprint of only 27 microns. This may be reduced further with better photolithographic alignment.

[0070] As mentioned above, electrical vias may be needed in great numbers in the capacitor structure to provide contact redundancy and/or for ESR/ESL control. By substantially reducing the lateral footprint of a via, the proposed layout can thus have a substantial impact on the effective capacitance resulting from the structure.

[0071] FIG. 8 is a top view 800 illustrating the effective capacitance area resulting from the proposed layout according to an embodiment. In particular, the area 802 corresponds to the wafer area in which a capacitance structure is built. Area 802 may correspond to the regions 702a shown in FIG. 7B be above. Conversely, areas 804 are wafer areas in which vias are built. Areas 804 may correspond to regions 702b illustrated in FIG. 7B above. In another embodiment, areas 804 may correspond to regions 702b and 702c as shown in FIG. 7c illustrated in FIG. 7C above. The area 808 corresponds to the dicing area of the wafer.

[0072] Optionally, areas 806 corresponding to regions of non-anodized metal may be provided. As mentioned above, these regions may be provided for the purpose of enhancing the anodization process across the wafer. Alternatively, areas 806 may correspond to wafer areas in which vias are built, similar to areas 804.

[0073] As shown in FIG. 8, the effective capacitive area is significantly increased relative to the total area of the wafer, as compared to the conventional layout illustrated in FIG. 5. This is further illustrated in FIG. 9, which shows the ratio of the effective capacitance area to the total wafer area as a function of capacitor surface area according to an example implementation. Particularly, in FIG. 9, the line 902 corresponds to performance using the layout of the present invention, whereas the line 904 corresponds to performance using the conventional layout. As shown, the utilization ratio increases significantly for all capacitor values. For smaller structures, the increase may be as high as 100%, doubling capacitive density. This kind of improvement may also be observed in a structure with high contact redundancy.

[0074] FIGS. 10A-10K illustrate an example process for producing a capacitor structure in accordance with the proposed layout, according to an embodiment. This example process is provided for the purpose of illustration only and is not limiting of embodiments of the present invention.

[0075] As shown in FIG. 10A, the process begins by forming a stack including a substrate 102, a conductive layer 104 above the substrate, and a metal layer 106 above the conductive layer 106.

[0076] In an embodiment, the conductive layer 104 comprises a first layer and a second layer, with the second layer disposed between the first layer and the metal layer 106. In an embodiment, the first layer is made of aluminum and the second layer is made of tungsten. The metal layer 106 may be made of aluminum.

[0077] Next, as shown in FIG. 10B, the process includes anodizing some or all of the metal layer 106 to form a porous layer 108 above the conductive layer 104. The porous layer 108 has pores that extend perpendicularly from a top surface of the porous layer 108 toward the conductive layer 104. When the metal layer 106 is made of aluminum, the porous layer 108 is made of anodic aluminum oxide (AAO).

[0078] In FIG. 10B, it is illustrated that the metal layer 106 is anodized in its entirety. While this embodiment is possible, in practice a small portion of metal layer 106 may be left non-anodized at the edges of the die and/or in the dicing street.

[0079] Because of the proposed layout, a uniform anodization can be obtained across the wafer. As such, the porous layer 108 has well-formed pores, i.e., they are substantially uniform and extend all the way down, substantially perpendicularly, to the conductive layer 104. In practice, an extra etching step may be used to ensure that the pores are fully open onto the conductive layer 104.

[0080] Next, as shown in FIG. 10C, a first hard mask layer 132 is applied over the porous layer 108. The first hard mask layer 132 is patterned to have openings over a defined first region 110 of the porous layer 108.

[0081] Preferably, the material for first hard mask layer 132 may be selected so as to be highly non-conformal to avoid that it enters into the pores of the porous layer 108.

[0082] Subsequently, as shown in FIG. 10D, conductive wires are formed in the pores of the first region 110. In an embodiment, the conductive wires are grown by electrochemical deposition (ECD). The conductive wires may be made of nickel or copper, for example. In an embodiment, the bottom ends of the conductive wires contact the conductive layer 104 at the bottoms of the pores of the first region 110.

[0083] The first hard mask layer 132 is then removed, and a second hard mask layer 112 is applied and patterned as shown in FIG. 10E. Specifically, the second hard mask layer 110 is patterned so as to cover the first region 110 of the porous layer as well as an adjacent third region 130 of the porous region. As further described below, the third region 130 will serve as an isolation region according to this embodiment.

[0084] Next, as shown in FIG. 10F, a MIM structure is disposed into the pores of a second region 120 of the porous layer 108. According to this embodiment, the second region 120 corresponds to the region of the porous layer 108 that is not covered by the second hard mask 110, i.e., outside of the first region 110 and the third region 130.

[0085] In an embodiment, this includes depositing the MIM structure into the porous layer 108 and over the second hard mask 112. In an embodiment, the top metal layer of the MIM structure may be etched over the first region 110 and the third region 130 as shown in FIG. 10F.

[0086] The deposition of the MIM structure into the pores of the second region 120 is highly conformal. In an embodiment, the MIM structure comprises a first metal layer (114), disposed conformally into the second region (120), an insulator layer (116) disposed conformally over the first metal layer (114), and a second metal layer (118) disposed conformally over the insulator layer (116). In an embodiment, the first metal layer contacts the conductive layer 104 at the bottom of each pore of the second region 120.

[0087] Next, as shown in FIG. 10G, a first conductive layer 122 may be formed over the MIM structure. The first conductive layer 122 may be etched over the first region 110 and the third region 130 as shown in FIG. 10G. In an embodiment, the first conductive layer 122 may serve as a top electrode of the capacitor structure.

[0088] Subsequently, as shown in FIG. 10H, the MIM structure (the first metal layer 114 and the insulator 116) and the second hard mask 112 are etched over at least a section of the first region 110 of the porous layer. This exposes the top ends of at least some of the conductive wires built into the first region 110 of the porous layer.

[0089] Next, as shown in FIG. 10I, an insulation layer 124 is formed over the first conductive layer 122. The insulation layer 124 fully covers (encapsulates) the first conductive layer 122.

[0090] Then, as shown in FIG. 10J, a second conductive layer 126 is formed. The second conductive layer 126 covers the exposed section of the first region 110 and at least a portion of the insulation layer 124. The second conductive layer 126 is in contact with the exposed top ends of at least some of the conductive wires. In an embodiment, the second conductive layer may serve as a contact to the bottom electrode of the capacitor structure.

[0091] Finally, as shown in FIG. 10K, a passivation layer 128 may be formed over the structure.

[0092] FIG. 11 illustrates an example capacitor structure 1100 according to an embodiment. Example structure 1100 is provided for the purpose of illustration and is not limiting of embodiments. Capacitor structure 1100 may be obtained using the process described above.

[0093] As shown, capacitor structure 1100 includes a porous layer that comprises a first region 110, a second region 120, and a third region 130.

[0094] In the first region 110, conductive wires are disposed in the pores of the porous layer, providing a vertical electrical via through the structure. The bottom ends of the conductive wires contact a conductive layer 104 at the bottom of the pores of the first region 110.

[0095] In the second region 120, a MIM structure is formed in the pores of the porous layer, providing a capacitor in the structure.

[0096] The third region 130 separates the first region 110 and the second region 120. In embodiment, the third region 130 isolates the first region 110 and the second region 120. In an embodiment, the pores of the third region 130 are empty.

[0097] In an embodiment, the conductive layer 104 comprises a first layer and a second layer, the second layer disposed between the first layer and the porous layer. In an embodiment, the second layer is discontinuous and open under the first region 110 and/or the second region 120 of the porous layer.

Additional Variants

[0098] Although the present invention has been described above with reference to certain specific embodiments, it will be understood that the invention is not limited by the particularities of the specific embodiments. Numerous variations, modifications and developments may be made in the above-described embodiments within the scope of the appended claims.