Component Carrier with Stack-Stack Connection for Connecting Components

Abstract

A component carrier includes a stack with at least one electrically insulating layer structure and electrically conductive layer structures some of which have a first density of trace structures and a second density of connection structures, and a further stack with at least one further electrically insulating layer structure and further electrically conductive layer structures some of which have a third density of further trace structures and a fourth density of further connection structures. A first component is applied to the stack and a second component is embedded in the further stack. The connection structures are respectively connected to the further connection structures. The first density of trace structures is lower than the third density of further trace structures. The stack and the further stack are connected with each other by the connection structures and by the further connection structures. The first component is connected to the second component.

Claims

1. A component carrier, comprising: a stack comprising at least one electrically insulating layer structure and a plurality of electrically conductive layer structures at least part of which having a first density of trace structures and a second density of connection structures; a further stack comprising at least one further electrically insulating layer structure and a plurality of further electrically conductive layer structures at least part of which having a third density of further trace structures and a fourth density of further connection structures; at least one first component applied to the stack; and at least one second component embedded in the further stack; wherein the connection structures are respectively connected to the further connection structures; wherein the first density of trace structures is lower than the third density of further trace structures; wherein the stack and the further stack are connected with each other by the connection structures of the stack and by the further connection structures of the further stack; and wherein the at least one first component is connected to the at least one second component.

2. The component carrier according to claim 1, wherein the at least one first component comprises at least one component being embedded in the stack and/or at least one component being surface mounted on the stack.

3. The component carrier according to claim 1, wherein the further stack is surface-mounted on the stack.

4. The component carrier according to claim 1, wherein the at least one second component is encapsulated by an electrically insulating encapsulant.

5. The component carrier according to claim 1, wherein the electrically conductive layer structures comprise a lower density stack coupling region and a higher density stack coupling region, wherein the higher density stack coupling region has the first density of trace structures and has the second density of connection structures.

6. The component carrier according to claim 5, wherein a line pitch of the lower density stack coupling region is in a range from 30 μm to 120 μm.

7. The component carrier according to claim 5, wherein a line pitch of the higher density stack coupling region is in a range from 2 μm to below 30 μm.

8. The component carrier according to claim 1, wherein a line pitch of the further electrically conductive layer structures is in a range from 0.4 μm to 10 μm.

9. The component carrier according to claim 1, wherein at least one of the at least one first component and the at least one second component comprises at least one of the group comprising a processor chip, a memory chip, a wafer level package, a bridge die, stacked dies, and an interposer, in particular an active interposer.

10. The component carrier according to claim 1, wherein at least part of the further connection structures is located at a bottom main surface of the further stack.

11. The component carrier according to claim 1, wherein at least part of the further connection structures is located at a top main surface of the further stack.

12. The component carrier according to claim 1, wherein the second density of connection structures and the fourth density of further connection structures differ from each other by not more than +/−20%, in particular differ from each other by not more than +/−5%, more particularly are substantially the same.

13. The component carrier according to claim 1, wherein the further connection structures are arranged at a main surface of the further stack facing the stack.

14. The component carrier according to claim 1, further comprising: yet another stack comprising a plurality of other electrically conductive layer structures having a fifth density of other trace structures and a sixth density of other connection structures, and at least one third component embedded in the other stack; wherein the second density of connection structures and the sixth density of other connection structures differ from each other by not more than +/−20%; wherein the first density of trace structures is lower than the fifth density of other trace structures; wherein the stack and the other stack are connected with each other by the connection structures of the stack and by the other connection structures of the other stack; and wherein the at least one first component and/or the at least one second component is or are connected to the at least one third component.

15. The component carrier according to claim 1, further comprising: at least one other component being mounted on a main surface of the further stack, which main surface faces away from the stack.

16. The component carrier according to claim 1, wherein the stack has an asymmetric build-up.

17. The component carrier according to claim 1, wherein at least one of the group consisting of the further stack and a surface mounted one of the at least one first component is mounted at least partially in a recess formed in a main surface of the stack.

18. The component carrier according to claim 1, comprising at least one of the following features: wherein the further stack is configured as chiplet, as a package accommodated at least partially in a cavity, as a package comprising vertically stacked semiconductor chips, and/or comprises a chiplet mounted on the further stack; wherein a central portion of the stack comprises a core, a coreless build-up, and/or a multilayer build-up.

19. A method of manufacturing a component carrier, the method comprising: providing a stack comprising at least one electrically insulating layer structure and a plurality of electrically conductive layer structures at least part of which having a first density of trace structures and a second density of connection structures; providing a further stack comprising at least one further electrically insulating layer structure and a plurality of further electrically conductive layer structures having a third density of further trace structures and a fourth density of further connection structures; applying at least one first component to the stack; embedding at least one second component in the further stack; providing the stack and the further stack so that the second density of connection structures and the fourth density of further connection structures differ from each other by not more than +/−20%; providing the stack and the further stack so that the first density of trace structures is lower than the third density of further trace structures; connecting the stack and the further stack with each other by the connection structures of the stack and by the further connection structures of the further stack; and connecting the at least one first component to the at least one second component.

20. A component carrier, comprising: a stack comprising at least one electrically insulating layer structure and a plurality of electrically conductive layer structures at least part of which having a first density of trace structures and a second density of connection structures; a further stack comprising at least one further electrically insulating layer structure and a plurality of further electrically conductive layer structures at least part of which having a third density of further trace structures and a fourth density of further connection structures; and at least one first component applied to the stack; wherein the connection structures are respectively connected to the further connection structures; wherein the first density of trace structures is lower than the third density of further trace structures; wherein the stack and the further stack are connected with each other by the connection structures of the stack and by the further connection structures of the further stack; and wherein the at least one electrically insulating layer structure comprises at least two sub-structures made of different dielectric materials.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0054] FIG. 1 illustrates a cross-sectional view of a component carrier according to an exemplary embodiment of the invention.

[0055] FIG. 2 schematically illustrates a plan view of part of the component carrier according to FIG. 1.

[0056] FIG. 3 illustrates a cross-sectional view of a component carrier according to another exemplary embodiment of the invention.

[0057] FIG. 4 illustrates a cross-sectional view of a component carrier according to still another exemplary embodiment of the invention.

[0058] FIG. 5 illustrates a cross-sectional view of a component carrier according to yet another exemplary embodiment of the invention.

[0059] FIG. 6 illustrates a cross-sectional view of a component carrier according to still another exemplary embodiment of the invention.

[0060] FIG. 7 illustrates a plan view of a component carrier according to still another exemplary embodiment of the invention.

[0061] FIG. 8 illustrates a plan view of a component carrier according to still another exemplary embodiment of the invention.

[0062] FIG. 9 illustrates a plan view of a component carrier according to still another exemplary embodiment of the invention.

[0063] FIG. 10 illustrates a plan view of a component carrier according to still another exemplary embodiment of the invention.

[0064] FIG. 11 illustrates a cross-sectional view of a portion of a component carrier according to yet another exemplary embodiment of the invention.

DETAILED DESCRIPTION OF ILLUSTRATED EMBODIMENTS

[0065] The illustrations in the drawings are schematically presented. In different drawings, similar or identical elements are provided with the same reference signs.

[0066] Before, referring to the drawings, exemplary embodiments will be described in further detail, some basic considerations will be summarized based on which exemplary embodiments of the invention have been developed.

[0067] According to an exemplary embodiment of the invention, a component carrier, such as an integrated circuit (IC) substrate or a printed circuit board (PCB), comprises a laminated layer stack (which also may be denoted as a main stack) with trace structures (in particular embodied as a wiring) of a first integration density and connection structures (such as pads and/or pillars) of a second integration density. For instance, the connection structures may be coplanar in a connection plane, such as a horizontal plane, of the stack. Beyond this, the component carrier may comprise a further layer stack (which may also be denoted as additional stack) with further trace structures (in particular, trace structure having a third density). To describe it briefly, the integration density of trace structures may be higher in the further stack compared with the stack. In other words, a wiring structure of the further stack may be denser than a wiring structure of the stack. Hence, only the connection structures may be provided matching for the stacks, whereas there may be a high freedom of design in terms of setting the density of the trace structures in accordance with the needs of a specific application. For example, the first density may be more than 20% larger than the third density (in particular, the difference between the third density and the first density divided by the third density may be at least 0.2). For assembling the component carrier, the stack and the further stack may be connected with each other by connecting the connection structures of the stack with the further connection structures of the further stack. For instance, said connection may be accomplished by soldering, sintering, an electrically conductive glue, or thermocompression bonding. By the described connection scheme, it may also be possible to electrically connect one or more first components applied to (for instance embedded in and/or surface mounted on) the stack to one or more second components being embedded in the further stack. By taking this measure, a functional connection between different components (preferably semiconductor chips) assigned to different stacks of a common PCB-type component carrier may be accomplished along a short connection path, which is advantageous in terms of signal integrity. In particular, signal losses may be reduced and signal quality may be improved. These advantageous effects can be combined with a simple manufacturability of the component carrier, since demanding high integration densities need only be provided specifically in a respective one of the stacks where functionally needed. In particular, an exemplary embodiment of the invention may provide an ultrahigh density fan-out architecture on a substrate.

[0068] Advantageously, the stack may have a bigger surface area than the further stack (and the optional other stack). That said, the further (and the optional other) stack may be totally surface mounted on stack main surface without overhang (see figures described below).

[0069] According to a preferred embodiment, the main stack may comprise a first portion embodied as a higher density stack coupling region and a second portion embodied as a lower density stack coupling region. The higher density stack coupling region may have a higher integration density than the lower density stack coupling region. The higher density stack coupling region may be connected to the further stack, whereas the lower density stack coupling region may be spaced with respect to the further stack by the higher density stack coupling region. Both the first portion and the second portion may form integral parts of the common main stack. Advantageously, the higher density stack coupling region can be used for connecting the additional or further stack. Only here a locally increased integration density is needed in order to enable a matching connection with the further stack with its higher integration density. In order to save manufacturing resources, a remaining other portion of the stack apart from a connection to the further stack may be realized as simple lower density stack coupling region. Such a manufacturing architecture may combine an excellent reliability and a high performance with a reasonable manufacturing effort.

[0070] Conventionally, a high-density layer has been manufactured separately and has then been embedded in or assembled to a layer stack. This is cumbersome. In other embodiments, an entire component carrier has been manufactured as high density stack. This involves an excessive manufacturing effort.

[0071] In order to overcome the above-mentioned and/or other shortcomings at least partially, an exemplary embodiment of the invention provides a component carrier configured as fan-out package with a split high-density connection on substrate layers.

[0072] According to an exemplary embodiment, a component carrier is provided which comprises a stack comprising a plurality of electrically conductive layer structures and at least one electrically insulating layer structure, wherein the electrically conductive layer structures comprise a lower density stack connection region and a higher density stack connection region, and a first component and a second component both being surface-mounted on the stack, wherein the first component has a component connection region having a connection density differing not more than +/−20% from a connection density of the higher density stack connection region, wherein the first component and the second component are electrically coupled with each other by the higher density stack connection region and by the component connection region. Preferably, also the second component has a component connection region having a connection density differing not more than +/−20% from a connection density of the higher density stack connection region. By connecting two surface mount device-type components with each other on a stack in the described way, it may be possible to separate routing complexity in two parts. A first part of routing complexity may be provided by the higher density stack connection region of the stack. A second part of the routing complexity may be provided by the component connection region of the respective surface mounted component. Advantageously, this may make it dispensable to provide the highest-level routing performance on each of the components and on the substrate. In contrast to this, different technologies may be matched to distribute connection resources between components and stack. As a result, a component carrier with high reliability may be obtained.

[0073] According to such an embodiment, it may be possible to mount at least one fan-out package (in particular containing one or more components) with one or more high density routing layers on an IC (integrated circuit) substrate with one or more high density routing layers to split a requested routing density between stack and components. Moreover, at least part of the involved components may be embedded to support an improved power delivery. To put it shortly, exemplary embodiment may split a high-density connection partially in a fan-out package and partially on substrate layers.

[0074] Exemplary embodiments may have advantages. In particular, it may be possible to improve or even optimize routing layers by splitting density layers. Furthermore, high density routing layers in a fan-out package may lower the demand of routing density on a substrate. Beyond this, high density routing on a fan-out region can be achieved easier and with higher yield. Advantageously, routing between components within a fan-out package can be outsourced to a mainboard. Moreover, a known good fan-out package may be provided on a known good substrate, which may further increase the yield. Furthermore, the manufacturing architecture according to exemplary embodiments of the invention may lead to a height reduction of the obtained component carrier. A high freedom of design may be achieved by the opportunity of integrating active and/or passive components, in embedding technology and/or by surface mounting. By accomplishing component-to-component coupling by matching connection structures of stack and a further stack, substrate embedded bridge dies as well as patch redistribution layers may be dispensable.

[0075] Exemplary applications of exemplary embodiments of the invention are high performance computing applications, server/cloud applications, chiplets, advanced driver assistance systems, and modules or packages involving artificial intelligence (AI).

[0076] FIG. 1 illustrates a cross-sectional view of a component carrier 100 according to an exemplary embodiment of the invention. FIG. 2 illustrates schematically a plan view of part of the component carrier 100 according to FIG. 1.

[0077] The component carrier 100 according to FIG. 1 may comprise a substantially plate-shaped IC (integrated circuit) substrate or a printed circuit board (PCB). Thus, the component carrier 100 shown in FIG. 1 may be highly compact in a vertical direction. More specifically, the component carrier 100 may comprise a stack 102 comprising electrically conductive layer structures 104 and electrically insulating layer structures 106. The electrically conductive layer structures 104 may comprise patterned metal layers (such as patterned copper foils or patterned deposited copper layers) and vertical through connections, for example copper filled vias which may be created by drilling and plating. The electrically insulating layer structures 106 may comprise a respective resin (such as a respective epoxy resin), preferably comprising reinforcing particles therein (for instance glass fibers or glass spheres). For instance, the electrically insulating layer structures 106 may be made of FR4. The electrically insulating layer structures 106 may also comprise resin layers being free of glass fibers.

[0078] Now referring to FIG. 2, a plan view of stack 102 is shown and will be explained in the following.

[0079] As can be taken from FIG. 2, part of the electrically conductive layer structures 104 has a first density of trace structures 128 and a second density of connection structures 130. The trace structures 128 may define a wiring structure for conducting electric signals. The connection structures 130 may be pads (or alternatively pillars) for accomplishing an electric connection between the stack 102 and below described further connection structures 138 of a further stack 132. For example, the connection structures 130 may be coplanar and may extend for example in the paper plane of FIG. 2. Also, the trace structures 128 may extend within a common plane, i.e., may be coplanar. It is however also possible that the connection structures 130 extend in different planes and/or that the trace structures 128 extend in different planes. One, some or all of the trace structures 128 and one, some or all of the connection structures 130 may be electrically coupled with each other. Reference sign 160 shows a rectangle corresponding to an area of stack 102. The density of the connection structures 130 may be calculated as the number of connection structures 130 of stack 102 (six in the shown example) divided by the area of rectangle 160. Correspondingly, the density of the trace structures 128 may be the number of trace structures 128 of stack 102 (six in the shown example) divided by the area of rectangle 160.

[0080] As also shown in FIG. 1 and FIG. 2, a further stack 132 is mounted on top of the stack 102. For example, further stack 132 may be a laminated layer stack with components 142 mounted thereon and being overmolded by a mold-type encapsulant 144. The components 142 being encapsulated in the encapsulant 144 may be reconnected with each other in the package-type encapsulated further stack 132. More specifically, the components 142 may be connected to each other by routing layers on the bottom surface of the wafer level package-type encapsulated further stack 132. The components 142 may be bare dies.

[0081] Further stack 132 may comprise one or more further electrically insulating layer structures shown schematically with reference sign 107 and a plurality of further electrically conductive layer structures 134. The further electrically insulating layer structures 107 can be embodied as described above for electrically insulating layer structures 106 of stack 102. Furthermore, the further electrically conductive layer structures 134 are only shown schematically in FIG. 1 and can be embodied as described above for electrically conductive layer structures 104 stack 102.

[0082] Again referring to FIG. 2, at least part of the further electrically conductive layer structures 134 has a third density of further trace structures 136 and has a fourth density of further connection structures 138. The connection structures 130 are respectively connected to the further connection structures 138. The further trace structures 136 may define a wiring structure for conducting electric signals. The further connection structures 138 may be pads (or alternatively pillars) for accomplishing an electric connection between the further stack 132 and the above-described connection structures 130 of the stack 102. For example, the further connection structures 138 may be coplanar and may extend for example in or parallel to the paper plane of FIG. 2. Also, the further trace structures 136 may extend within a common plane, i.e., may be coplanar. It is however also possible that the further connection structures 138 extend in different planes and/or that the further trace structures 136 extend in different planes. One, some, or all of the further trace structures 136 and one, some, or all of the further connection structures 138 may be electrically coupled with each other. Reference sign 162 shows a rectangle corresponding to an area of further stack 132. The density of the further connection structures 138 may be the number of further connection structures 138 of further stack 132 (six in the shown example) divided by the area of rectangle 162. Correspondingly, the density of the further trace structures 136 may be the number of further trace structures 136 of further stack 132 (eight in the shown example) divided by the area of rectangle 162.

[0083] In view of the foregoing, the second density of connection structures 130 and the fourth density of further connection structures 138 differ from each other only slightly, for instance by about 10% (please note that the drawing of FIG. 2 is only schematic for the purpose of explanation, and is not true to scale). Furthermore, the first density of trace structures 128 is lower than the third density of further trace structures 136.

[0084] Hence, the density of the connection structures 130, 138 may be substantially the same in both stacks 102, 132. Consequently, the connection pattern of the connection structures 130 and of the further connection structures 138 may match at least approximately. In other words, the connection structures 130 and the further connection structures 138 may be in alignment, as shown in FIG. 2. Consequently, each of the connection structures 130 may be connected with an assigned one of the further connection structures 138, for instance by soldering or sintering or using an adhesive glue.

[0085] In contrast to this, there is no need to have similar densities of tracing structures 128, 136. Hence, tracing structures 128, 136 may be freely designed for stack 102 and further stack 132 separately, which increases the freedom of design.

[0086] Again referring to FIG. 1, several first components 124, 140 are applied to the stack 102. More specifically, said first components 124, 140 comprise a plurality of embedded components 124 and a plurality of surface mounted components 140.

[0087] The embedded components 124 are embedded in stack 102, more specifically in a core 164 thereof. However, in other embodiments core 164 may be substituted by a dielectric multilayer. In a coreless embodiment (which may be implemented with or without embedding of components), the manufacturing process may omit a core and may start with any sacrificial carrier, for example a glass plate.

[0088] The surface mounted components 140 are surface mounted on an upper main surface of the stack 102 on which also the further stack 132 is surface mounted. For example, the embedded components 124 may be passive components, such as capacitors, integrated passive devices (IPDs), power management integrated circuits (PMICs), etc. For instance, the surface mounted components 140 may be high bandwidth memories (HBMs). Also, one or more embedded inductors are possible in an embodiment.

[0089] Moreover, a plurality of second components 142 are embedded in the further stack 132. Said second components 142 may be for example central processing units (CPUs), controller chips, etc.

[0090] Referring again to FIG. 1 and FIG. 2, the stack 102 and the further stack 132 are connected with each other by the connection structures 130 of the stack 102 and by the further connection structures 138 of the further stack 132. By this connection, also the first components 124, 140 and the second components 142 are electrically connected. This can be accomplished by the electrically conductive layer structures 104 and the further electrically conductive layer structures 134. As a result, the various components 124, 140, 142 may be functionally coupled with each other. Consequently, a common electronic functionality may be provided by the connected and interacting components 124, 140, 142.

[0091] As shown in FIG. 1, the second components 142 are encapsulated by an electrically insulating encapsulant 144, such as a mold compound. This protects the surface mounted encapsulated second components 142 against mechanical damage and provides an electric isolation. Moreover, this may prevent oxidation and/or corrosion of the metallic surface of second component 142.

[0092] Now referring specifically to stack 102, the electrically conductive layer structures 104 comprise higher density stack coupling regions 108 and a lower density stack coupling region 110 in between. The upper higher density stack coupling region 108 has the first density of trace structures 128 and has the second density of connection structures 130. According to FIG. 1, the lower density stack coupling region 110 corresponds to a central portion of the stack 102. Two higher density stack coupling regions 108 are formed on two opposing main surfaces of the central portion of the stack 102, so that the higher density stack coupling regions 108 form exterior main surfaces of stack 102. The central lower density stack coupling region 110 corresponds to a core region of the stack 102. By providing a locally high density of electrically conductive structures only at the two opposing main surfaces of the stack 102 which may function as electronic interfaces to components, boards, etc., a locally higher electronic functionality may be combined with a simple manufacturability of the component carrier 100 in view of the fact that the central portion of stack 102 can be manufactured with low effort.

[0093] In an embodiment, the two opposed higher density stack coupling regions 108 may be electrically connected by vertical connection elements or structures, preferably by plated through holes (PTH) which penetrate trough the stack thickness of stack 164.

[0094] FIG. 1 shows yet another stack 146 which is surface mounted on the stack 102 side-by-side with the further stack 132. As shown only schematically in FIG. 1, the other stack 146 comprises a plurality of other electrically conductive layer structures 148 having a fifth density of other trace structures 150 and a sixth density of other connection structures 152. To describe it briefly, the other electrically conductive layer structures 148 may be embodied in a corresponding way as the further electrically conductive layer structures 134 of the further stack 132. In particular, the other trace structures 150 may be embodied correspondingly to the further trace structures 136, and the other connection structures 152 may be embodied correspondingly to the further connection structures 138. Also, the line pitch and integration density of the other stack 146 may be similar or identical to the line pitch and integration density of the further stack 132. Correspondingly, a third component 154 (alternatively a plurality of third components) may be embedded in the other stack 146 and may be encapsulated in another encapsulant 166, such as a mold compound. The component 154 may be a bare die. Moreover, the second density of connection structures 130 in the upper higher density stack coupling region 108 and the sixth density of other connection structures 152 in the other stack 146 can differ from each other only slightly (in particular by not more than 20%). In contrast to this, the first density of trace structures 128 in the upper higher density stack coupling region 108 may be (even significantly) lower than the fifth density of other trace structures 150 in the other stack 146 (in particular may differ by more than 20%). As shown, the stack 102 and the other stack 146 are connected with each other by the connection structures 130 of the stack 102 and by the other connection structures 152 of the other stack 146, for instance in a corresponding way as described above for stack 102 and further stack 132.

[0095] By the electrically conductive layer structures 104, 134 and 148, the first components 124, 140, the second components 142 and the third component 154 may be electrically connected with each other. In a nutshell, the construction and the stack coupling of the other stack 146 may be corresponding to the construction and the stack coupling of the further stack 132, as described above in detail. For instance, the other stack 146 with the encapsulated third component 154 may be a wafer level package. Stack 146 (and its component 154) and stack 132 (and its components 142) may be electrically connected with each other by the upper higher density stack coupling region 108. At the bottom side of each of stack 146 and stack 132, a routing structure may be formed which contributes to said connection. Said routing structure may comprise, for example, one, two or three layers.

[0096] Furthermore, the upper higher density stack coupling region 108 of FIG. 1 may connect different components 142, 154 of stacks 132, 146 being surface-mounted on stack 102. Advantageously, this architecture may split high density connection resources partially in surface-mounted fan-out packages and partially on substrate layers.

[0097] As can be taken from the dimensions of the elements of the electrically conductive layer structure 104 in FIG. 1, a line pitch of the lower density stack coupling region 110 (for example 50 μm) may be larger than a line pitch of the higher density stack coupling regions 108 (for example 10 μm). Hence, although forming part of the same printed circuit board-type or integrated circuit substrate-type stack 102, different integration densities may be realized in regions 108, 110. The upper higher density stack coupling region 108 may require a high integration density for coupling high integration density components 142, 154 with each other. However, there are no demanding requirements in terms of integration density for core 164, so that the lower density of lower density stack coupling region 110 may be sufficient here. For a certain application, also the bottom-sided higher density stack coupling region 108 may require a high integration density, for instance for surface mounting further components (not shown in FIG. 1) on the bottom main surface of stack 102. Thus, a higher manufacturing effort for realizing a higher integration density needs to be provided only in those spatial portions where really needed for the function of the component carrier 100 to be manufactured. This may keep the overall manufacturing effort at a reasonable level.

[0098] A line pitch of the further electrically conductive layer structures 134 (for example 2 μm), being directly electrically coupled with the embedded second components 142, may be even less than the line pitch in the higher density stack coupling region 108. Hence, the upper higher density stack coupling region 108 may function as an interface between the typically higher line pitch of component carrier technology (as present in core 164) and the typically lower line pitch of semiconductor technology (as present in components 142, 154 being directly coupled with the further electrically conductive layer structures 134 of the further stack 132). Moreover, high density resources may be split between the further stack 132 and the upper higher density stack coupling region 108.

[0099] According to FIG. 1, all further connection structures 138 are located at a bottom main surface 118 of the further stack 132. Thus, the further connection structures 138 are all arranged at the bottom main surface 118 of the further stack 132 facing the stack 102. Consequently, an upper main surface 120 of the further stack 132 may be delimited exclusively by dielectric material of mold-type encapsulant 144. This may lead to a compact design and a high electric reliability.

[0100] Again referring to FIG. 1, each of the further stack 132, the other stack 146, and components 140 may be surface mounted on stack 102 by electrically conductive connection elements 168. Said electrically conductive connection elements 168 may be for example solder structures, such as solder balls or solder paste. Alternatively, sinter structures, electrically conductive glue and/or metallic pillars (for example copper pillars) may be used for accomplishing such an electric connection.

[0101] Concluding, the embodiment of FIG. 1 provides ultrahigh density layers on a substrate (see higher density stack coupling regions 108 of stack 102) between fan-out packages (see stacks 132, 146 with embedded components 142, 154) and/or high-bandwidth memory components (compare components 140). Furthermore, ultrahigh density layers may also be provided on a coupling interface of the fan-out packages to be interconnected. Optional embedded passive components 124 in stack 102 are shown as well. Advantageously, the described embodiment divides complexity in terms of integration density between ultrahigh density layers in the packages and local ultrahigh density layers on the board.

[0102] Preferably, there may be higher density copper portions in the first density of trace structures 128 in the area below first components 140 and/or the further stack 132 and/or the area between first components 140 and/or the further stack 132 to connect said two elements. However, there may be some portions in the first density of trace structures 128 where there is less copper loading in the stack 102 (preferably not under the components and between them). In other words, not all layers need to be made of copper, for instance none or one as indicated with an arrow 199 in FIG. 1.

[0103] For manufacturing a component carrier 100 such as the one shown in FIG. 1, it is for example possible it will carry out subtractive processes (such as chemical and/or physical etching processes using proper masks) for creating the lower density stack coupling region 110. Advantageously, additive processes (such as modified semi additive processing, mSAP, or semi additive processing, SAP) and/or a nanoimprint lithography (NIL) process may be preferably used to manufacture the higher density stack coupling region 108. Additionally and/or alternatively, a subtractive process may be used for processing the higher density stack coupling region 108, and vice versa additive processes may be used for processing the lower density stack coupling region 110. For creating a high-density stack coupling region 108, also a trenching process (for instance using a photo process, a plasma etching process, a laser process) may be used as well.

[0104] FIG. 3 illustrates a cross-sectional view of a component carrier 100 according to another exemplary embodiment of the invention.

[0105] A main difference between the embodiment of FIG. 3 and the embodiment of FIG. 1 is that, in the embodiment according to FIG. 3, other components 126 are mounted on a top main surface 120 of the further stack 132, said top main surface 120 facing away from the stack 102. In order to make this possible, some of the further connection structures 138 extend up to the top main surface 120 of the further stack 132 and are used for electrically connecting the other components 126 by additional electrically conductive connection elements 168 (such as solder structures). In the shown embodiment, the connection of the one or more other components 126 on top of the further stack 132 may be accomplished by one or more vertical through connections (such as metal pillars or metallic vias) extending vertically through the encapsulant 144 up to the other main surface 120 of the further stack 132. For example, the other components 126 may be a central processing unit (CPU) and/or a memory chip. According to FIG. 3, the further stack 132 functions as molded interposer assembled on substrate-type stack 102. The component 142 encapsulated in the package-type stack 132 may be a bridge die for accomplishing ultrahigh density connections within the package-type stack 132. Such a bridge die may include interior circuitry coupled with the other components 126 for appropriately coupling electric signals between the other components 126.

[0106] As core 164, any multilayer or any other layer boards may be used.

[0107] FIG. 4 illustrates a cross-sectional view of a component carrier 100 according to still another exemplary embodiment of the invention.

[0108] A main difference between the embodiment of FIG. 4 and the embodiment of FIG. 1 is that, in the embodiment according to FIG. 4, one of the surface mounted first components 140 is arranged in a lateral recess 156 at a lateral side of stack 102. Furthermore, the stack 102 according to FIG. 4 includes only a single bottom-sided lower density stack coupling region 110 and a single top-sided higher density stack coupling region 108. Thus, stack 102 according to FIG. 4 and therefore component carrier 100 as a whole have an asymmetrical build up.

[0109] FIG. 5 illustrates a cross-sectional view of a component carrier 100 according to yet another exemplary embodiment of the invention.

[0110] A main difference between the embodiment of FIG. 5 and the embodiment of FIG. 1 is that, in the embodiment according to FIG. 5, a lower portion of the further stack 132 is mounted in a central recess 156 of the stack 102. Consequently, the height of the component carrier 100 can be reduced. In other words, cavity 156 in the ultrahigh density layers of the upper higher density stack coupling region 108 may decrease the overall thickness of the component carrier 100.

[0111] Although the other stack 146 is omitted in the embodiment of FIG. 5, it can be present in yet another embodiment and can be assembled in cavity 156 as well.

[0112] FIG. 6 illustrates a cross-sectional view of a component carrier 100 according to still another exemplary embodiment of the invention.

[0113] A main difference between the embodiment of FIG. 6 and the embodiment of FIG. 1 is that, in the embodiment according to FIG. 6, the other stack 146 is substituted by a fan-out package 170. Fan-out package 170 may have any configuration being different from FIG. 1. Moreover, the surface mounted devices on stack 102 are in mutual alignment at upper main surfaces according to FIG. 6, thereby further reducing the thickness of the component carrier 100. This may be achieved by arranging the thicker components 140 in cavities 156.

[0114] FIG. 7, FIG. 8, FIG. 9, and FIG. 10 illustrate plan views of component carriers 100 according to exemplary embodiment of the invention configured as a chiplet. Hence, FIG. 7 to FIG. 10 shows the flexible design of the manufacturing architecture of the present disclosure. In these embodiments, components 140 may be for instance high-bandwidth memories. Furthermore, an additional controller chip component 172 may be provided as well in some of these embodiments.

[0115] FIG. 11 illustrates a cross-sectional view of a portion of a component carrier 100 according to yet another exemplary embodiment of the invention.

[0116] Descriptively speaking, FIG. 11 shows a portion of component carrier 100 according to FIG. 1 with a different dielectric configuration in a central portion. To put it shortly, core 164 of FIG. 1 has been substituted by a multilayer build-up which is also coreless according to FIG. 11. A corresponding central portion of stack 102 is formed by a sequence of stacked electrically insulating layer structures 106 (such as laminated resin or prepreg layers) in which a plurality of electrically conductive layer structures 104 (in the shown embodiment copper filled laser vias which are all tapering in the same direction) are formed. Advantageously, such kind of build-up may further homogenize and balance the stack-up. Thus, a thinner build-up can be realized having also only a little bit warpage. With such a kind of build-up structure the density can also be more relaxed, as more layers can be realized with the same thickness compared to another embodiment with a core 164. In case of an asymmetric layer count, it may be possible that at least on one layer, another insulating material can be chosen to relax the mechanical stress. This is of course strongly related to the circuitry design.

[0117] Next, a further embodiment will be explained referring in particular to the embodiments of FIG. 1 and FIG. 11 with modifications. According to such an embodiment of the invention, a component carrier 100 is provided which comprises a stack 102 comprising at least one electrically insulating layer structure 106 and a plurality of electrically conductive layer structures 104 at least part of which having a first density of trace structures 128 and a second density of connection structures 130. Moreover, a further stack 132 is provided which comprises at least one further electrically insulating layer structure 107 and a plurality of further electrically conductive layer structures 134 at least part of which having a third density of further trace structures 136 and a fourth density of further connection structures 138. Optionally, at least one first component is applied to the stack 102. The connection structures 130 are respectively connected to the further connection structures 134. The first density of trace structures 128 is lower than the third density of further trace structures 136. The stack 102 and the further stack 132 are connected with each other by the connection structures 130 of the stack 102 and by the further connection structures 138 of the further stack 132.

[0118] Advantageously, the at least one electrically insulating layer structure 106 of stack 102 comprises at least two sub-structures made of different dielectric materials. In particular, the electrically insulating material of one or more of the electrically insulating layer structures 106 of one or more higher density stack coupling regions 108 (i.e., dielectric material surrounding trace structures 128 and connection structures 130) may be different from the electrically insulating material of one or more electrically insulating layer structures 106 of the one or more lower density stack coupling region 110 (such as material of core 164 according to FIG. 1 or central electrically insulating layer structures 106 according to FIG. 11). The selection of different electrically insulating materials of electrically insulating layer structures 106 of the one or more higher density stack coupling regions 108 compared with the one or more lower density stack coupling region 110 may be performed to balance the mechanical stress or to optimize the shape of the trace structures 128, 136. In one embodiment, core 164 comprises FR4 material, whereas the electrically insulating layer structures 106 of the one or more higher density stack coupling regions 108 may be made of a build-up film. In another embodiment, the electrically insulating layer structures 106 of the one or more lower density stack coupling regions 110 may comprise a build-up film, and the electrically insulating layer structures 106 of the one or more higher density stack coupling regions 108 comprises photoimageable dielectric (PID) material or material suitable for a nano-imprint process (such as nano imprint lithography, NIL). Thus, all kind of combinations of dielectric material may be possible depending on the design of the component carrier 100. In a further embodiment, the layer stack 102 comprises organic material and is produced with PCB-based technologies, wherein the further layer stack 132 is produced with wafer-level technologies and/or comprises inorganic material (like silicon).

[0119] It should be noted that the term “comprising” does not exclude other elements or steps and the article “a” or “an” does not exclude a plurality. Also, elements described in association with different embodiments may be combined.

[0120] Implementation of the invention is not limited to the preferred embodiments shown in the figures and described above. Instead, a multiplicity of variants is possible which use the solutions shown and the principle according to the invention even in the case of fundamentally different embodiments.