INTERPOSER AND PACKAGING DEVICE ARCHITETCURE AND METHOD OF MAKING FOR INTEGRATED CIRCUITS

Abstract

An apparatus and a method of making are disclosed for an improved interposer comprises a wide bandgap semiconductor interposer such as silicon carbide (SiC) with a plurality of connectors formed in situ within the interposer for connecting the integrated circuit die to the substrate. The plurality of connectors may include carbon electrical connectors and/or optical wave guide connectors formed an angle within the interposer. The improved interposer may include a with the integrated circuit die disposed in the recess and thermally coupled to the silicon carbide (SiC) interposer for providing a heat sink for the integrated circuit die. A first and a second recess may be formed in separate surfaces of the silicon carbide (SiC) interposer enabling multiple interposers to be stacked upon one another.

Claims

1. An improved interposer for connecting an integrated circuit die or multiple dies to a substrate, comprising: a silicon carbide (SiC) interposer having a first and a second outer surface; and a plurality of connectors formed in situ within said silicon carbide (SiC) interposer for connecting the integrated circuit die to the substrate.

2. The improved interposer as set forth in claim 1, wherein plurality of connectors are carbon electrical connectors.

3. The improved interposer as set forth in claim 1, wherein plurality of connectors are optical wave guide connectors.

4. The improved interposer as set forth in claim 1, wherein plurality of connectors are optical wave guide connectors: and each of said optical wave guide connectors comprising a tunnel formed in said silicon carbide (SiC) by carbon rich tunnel walls.

5. The improved interposer as set forth in claim 1, wherein at least one of said plurality of connectors formed in situ within said silicon carbide (SiC) interposer is formed at an angle relative to said first outer surface.

6. The improved interposer as set forth in claim 1, wherein at least one of said plurality of connectors formed in situ within said silicon carbide (SiC) interposer is an angular monolithic via formed at an angle relative to said first outer surface.

7. The improved interposer as set forth in claim 1, wherein said plurality of connectors are carbon electrical connectors formed by laser irradiation of said silicon carbide (SiC) to form said carbon electrical connectors.

8. The improved interposer as set forth in claim 1, wherein plurality of connectors are optical wave guide connectors formed by laser irradiation of said silicon carbide (SiC) to form said optical wave guide.

9. The improved interposer as set forth in claim 1, including a recess formed in said first outer surface; and the integrated circuit die disposed in said recess and thermally coupled to said silicon carbide (SiC) interposer for providing a heat sink for the integrated circuit die.

10. The improved interposer as set forth in claim 1, including a recess formed in said first outer surface by a laser ablating process; and the integrated circuit die disposed in said recess and thermally coupled to said silicon carbide (SiC) interposer for providing a heat sink for the integrated circuit die.

11. An improved interposer for connecting a silicon integrated circuit die to a substrate, comprising: a wide bandgap interposer having a first and a second outer surface; a plurality of connectors formed in situ within wide bandgap interposer for connecting the silicon integrated circuit die to the substrate.

12. The improved interposer as set forth in claim 11, wherein said wide bandgap interposer is selected from the group consisting of silicon carbide (SiC), gallium nitride (GaN) aluminum nitride (AlN), synthetic diamond, glass and their respective compounds and alloyed variants engineered to enhance the quantum conversion process discussed in this invention.

13. The improved interposer as set forth in claim 11, wherein said wide bandgap interposer is a combination compounds selected from the group consisting of silicon carbide (SiC), gallium nitride (GaN) aluminum nitride (AlN), synthetic diamond, glass and their respective compounds and alloyed variants engineered to enhance the quantum conversion process discussed in this invention.

14. The improved interposer as set forth in claim 1, wherein said plurality of connectors are carbon electrical connectors formed in said wide bandgap material to form said carbon electrical connectors.

15. The improved interposer as set forth in claim 1, wherein plurality of connectors are optical wave guide connectors formed in said wide bandgap material to form said optical wave guide.

16. The improved interposer as set forth in claim 1, wherein plurality of connectors are optical wave guide connectors; and each of said optical wave guide connectors comprising a tunnel formed in said wide bandgap material by carbon rich tunnel walls.

17. The improved interposer as set forth in claim I, including a recess formed in said first outer surface; and the integrated circuit die disposed in said recess and thermally coupled to said wide bandgap material for providing a heat sink for the integrated circuit die.

18. The improved interposer as set forth in claim 1, including a recess formed in said first outer surface by a laser ablating process; and the integrated circuit die disposed in said recess and thermally coupled to said wide bandgap material for providing a heat sink for the integrated circuit die.

19. An improved packaging device for connecting an integrated circuit die to a circuit board, comprising: a silicon carbide (SiC) material having a first and a second outer surface; a recess formed in said first outer surface; the integrated circuit die disposed in said recess and thermally coupled to said silicon carbide (SiC) material for providing a heat sink for the integrated circuit die; a plurality of connectors formed in situ within said silicon carbide (SiC) material for connecting the integrated circuit die to said second outer surface; and said second outer surface of said silicon carbide (SiC) interposer being directly connected to the circuit board.

20. An improved packaging device for connecting integrated circuit dies, comprising: a silicon carbide (SiC) material having a first and a second outer surface; a recess formed in said first outer surface; a first integrated circuit die disposed in said recess and thermally coupled to said silicon carbide (SiC) martial for providing a heat sink for the integrated circuit die; a second recess formed in said second outer surface; a second integrated circuit die disposed in said second recess and thermally coupled to said silicon carbide (SiC) material for providing a heat sink for the integrated circuit and a plurality of connectors formed in situ within said silicon carbide (SiC) material for connecting said first and said second integrated circuit die to a third outer surface of said silicon carbide (SiC) interposer.

21. An improved interposer system comprising: a first silicon carbide (SiC) interposer having a first and a second outer surface with a first and a second recess defined in said first and second outer surfaces; a first and a second integrated circuit die disposed in said first and second recess and thermally coupled to said first silicon carbide (SiC) interposer for providing a heat sink for said first and second integrated circuit die; a second silicon carbide (SiC) interposer having third and a fourth outer surface with a third and a fourth recess defined in said third and a fourth outer surfaces; a third and a fourth integrated circuit die disposed in said third and a fourth recess and thermally coupled to said second silicon carbide (SiC) interposer for providing a heat sink for said integrated circuit die and said first silicon carbide (SiC) interposer being stacked upon or adjacent to said second silicon carbide (SiC) interposer for interconnecting said first through fourth integrated circuit dies.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope, and may admit to other equally effective embodiments.

[0032] FIG. 1 illustrates a laser beam from a laser contacting a silicon carbide (SiC) substrate;

[0033] FIG. 2 is a view similar to FIG. 1 illustrating a laser beam from a laser contacting a silicon carbide (SiC) substrate;

[0034] FIG. 3 is a cross-sectional view of FIG. 2;

[0035] FIG. 3A is a cross-sectional view of the state-of-the-art interconnected;

[0036] FIG. 3B is a top view of layer 2 in FIG. 3A;

[0037] FIG. 3C is a cross-sectional view of the present invention illustrating laser conversion interconnection;

[0038] FIG. 3D is a top view of FIG. 3C;

[0039] FIG. 3E illustrates different geometric shapes which the laser beam may create;

[0040] FIG. 3F illustrates a first and second laser beam with circular cross-sections;

[0041] FIG. 3G illustrates shutter elements placed within the beam optical path;

[0042] FIG. 3H illustrates a top hat laser beam with uniform intensity profile;

[0043] FIG. 3I illustrates a similar structure which may be created in silicon carbide (SiC) by direct-write a Gaussian laser beam using Galvanometer—optical elements;

[0044] FIG. 3J illustrates the resultant carbon rich conductive serpentine structure created with the laser in FIG. 3I;

[0045] FIG. 3K is an isometric view of FIG. 3 illustrating in-situ laser converted 3D monolithic vias;

[0046] FIG. 3L is a schematic of one large contact split into 3 different monolithic vias;

[0047] FIG. 4 illustrates the laser conversion processing used throughout the full thickness;

[0048] FIG. 4A illustrates the state of the art semi addictive interconnect fabrication process;

[0049] FIG. 4A1 illustrates a second state of the art semi addictive interconnect fabrication process;

[0050] FIG. 4A2 illustrates state of the art semi additive interconnect fabrication processes, a dual damascene patterning process;

[0051] FIG. 4B illustrates examples of the 3DR structures created laser thickness without drilling;

[0052] FIG. 4C illustrates a layer of silicon carbide (SiC) structure where in the laser quantum conversion patterning creates direct 3D structure throughout the thickness at variable angles;

[0053] FIG. 5 illustrates a silicon carbide (SiC) substrate prepared with machine grooves housing multiple chips/chiplets with different functionality;

[0054] FIG. 5A illustrates a first state of the an 2.5D interconnect structures, 2.5D Bridge architecture landscape;

[0055] FIG. 5A1 illustrates a second state of the art 2.5D interconnect structures, 2.5D Bridge architecture landscape;

[0056] FIG. 5A2 illustrates a state of the art 2.5D interconnect structures, 2.5D Bridge architecture landscape, TSMC silicon interposer;

[0057] FIG. 5B illustrates how the silicon carbide (SiC) interposer may be customized depending on the specification of each chip;

[0058] FIG. 6 illustrates a 3-D integration on laser inverted silicon carbide (SiC) interposer and silicon carbide (SiC) Thermo chip;

[0059] FIG. 6A illustrates an architecture option including a laser converted silicon carbide (SiC) interposer, a laser converted silicon carbide (SiC) Thermo chips and a substrate;

[0060] FIG. 6B illustrates an alternative architecture option illustrating a compact structure using machined silicon carbide (SiC) interposer for eliminating the need of silicon carbide (SiC) Thermo chips;

[0061] FIG. 6C illustrates a first simultaneous fabrication of QCIA (Quantum Conversion Integration Architecture) architecture enabling accelerated run rate an improved yield;

[0062] FIG. 6C1 illustrates a second simultaneous fabrication of QCIA (Quantum Conversion Integration Architecture) architecture enabling accelerated run rate an improved yield;

[0063] FIG. 6C2 illustrates the completed fabrication of QCIA (Quantum Conversion Integration Architecture) architecture enabling accelerated run rate an improved yield;

[0064] FIG. 6D illustrates a customized point to point connection using QCIA (Quantum Conversion Integration Architecture) architecture and laser conversion patterning or quantum conversion patterning (QCP);

[0065] FIG. 6E is an isometric view of FIG. 6 illustrating 3D integration of multiple integrated circuits chips connected at different faces of the silicon carbide (SiC) interposer;

[0066] FIG. 6F1 is a first illustration of the current state of practice in the industry for attempting to offer die stacking;

[0067] FIG. 6F2 is a second illustration of the current state of practice in the industry for attempting to offer die stacking;

[0068] FIG. 6F3 is a third illustration of the current state of practice in the industry for attempting to offer die stacking;

[0069] FIG. 6F4 is a fourth illustration of the current state of practice in the industry for attempting to offer die stacking;

[0070] FIG. 7 illustrates the option for in-situ deposition and patterning of QCIA on organic substrates;

[0071] FIG. 8 illustrates an architecture option for the improved interposer showing multiple different redistribution layers on both sides of the interposer outer surfaces;

[0072] FIG. 9 illustrates an architecture option for the improved packaging device in which the improved interposer shown in FIG. 8 is further assembled a top of a high density interconnect substrate;

[0073] FIG. 9A is an enlarged portion of FIG. 9;

[0074] FIG. 9B is an enlarged portion of FIG. 9A;

[0075] FIG. 10 illustrates a first parallel processing nature of assembling the different layers illustrated in FIG. 9;

[0076] FIG. 10A illustrates a second parallel processing nature of assembling the different layers illustrated in FIG. 9;

[0077] FIG. 11 illustrates the method of making the improved interposer with multiple redistribution layers using two different variations of the process of fabrication;

[0078] FIG. 12 is a schematic representation of a single unit of the QCIA interconnect structure; and

[0079] FIG. 13 is an illustration schematic of a substrate core structure made possible using the proposed quantum conversion patterning process and materials set.

[0080] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

DETAILED DISCUSSION

[0081] FIGS. 1-4, 4B-5, 5B-6E and 7 illustrate an improved interposer 10 for connecting an integrated circuit die 12 or multiple dies 12 to a substrate 14. The interposer 10 may comprises a silicon carbide (SiC) interposer 16. The interposer 10 has a first outer surface 20 and a second outer surface 22 and a plurality of connectors 30 formed in situ within the silicon carbide (SiC) interposer 16 for connecting the integrated circuit dies 12 to the substrate 14.

[0082] The plurality of connectors 30 may include carbon electrical connectors 32. The plurality of connectors 32 may include optical wave guide connectors 34. Each of the optical wave guide connectors 34 may comprises a tunnel 36 formed in the silicon carbide (SiC) 16 by carbon rich tunnel walls 38.

[0083] The plurality of connectors 30 formed in situ within the silicon carbide (SiC) interposer 16 may be formed at an angle 40 relative to the first outer surface 20. The plurality of connectors 30 formed in situ within the silicon carbide (SiC) interposer 16 may be an angular monolithic 42 via formed at an angle 40 relative to the first outer surface 20. The plurality of connectors 30 may include carbon electrical connectors 32 formed by laser irradiation 50 of the silicon carbide (SiC) 16 to form the carbon electrical connectors 32.

[0084] The plurality of connectors 30 may include optical wave guide connectors 34 formed by laser irradiation 50 of the silicon carbide (SiC) 16 to form the optical wave guide 34.

[0085] The subject invention may further include a recess 60 formed in the first outer surface 20 and the integrated circuit die 12 is disposed in the recess 60 and thermally coupled to the silicon carbide (SiC) interposer 16 for providing a heat sink 62 for the integrated circuit die 12. A recess 60 may be formed in the first outer surface 20 by a laser ablating process 52 and the integrated circuit die 12 is disposed in the recess 60 and thermally coupled to the silicon carbide (SiC) interposer 16 for providing a heat sink 62 for the integrated circuit die 12.

[0086] The subject invention includes an improved interposer 10 for connecting an integrated circuit dies 12 to a substrate 14 comprising a wide bandgap interposer 18 having a first outer surface 20 and a second outer surface 22. A plurality of connectors 30 are formed in situ within wide bandgap interposer 18 for connecting the integrated circuit die 12 to the substrate 14. The circuit dies 12 may include Si, SiGe, GaN, SiC, the combination of two or more of Si, SiGe, GaN, SiC or other dies.

[0087] The subject invention includes an improved interposer 10 for connecting integrated circuit dies 12 to a substrate 14 comprises a wide bandgap interposer 18 having a first outer surface 20 and a second outer surface 22 and multiple redistribution layers 70 on top of the first outer surface 20 and below the second outer surface 22. A plurality of connectors 30 are formed in situ within wide bandgap interposer 18 for connecting the silicon integrated circuit die 12 to the substrate 14. A plurality of connectors 30 are formed within the redistribution layers 70 for connecting the silicon integrated circuit die 12 to the substrate 14 and for interconnecting the redistribution layers 70 among each others across both the first outer surface 20 and the second outer surface 22 of the interposer 10.

[0088] The subject invention includes an improved interposer 10 for connecting integrated circuit dies 12 to a substrate 14 comprising a wide bandgap interposer 18 having a first outer surface 20 and a second outer surface and multiple redistribution layers 70 on top of the first outer surface 20 and below the second outer surface 22. The number, material type and dimensions of the redistribution layers 70 on both outer surfaces 20 and 22 of the interposer 10 need not to be the same. A plurality of connectors 30 are formed in situ within wide bandgap interposer 18 for connecting the silicon integrated circuit die 12 to the substrate 14. A plurality of connectors 30 are formed within the redistribution layers 70 for connecting the silicon integrated circuit die 12 to the substrate 14 and for interconnecting the redistribution layers 70 among each other's across both outer surfaces 20 and 22 of the interposer 10. The plurality of connectors 30 may take different dimensions and be constructed at multiple different angels 40.

[0089] The wide bandgap interposer 18 is selected from the group consisting of silicon carbide (SiC), gallium nitride (GaN) aluminum nitride (AlN), synthetic diamond, glass and their respective compounds and alloyed or hybrid variants engineered to enhance the quantum conversion process discussed in this invention.

[0090] The wide bandgap interposer 18 may include a combination of compounds selected from the group consisting of silicon carbide (SiC), gallium nitride (GaN) aluminum nitride (AlN) synthetic diamond, glass and their respective compounds and alloyed variants engineered to enhance the quantum conversion process discussed in this invention.

[0091] The plurality of connectors 30 may include carbon electrical connectors 32 formed in the wide bandgap material 18 to form the carbon electrical connectors 32. The plurality of connectors 30 may include optical wave guide connectors 34 formed in the wide bandgap material 18 to form the optical wave guide 34. The plurality of connectors 30 are optical wave guide connectors 34 and each of the optical wave guide connectors 34 comprise a tunnel 36 former in the wide bandgap material 18 by carbon rich tunnel walls 38.

[0092] A recess 60 may be formed in the first outer surface 20. The integrated circuit die 12 is disposed in the recess 60 and is thermally coupled to the wide bandgap material 18 for providing a heat sink 62 for the integrated circuit die 12.

[0093] A recess 60 may be formed in the first outer surface 20 by a laser ablating process 52 and the integrated circuit die 12 is disposed in the recess 60 and is thermally coupled to the wide bandgap material 18 for providing a heat sink 62 for the integrated circuit die 12.

[0094] The subject invention further includes an improved packaging device 100 for connecting integrated circuit die 12 to a circuit hoard 110 comprising a silicon carbide (SiC) material 16 having a first outer surface 20 and a second outer surface 22. A recess 60 is formed in the first outer surface 20. The integrated circuit die 12 is disposed in the recess 60 and is thermally coupled to the silicon carbide (SiC) material 16 for providing a heat sink 62 for the integrated circuit die 12. A plurality of connectors 30 are formed in situ within the silicon carbide (SiC) material 16 for connecting the integrated circuit die 12 to the second outer surface 22. The second outer surface 22 of the silicon carbide (SiC) interposer 16 is directly connected to the circuit board 110.

[0095] The subject invention further includes an improved packaging device 100 for connecting integrated circuit dies 12 comprises a silicon carbide (SiC) material 16 having a first outer surface 20 and a second outer surface 22. A recess 60 is formed in the first outer surface 20. A first integrated circuit die 112 is disposed in the recess 60 and is thermally coupled to the silicon carbide (SiC) material 16 for providing a heat sink 62 for the integrated circuit die 12. A second recess 64 is formed in the second outer surface 22. A second integrated circuit die 114 is disposed in the second recess 64 and is thermally coupled to the silicon carbide (SiC) material 16 for providing a heat sink 62 for the second integrated circuit die 114. A plurality of connectors 30 are formed in situ within the silicon carbide (SiC) material 16 for connecting the first integrated circuit die 112 and the second integrated circuit die 114 to a third outer surface 24 of the silicon carbide (SiC) interposer 16.

[0096] The subject invention further includes at improved interposer system 120 comprises a first silicon carbide (SiC) interposer 122 having a first outer surface 124 and a second outer surface 126 with a first recess 60 and a second recess 64 defined in the first outer surface 124 and second outer surface 126. A first integrated circuit die 112 and a second integrated circuit die 114 are disposed in the first recess 60 and second recess 64 and are thermally coupled to the first silicon carbide (SiC) interposer 112 for providing a heat sink 62 for the first integrated circuit die 112 and second integrated circuit die 114. A second silicon carbide (SiC) interposer 132 has third outer surface 134 and a fourth outer surface 136 with a third recess 66 and a fourth recess 68 defined in the third outer surface 134 and a fourth outer surfaces 136. A third integrated circuit die 116 and a fourth integrated circuit die 118 are disposed in the third recess 66 and a fourth recess 68 and are thermally coupled to the second silicon carbide (SiC) interposer 132 for providing a heat sink 62 for the integrated circuit die 116 and 118. The first silicon carbide (SiC) interposer 122 is stacked upon or adjacent to the second silicon carbide (SiC) interposer 132 for interconnecting the first integrated circuit dies 112, 114, 116 and 118.

[0097] The subject invention further includes an improved packaging substrate core 160 for constructing high density interconnect substrate 162 with multiple build up layers 164 on both surfaces of the core 160. The core 160 comprises a silicon carbide (SiC) material 16 having a first outer surface 20 and a second outer surface 22. The SiC material 16 has plated through boles 170 and plurality of connectors 172 formed within the core material structure 160 using both laser irradiation conversion 50 and/or laser drilling 54.

[0098] FIG. 1 illustrates a laser beam 56 from a laser contacting a silicon carbide (SiC) substrate 14 wherein the laser converts the silicon carbide (SiC) 15 for creating conductive materials 19 in otherwise insulating or semi-conductive silicon carbide (SiC) 15. FIG. 1 further illustrates a cross-section of laser conversion creating quantum-pretictic materials 19A that are conductive thermally and electrically. The position, size, configuration of the conductive structure 19 is manipulated by the laser beam 56 profile, laser processing parameters and the processing ambient.

[0099] FIG. 2 is a cross-section view similar to FIG. 1 illustrating the shape, location, size and thickness of laser converted structures 19 may be controlled by manipulating the laser beam 56 profile, laser radiation conditions and relative motion between the beam 56, the substrate 14 and the work surface 20.

[0100] FIG. 3 is a cross-sectional view of a silicon carbide (SiC) substrate 14 wherein L1-L4 represent different interconnected layers 180 created simultaneously in the substrate materials 14 (in-situ) without any metallization additives. The areas of conversion 19 are stacked above and below via structures 30 created by laser conversion. The areas of conversion 19 which are stacked above and below may represent both electrical interconnection structures 182 and thermal interconnection structures 184.

[0101] FIG. 3A is a cross-sectional view of the state-of-the-art interconnected. FIG. 3B is a top view of layer 2 in FIG. 3A illustrating a power plane 190 plated with the copper 192, conductive copper tracers 194 and microvia 196 plated and filled with copper. FIG. 3B is a top view of FIG. 3A. FIG. 3C is a cross-sectional view of the present invention illustrating laser conversion interconnection 39. FIG. 3D is a top view of FIG. 3C illustrating laser converted 3D structure 39 through the full thickness. FIG. 3D further illustrates areas of laser converted material 39 through via structure laser converted power plan 200.

[0102] FIG. 3E illustrates different geometric shapes 210 which the laser beam 56 may create. For example, the geometric shapes 210 may include circle 212, square 214, cylindrical 216, elliptical 218, rectangle 220, triangle 222 or other shapes. More specifically, the subject invention will utilize different optical elements including but not limited to lenses, diffraction gradients, diffusers, collimators and different beam shaping techniques. These different beam shaping techniques may include but not limited to diffractive shaping techniques or refractive techniques.

[0103] FIG. 3F illustrates a first laser beam 56 and second laser beam 57 with circular cross-sections 230. Additionally the energy intensity profile 236 of the beams 56 can also be controlled either independently or in conjunction with the be shape 238 to control the profile of the intensity distribution 239 within the cross-section of the beam 56. For example the laser beam 56 may include a Gaussian density distribution 232 or a top hat beam energy distribution 234.

[0104] FIG. 3G illustrates shutter elements 240 placed within the beam optical path which will be optimized and used to further convert the uniform laser beam 56 into various different patterns. For example, FIG. 3G includes a top hat laser beam energy distribution 234 with uniform intensity profile 248 throughout a square shaped cross-section 242 for producing a serpentine shaped shutters 244.

[0105] FIG. 3H illustrates a top hat laser beam 234 with uniform intensity profile 248 but shaped into the desired serpentine structure 244. Furthermore, FIG. 3H illustrates a top view of silicon carbide (SiC) interposer 10 or substrate 14 after radiation with the laser beam 56 creating carbon rich conductive serpentine structure 246.

[0106] FIG. 3I illustrates a similar structure which may be created in silicon carbide (SiC) 15 by direct-write a Gaussian laser beam using Galvanometer—optical elements 250. In this case one or more than one optical beam 56 may be used. FIG. 3J illustrates the resultant carbon rich conductive serpentine structure 246 created with the laser in FIG. 3I without any deposition or plating.

[0107] FIG. 3K illustrates an angular monolithic vias 260 and monolithic 3D 261 interconnecting to connect among all different surfaces of the interposer device 10. More specifically, FIG. 3K is an isometric view of FIG. 3 illustrating in-situ laser converted 3D monolithic vias 261, for example, angular monolithic vias 260 and monolithic 3D 261 interconnects created to connect among all different surfaces of the interposer device 10. FIG. 3L is a schematic of one large contact split 262 into 3 different monolithic vias 260, namely, layer 1 264, layer 2 266 and layer 3 268. Each monolithic via 260 may be created at different angels with different dimensions and is made to terminate at different layers.

[0108] FIG. 4 illustrates the laser conversion 39 processing used throughout the full thickness and at the surfaces of the substrate 14 to create: fan out structures 270 as shown in a-a1, b-b1 wherein a-b pitch is <<a1-b1, through via structures a-a11, surface to surface connections a-c and thermal dissipation structures d-d1. FIG. 4A and FIG. 4A1 illustrate state of the art semi addictive interconnect fabrication process 280. More specifically, FIG. 4A illustrates a damascene pattering process 282 having the substrate 290, copper 291 and dielectric 292 including steps 1, 2a, 2b, 3, 4, 5 and 6. FIG. 4A1 illustrates a semi additive pattering process 284 including providing a substrate 290, plating a thin layer of copper 291, pasting the film 294, exposuring 296, image develop 298, plating-through-hole (PTH) 300, removing the excess film 302 and etching 304. FIG. 4A2 illustrates state of the art semi additive interconnect fabrication processes 280, a dual damascene patterning process 310. More specifically, SiC deposition 312, SiO deposition 314, via pattern 316, via etch 318, metal pattern 320, metal etch 322, seed deposition 324, Cu plating 326 and Cu CMP 328.

[0109] FIG. 4B illustrates examples of the 3DR structures created laser thickness without drilling. Laser conversion 39 patterning is equivalent to quantum conversion patterning (QCP) 330. FIG. 4B includes a full thickness “T” silicon carbide (SiC) layer 332. The layer 15 could be identified by different layer thicknesses as designated as tn1, tn2, tn3 . . . tn. The laser beam 56 conditions may be adjusted such as beam profile, focus plane, intensity to enable the conversion process at the desired depth for tn1. Simultaneously or sequentially define and irradiate a second laser beam 57 to create the conversion in the subsequent layer tn2. Similarly create layers tn3 . . . tn. All steps are created without any external material plating, deposition or doping. In addition to sequential or simultaneous layers created with laser, direct surface to surface conductive 3D structures are created at different angles 40 through the whole thickness of the silicon carbide (SiC) layer 332. A first laser beam 334 creates structure at thickness tn1. A second laser beam 336 creates structure at thickness tn2. A third laser beam 338 creates structure at thickness tn3 and tn4.

[0110] FIG. 4C illustrates a layer of silicon carbide (SiC) structure “A” 332 where in the laser quantum conversion patterning 330 creates direct 3D structure 19 throughout the thickness at variable angles 40. The flexibility to define various angles 40 and to create direct 3D interconnection structures 19 allows for higher volumetric interconnection density, overhaul miniaturization, and seamless interconnection without layer to layer interfaces reducing resistive parasitic and improving performance.

[0111] FIG. 5 illustrates a wide band gap material with machined groves housing multiple chip/chip lets with different functionality. More specifically, FIG. 5 illustrates a silicon carbide (SiC) substrate 14 prepared with machine grooves 60 housing multiple chips/chiplets 340 with different functionality, such as Si chips 341, memory chip 342,, optical switch 344. The silicon carbide (SiC) substrate 14 may include optical engines 343 connected through 2.5D 19 and/or 3D integration architecture 19 using laser converted silicon carbide (SiC) 15. Additionally the substrate 14 may include optical wave guide 36 created using laser conversion connecting through silicon carbide (SiC) 15, thermal vias through silicon carbide 345, chip to chip electrical connections 346 through silicon carbide (SiC) 15, fan out structures 347 through silicon carbide (SiC) 15, and thermal connection 350 in the silicon carbide (SiC) 15 to cool the chip 340 at the sides of the groove 60.

[0112] FIG. 5A illustrates a state of the art 2.5D interconnect structures, substrate embedded 2.5D or 2.5D Bridge architecture landscape. Intel's embedded multi-die interconnect bridge (EMIB). This is an approach to do in-package high-density interconnect of heterogeneous chips. Instead of using a large silicon interposer typically found in other approaches, EMIB uses a very small bridge die with multiple routing layers. EMIB technology is an example of 2.5D packaging solution. FIG. 5A includes a HGM Die 1 360 and a GPU Die 2 362. Inters embedded multi-die interconnect bridge (EMIB) or bridge die 364 provides localized interconnects, bridge technologies, better electrical and local parasitic capacitance.

[0113] FIG. 5A1 illustrates a state of the art 2.5D interconnect structures, elevated fanout bridge 2.5D or 2.5D Bridge architecture landscape. AMD elevated fan out bridge is a variant of the original intel embedded interconnect bridge where the very small bridge die is located not inside the package substrate but rather inside the fan out layers fabricated on top of the substrate. Both the embedded interconnect bridge (FIG. 5A) and the elevated fan out bridge are very similar in functionality and differ slightly in the manufacturing process. FIG. 5A1 includes a HBM Die 1 370, a GPU Die 2 372, a mold 1 374, a EFB 376, a Cu Pillars 378, a first top build up layer 380, a substrate core 382, a second top build up layer 384. The AMD elevated bridge 386 provides scalable solutions, lithographical v defined, standard substrates, lower costs, standard flip chip process and lower complexity bumping assembly process.

[0114] FIG. 5A2 illustrates a state of the art 2.5D interconnect structures, 2.5D Bridge architecture landscape, TSMC silicon interposer. This represents the silicon interposer architecture used by multiple device makers and fabricated primarily by TSMC (Taiwan semiconductor manufacturing company). The technology in this schematic uses a large piece of silicon with through silicon vias interconnect to connect multiple different chiplets. The through silicon interconnect are fabricated using traditional damascene process. The structure represents the suite of practice in the industry and illustrate the limitation of the Si interposer architecture as a 2.5D with limited dies stacking capabilities compared with the proposed invention. FIG. 5A2 includes a first substrate 390 haying a chip 1 392, a second substrate 394 having a chip 2 396. A micro bump 398 separates the chip 1 392 and the chip 2 396 from a silicon interposer 400 having a decap 402 and a tier 1 404. FIG. 5A2 further includes a substrate 406 having a TSV 408, flip chip bumps 410 and a package substrate 412.

[0115] FIG. 5B illustrates how the silicon carbide (SiC) interposer may be customized depending on the specification of each chip. The number of layers may all be created virtually through the full thickness of the interposer. For example chip 4 426 is routed using five layers, chip 3 424 is routed using two layers and chip 1 420 requires mixed routing schemes including slant via a-a1 staggered six layers routing b-b1, die to die connection c-c1 and thermal dissipation interconnection d-d1. Chip 2 422 is illustrated with various passive elements created using laser conversion patterning or quantum conversion patterning (QCP). Also constructed within the silicon carbide (SiC) interposer as shown in FIG. 5B includes a resistor, inductor and capacitor. Depending on the specifically of each chip, the silicon carbide (SiC) interposer may be customize the # of layers. All layers are created virtually through the full thickness of the Interposer structure (in one Embodiment of the Invention).

[0116] FIG. 6 illustrates a 3-D integration on laser converted silicon carbide (SiC) interposer 430 and silicon carbide (SiC) Thermo chip(s) 432 coupled to a packing substrate 440. The converted system includes chips with various functionalities including but not limited to Si-chips 434, memory chips 436, optical chips, switch or component 438, Thermo chips 432 and various other examples.

[0117] FIG. 6A illustrates an architecture option including, a laser converted silicon carbide (SiC) interposer 450, a laser converted silicon carbide (SiC) Thermo chips 452 and a substrate 458. The HBM 454 may include a memory chip 456, the optical 460 may include an optical chip/engine 462 and the SoC 464, SoC 466 and SoC 468 may include logic chips 464, 466 and 468 respectively.

[0118] FIG. 6B illustrates an alternative architecture option illustrating a substrate 482 and a compact structure using machined silicon carbide (SiC) interposer 470 for eliminating the need of silicon carbide (SiC) Thermo chips. The HBM 472 may include a memory chip, the optical may include an optical chip/engine 474 and the SoC 476, SoC 478 and SoC 480 may include logic chips 476, 478 and 480 respectively.

[0119] FIGS. 6C, 6C1 & 6C2 illustrate simultaneous fabrication of QCIA (Quantum Conversion Integration Architecture) architecture enabling accelerated run rate an improved yield on a substrate 504. FIG. 6C illustrates that two different QCIA designs (QCIA 1 490 in FIG. 6C1 and QCIA 2 492 in FIG. 6C2) that are being combined to form the 3D stacked QCIA architecture illustrated in FIG. 6B, the process, material and approach proposed in this invention allows for the creation of the two separate parts FIG. 6C1 and FIG. 6C2 in parallel then subsequently assembly them on top of each other to produce the 3D architecture shown in FIG. 6B. This is a unique and differentiating feature the proposed invention comparison with the state of practice shown in FIGS. 5A, A1 and A2. QCIA 1 490 in FIGS. 6C1 & 6C2 includes a HBM 494, SoC1 496 and SoC2 498. QCIA 2 492 in FIGS. 6C1 & 6C2 includes an optical chip/engine 500 and SoC3 502.

[0120] FIG. 6D illustrates a customized point to point connection using QCIA (Quantum Conversion Integration Architecture) architecture and laser conversion patterning or quantum conversion patterning (QCP) which results in a power efficient and thermally enhanced integration architecture with a compact footprint design and higher-speed interconnection. All the chipless are independently cooled and thermally managed for maximizing system energy efficiency. This architecture much increases density (connection/mm^3). Due to the ability to create 3D angular monolithic vias, this architecture introduces new metric into the 3D-integration, namely, the volumetric density (number of connection/mm^3) rather than the standardized industry density (number of concentration/area). The QCIA 510 in FIG. 6D includes SoC1 512, SoC2 514, SoC3 516, an optical chip/engine 518, HBM 520 and substrate 522.

[0121] FIG. 6E is an isometric view of FIG. 6 illustrating 3D integration of multiple integrated circuits chips connected at different faces of the silicon carbide (SiC) interposer. Microchip 1 530 is positioned inside a recess created to have the microchip 1 530 at one side of the interposer 10. Microchip 2 532 is positioned inside a recess created to have the microchip 2 532 at another side of the interposer 10. Microchip 3 534 is positioned inside a recess created to have the microchip 3 534 at another side of the interposer 10. A first angular monoloithic vias 540 connects the microchip 1 530 with the microchip 2 532. A second angular monoloithic vias 542 connects the microchip 1 530 with the microchip 3 534. A third angular monoloithic vias 544 connects microchip 2 532 with microchip 3 534.

[0122] FIGS. 6F1, 6F2, 6F3 and 6F4 illustrate state of the art 3D interconnect structures. FIGS. 6F1, 6F2, 6F3 and 6F4 are a summary illustrating the current state of practice in the industry for attempting to offer die stacking. All 4 different architectures illustrated in the schematics have the same limitation of no more than two die stacks. This is a fundamental differentiation with the proposed invention. Using the material and proposed process in our invention, we are able to stack more than 3 dies and offer the thermal and power delivery solution to support that high die stack designs.

[0123] FIG. 7 illustrates the option for in-situ deposition and patterning of QCIA on organic substrates. More specifically, FIG. 7 illustrates the direct formations of redistribution layers on packaging substrate for heterogeneous integrated applications. Each layer is deposited then laser converted to form the pattern before the substrate layer is deposited. The steps in FIG. 7 include providing a packing substrate 550, low temp deposited material (SiC) or carbine like diamond 552 onto the packing substrate 550, laser conversion putting of the deposited layer 554, subsequent layer deposition 556, subsequent layer is laser converted 558, third layer is deposited 560, third layer is converted completing the overall redistribution or fan-out structure 562.

[0124] FIG. 8 illustrates an architecture option for the improved interposer showing multiple different redistribution layers on both sides of the interposer outer surfaces. FIG. 8. Illustrates the option for formation of multiple redistribution layers of varied number, dimensions functionality and materials type on both sides of the interposer outer surface. More specifically, the interposer 10 in FIG. 8 includes a IC-chiplets 570, chiplets routing/redistribution layer 572, a QCI interposer 574, fan out and redistribution layer 576, QCI interposer fan-out pitch 578.

[0125] FIG. 9 illustrates an architecture option for the improved packaging device in which the improved interposer shown in FIG. 8 is further assembled a top of a high density interconnect substrate. The high-density interconnect illustrated in FIG. 9 is comprised of multiple build up layers formed on both sides of the outer surfaces of a SiC core structure formed with the laser irradiation conversion process and laser drilling. The QCIA performance is optimized for energy efficient high-performance computing. FIG. 9 includes an optical Xvr 580, XPU2 582, DRAM 584, OCIA interconnect Structure 586, Si Ivr II 588, XPU1 590, second DRAM 592, BIST/control 594, Power FET 1 596, QCIA substrate 598, Si IVR I 600 and System PBC 602.

[0126] FIG. 9A and 9B are a detailed schematic showing a higher magnification of the QCIA interconnect structure 586 shown in FIG. 9. In this illustration, the QCIA interconnect structure 586 consists of a SiC interposer 604 with QCP interconnects 606 featuring one die to die interconnect layer on top 608 and five (5) fan out build up layers on the bottom 610. FIGS. 10 and 10A illustrate the parallel processing nature of assembling the different layers illustrated in FIG. 9.

[0127] FIG. 11 illustrates the method of making the improved interposer with multiple redistribution layers using two different variations of the process of fabrication. In one embodiment the fabrication process uses SiC in a wafer format 620 in another embodiment the fabrication process uses SiC in square quarter panel size format 622. FIG. 11 illustrates the detailed process of transforming both the wafer format SiC 620 and the quarter panel format SiC 622 into full panel size making them compatible with widely used panel manufacturing processes for high density interconnect substrate fabrication infrastructure.

[0128] FIG. 12 is a schematic representation of a single unit of the QCIA interconnect structure 630 including a hybrid glass SiC interposer featuring 3 chiplets 632 connected side by side on top of the QCIA interconnect structure 630 with one die to die interconnect layer on top of the SiC interposer and five (5) fan out layers on the bottom side. The QCIA interconnect structure 630 further includes a RDL layer 640 on top of both Glass and SiC hybrid interposer and TGV through glass via 642.

[0129] FIG. 13 is an illustration schematic of a substrate core structure made possible using the proposed quantum conversion patterning process and materials set. The structure of the core module features SiC with embedded power, active and passive device elements. The QC-Core have interconnect through hole structures created using the quantum conversion patterning process. The combined choice of the base material (SiC, Si3N4, AlN or a hybrid structure of all three) plus the highly conductive laser converted structure make the QC-Core module a unique power delivery and thermal management circuit element that could function on its own as a power package device or could subsequently be integrated into organic packaging device or Silicon based device for further system level integration. More specifically, the QC-Core 650 structure may include a control device 652, a power device 654, a polymer material layer 656, a QCIA substrate core material 658 such as SiC, Si3N4 or hybrid, a OCIA interconnect 660 created in situ within SiC or Si3N4, a passive 662 and copper metallization 664.

[0130] The subject invention further incorporates the following:

[0131] A microelectronic interposer with double sided redistribution layers used for multiple chips interconnection and fan out of electronic circuitries (QCIA interposer).

[0132] Stackable and reconfigurable microelectronic system featuring the QCIA interposer and high density interconnect substrates manufactured using the proposed invention (a 3D heterogeneous integration architecture built using the proposed invention).

[0133] Substrate with power delivery and thermal management modules fully integrated into the substrate structure and fabricated using the QCP process eliminating the need for electroless metallization.

[0134] Thermal Chip: a wide bandgap material such as SiC with thermal conduction pathways in-situ fabricated through the thickness, at the surface and across the edges of the Chip to conduct heat and dissipate the thermal energy generated at multiple levels of the system.

[0135] Power delivery modules such as power converters built in a wide bandgap materials such as SiC using the Quantum conversion pattering process and placed at multiple stack locations in the microelectronic system.

[0136] Thermal management Modules such as power converters built in a wide bandgap materials such as SiC using the Quantum conversion pattering process and placed at multiple stack locations in the microelectronic system.

[0137] A substrate core device where SiC or other wide bandgap material is used and patterned using laser conversion irradiation and/or laser drilling to form the interconnect within the core structure.

[0138] A substrate core device where SiC or other wide bandgap material is used and patterned using laser conversion irradiation and/or laser drilling to form the interconnect within the core structure. The core device is made to incorporate the power delivery modules and the thermal management modules.

[0139] Example of the laser processing parameters to induce the quantum conversion patterning Single crystal 4H-SiC wafer with polished ˜00011-Si face is used in this study for fabricating the nanoribbons/SiC structure. The wafer has a low-doped (531015 cm23 625%), n-type, 10 mm ˜610%! thick epilayer grown onaxis @(0001)60.25°# over a 50.8 mm diameter 4H-SiC substrate. To fabricate the C-rich SiC nanoribbon, laser irradiation experiments were conducted using a Q-switched Nd:YAG laser of wavelength 1064 nm. 1 mm wide and 7 mm long region was irradiated with laser pulses of repetition rate f535 kHz, pulse duration ˜on-time! t P5260 ns, pulse energy EP50.6 mJ/pulse, laser beam diameter D51 mm, and laser scanning speed V55 mm/s. This region was irradiated three times in a nitrogen ambient ˜1 atm! before taking the sample out of the processing chamber. The incident fluence of a single pulse, which is given by fP5Ep/Ai, where Ai is the irradiated area given by Ai5(pd2/4)1DVt P for a circular spot, is found to be 76.4 mJ/cm2 and the pulse intensity, which is given by I p5(fP /t P), is 293.3 kW/cm2. However, a fraction of this energy is absorbed by the work piece because the transmittance and reflectance of the 4H-SiC sample used in this study were measured to be 0.4 and 0.15, respectively, at 1064 nm wavelength. 14 Focused ion beam ˜FIB! milling was used to prepare 5 mm38 mm31200 Å section of the laser-irradiated 4H-SiC wafer for microscopic studies. High-resolution transmission electron microscope ˜HRTEM!, Techni F 30, equipped with a windowless Link energy dispersive spectroscopy ˜EDS! analyzer was used to study the laser-fabricated nanostructure and to obtain selected area electron diffraction ˜SAED! patterns for different regions in the laser-treated wafer.

[0140] Additional experimentation was also conducted using different laser wavelength to create conversion sin the SiC materials these wavelength examples are 193 nm, 532 nm, 532 nm wavelength laser with femto second pulse width.

[0141] Example of commercially available build up polymeric film used for fabricating the redistribution and/or the build up layer used on top and below the QCIA Interposer. The most commonly used microfilm materials for build up circuit fabrication in advanced packaging is Ajinomato Build up Film (https://www.ajinomoto.com/innovation/action/buildupfilm). In fact, Ajinomoto Build-up Film (ABF) can be found at the heart of most of the world's personal computers, where it provides electrical insulation of complex circuit substrates for high-performance central processing units (CPUs). These films comes in multiple different versions across a wide array of electronic materials properties, thermo mechanical properties and geometrical dimensions (i.e., film thickness, film thickness variation, width)

[0142] The table below offer some example of the available varieties of these materials:

TABLE-US-00001 Ajinomoto Build-Up Film ®(ABF) Variety Features GX-92 Standard GX-T31 Low surface roughness, Low CTE GZ-41 Low surface roughness, Low CTE, High Tg GL-102 Low surface roughness, Low dielectric loss tangent, Low CTE, High Tg

[0143] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

TABLE-US-00002 Comparison between the proposed invention and the state of the art State of the Art Proposed Invention Build up substrate 3 D monolithic substrate packaging process packaging process Semi additive patterning process Quantum conversion Subtractive patterning process patterning process Damascene and double damascene patterning process Additive Manufacturing 3 D in-situ Manufacturing 3 D in-situ interconnect manufacturing In-situ 3 D interconnect fabrication Stacked via interconnect Angular monolithic via Cu metallization conductor lines C3-interconnect Conductive carbon connections Converted-Carbon Connection

TABLE-US-00003 The subject invention may be described by a complex 2 × 3 × 5 matrix: Connection Type Created by quantum conversion Device Type patterning approach Integration scheme Interposer Package Electric Optical Hybrid 2 D X X X X X 2.5 D — X X X X 3 D X — X X X 3 D w/inter- X X X X X leaved SiC Combined X — X X X 2 D, 2.5 D and 3 D (SiCcube interconnect depicted in FIG. 6d)