VECTOR SYNTHESIS PHASE SHIFTER AND VECTOR SYNTHESIS PHASE SHIFTING METHOD

Abstract

A vector sum phase shifter and a vector sum phase shifting method are disclosed. The method may include: passing a first reference input excitation, after being adjusted by a first current source, through a first vector direction control circuit for vector direction determination and then to a first gate width control circuit for adjustment to generate a first output signal; passing a second reference input excitation, after being adjusted by a second current source, through a second vector direction control circuit for vector direction determination and then to a second gate width control circuit for adjustment to generate a second output signal; and vectorially summing the first output signal and the second output signal.

Claims

1. A vector sum phase shifter, comprising: a first vector sum branch with an input end connected to a first reference input excitation; a second vector sum branch with an input end connected to a second reference input excitation; and a summer to which both an output end of the first vector sum branch and an output end of the second vector sum branch are connected; wherein the first vector sum branch comprises: a first current source, a first vector direction control circuit, and a first gate width control circuit; wherein the first reference input excitation, after being adjusted by the first current source, passes through the first vector direction control circuit for vector direction determination and is output to the first gate width control circuit, and then to the summer after being adjusted by the first gate width control circuit; wherein the second vector sum branch comprises: a second current source, a second vector direction control circuit, and a second gate width control circuit; wherein the second reference input excitation, after being adjusted by the second current source, passes through the second vector direction control circuit for vector direction determination and is output to the second gate width control circuit and then to the summer after being adjusted by the second gate width control circuit; and wherein the summer vectorially sums an output signal from the first vector sum branch and an output signal from the second vector sum branch.

2. The phase shifter of claim 1, wherein the first vector direction control circuit comprises two control switches, only one of which is closed when the phase shifter works; and the second vector direction control circuit comprises two control switches, only one of which is closed when the phase shifter works.

3. The phase shifter of claim 1, wherein the first reference input excitation is orthogonal to the second reference input excitation.

4. The phase shifter of claim 1, wherein the first current source comprises a plurality of current output circuits with same or different current values, and at least one of the plurality of current output circuits is used as a current source to output a current; and the second current source comprises a plurality of current output circuits with same or different current values, and at least one of the plurality of current output circuits is used as a current source to output a current.

5. The phase shifter of claim 1, wherein the first gate width control circuit comprises a first transistor array comprising two MOS transistor arrays arranged opposite each other; and the second gate width control circuit comprises a second transistor array comprising two MOS transistor arrays arranged opposite each other.

6. The phase shifter of claim 5, wherein each of the MOS transistor arrays is a combination of MOS transistors based on a Gilbert structure.

7. The phase shifter of claim 5, wherein, the MOS transistor arrays each comprises a plurality of MOS transistor groups connected in series, each MOS transistor group comprises three P-type MOS transistors comprising a first P-type MOS transistor, a second P-type MOS transistor, and a third P-type MOS transistor; and in each MOS transistor group, a source of the first P-type MOS transistor, a source of the second P-type MOS transistor, and a drain of the third P-type MOS transistor are connected together, a drain of the first P-type MOS transistor and drains of the first P-type MOS transistors of other MOS transistor groups are connected together, a drain of the second P-type MOS transistor and drains of the second P-type MOS transistors of other MOS transistor groups are connected together, a source of the third P-type MOS transistor and sources of the third P-type MOS transistors of other MOS transistor groups are connected together, and gates of the first P-type MOS transistor, the second P-type MOS transistor, and the third P-type MOS transistor in each MOS transistor group are connected together.

8. A vector sum phase shifting method, comprising: passing a first reference input excitation, after being adjusted by a first current source, through a first vector direction control circuit for vector direction determination and then to a first gate width control circuit for adjustment to generate a first output signal; passing a second reference input excitation, after being adjusted by a second current source, through a second vector direction control circuit for vector direction determination and then to a second gate width control circuit for adjustment to generate a second output signal; and vectorially summing the first output signal and the second output signal.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0012] FIG. 1 is a schematic diagram of a typical phased array system;

[0013] FIG. 2 is a schematic diagram of a vector sum phase shifter;

[0014] FIG. 3 is a schematic diagram of the structure of a vector sum phase shifter according to an embodiment;

[0015] FIG. 4 is a schematic diagram of a circuit of a vector sum phase shifter according to an embodiment;

[0016] FIG. 5 is a schematic diagram of a circuit of a vector sum phase shifter according to an embodiment;

[0017] FIG. 6 is a schematic diagram of a circuit of a current source according to an embodiment;

[0018] FIG. 7 is a schematic diagram of a circuit of a transistor array according to an embodiment; and

[0019] FIG. 8 is a flowchart of a vector sum phase shifting method according to an embodiment.

DETAILED DESCRIPTION

[0020] The technical schemes of the present disclosure will be described hereinafter with reference to the drawings and embodiments.

[0021] In an embodiment, if there is no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other, and all the combinations fall within the scope of the present disclosure. Moreover, although a logical order is shown in the flowcharts, the steps shown or described may be performed, in some cases, in a different order than shown or described herein.

[0022] As shown in FIG. 3, this embodiment provides a vector sum phase shifter, including: a first vector sum branch with an input end connected to a first reference input excitation, a second vector sum branch with an input end connected to a second reference input excitation, and a summer to which an output end of the first vector sum branch and an output end of the second vector sum branch are connected;

[0023] the first vector sum branch including: a first current source, a first vector direction control circuit, and a first gate width control circuit;

[0024] the first reference input excitation, after being adjusted by the first current source, passing through the first vector direction control circuit for vector direction determination, and then being output to the first gate width control circuit and then to the summer after being adjusted by the first gate width control circuit;

[0025] the second vector sum branch including: a second current source, a second vector direction control circuit, and a second gate width control circuit;

[0026] the second reference input excitation, after being adjusted by the second current source, passing through the second vector direction control circuit for vector direction determination, and then being output to the second gate width control circuit and then to the summer after being adjusted by the second gate width control circuit; and

[0027] the summer vectorially summing an output signal from the first vector sum branch and an output signal from the second vector sum branch.

[0028] A schematic diagram of a circuit according to an embodiment of the present disclosure is shown in FIG. 4. A first reference input excitation VinI and a second reference input excitation VinQ pass through a first current source and a second current source, respectively, for control of the gains Ai and Aj of the first reference input excitation VinI and the second reference input excitation VinQ, respectively, then through a first vector direction control circuit and a second vector direction control circuit for selection of directions of the excitations, and then through a first gate width control circuit and a second gate width control circuit for control of the gains Ai and Aj of the first reference input excitation VinI and the second reference input excitation VinQ by changing gate width of transistors, and then enter a summer through two vector sum branches to form a final output signal.

[0029] According to the disclosure, the current source and amplifying transistor realize a two-stage gain control function, and the control word of the current source can be correspondingly reduced by using an M-bit control word of the amplifying transistor, so as to reduce the power consumption with the gain unchanged. For example, if the M-bit control word of the amplifying transistor is doubled, the control word of the current source can be reduced to ½ of the original, thus ensuring the gain unchanged. According to the disclosure, by adding one stage of an amplifying transistor with the adjustable M-bit control word, low power consumption can be achieved with the same gain. While ensuring that the gain of the phase shifter is kept unchanged, the power consumption of the vector summer is greatly reduced, the phase shift value also becomes less sensitive to circuit mismatch, and thus the phase shift accuracy of the phase shifter is improved.

[0030] According to an embodiment of the present disclosure, the first vector direction control circuit includes two control switches, only one of which is closed when the phase shifter works; and the second vector direction control circuit includes two control switches, only one of which is closed when the phase shifter works.

[0031] According to an embodiment of the present disclosure, the first reference input excitation is orthogonal to the second reference input excitation.

[0032] In the related art, the vector summer in the active phase shifter is a major contributing factor to the power consumption of an active phase shifter. The mainstream vector summer architecture is shown in FIG. 5. The circuit structure is composed of two Gilbert cells and some control switches.

[0033] The small signal voltage gain of this circuit is:

[00002]$\begin{array}{c}{A}_v=\left(g_{mI}+g_{mQ}\right)R\\ =R\sqrt{\mu C_{ox}\frac{W_2}{L_2}}*\sqrt{\left(I_{\mathrm{SSI}}+I_{SQ}\right)}\end{array}$

where g.sub.ml and g.sub.mQ represent the small signal current gains of I and Q channels, respectively, and R represents the equivalent load of the circuit; μ represents the carrier mobility, C.sub.oX represents the gate oxide thickness of the MOS transistor, W2 represents the gate width, L.sub.2 represents the gate length, I.sub.SSI represents the total current of the I channel, and I.sub.SSQ represents the total current of the Q channel, so the phase of the output signal is:

[00003]$\varphi =\arctan \left(\frac{A_{vQ}}{A_{\mathrm{vI}}}\right)=\arctan \left(\frac{g_{mQ}}{g_{\mathrm{mI}}}\right)=\arctan \left(\sqrt{\frac{I_{SSQ}}{I_{\mathrm{SSI}}}}\right)$

where A.sub.VQ represents the voltage gain of the Q channel and A.sub.VI represents the voltage gain of the I channel.

[0034] In the design of a signal summer, as long as the sum of the gains of the Gilbert cells of the two channels is a fixed value, the gain of the output signal can be kept unchanged with different phases, and the root mean square error of the gain of the circuit can be reduced, and outputs with different phases are realized by changing the ratio of the amplitudes of signals from the two channels.

[0035] For the Gilbert cell circuit driven by a tail current source as shown in FIG. 5, the gain of the output signal can be kept constant as long as I.sub.SSI+I.sub.SSQ=C is set to a fixed value, and the phase of the output signal can be changed by adjusting the ratio of I.sub.SSI to I.sub.SSQ.

[0036] Here, C is also the total working current of the entire vector summer. A large working current of the vector summer causes the entire phase shifter to consume a large amount of power. Because the number of channels in a phased array system is usually large, a large number of phase shifters would be required accordingly. Large power consumption of phase shifters will inevitably lead to a large increase in power consumption of the phased array.

[0037] A vector summer in an active phase shifter usually ensures a constant gain of the phase shifter by a constant total current of I and Q channels. There are two main problems in this method:

[0038] 1. The difference between the maximum current and the minimum current of the two branches is relatively large, and it is difficult to achieve good matching in the circuit due to the large current difference, which leads to the decrease in phase shift accuracy.

[0039] 2. The linearity requirement of the active phase shifter usually limits the minimum current value of the branch. For an N-bit phase shifter, the ratio of the maximum current value to the minimum current value is

[00004]$\frac{1}{{\tan }^2\left(\frac{2^{*}\pi }{2^N}\right)},$

which also leads to the relatively large working current of the vector summer, and the larger the bit of the phase shifter N is, the greater the power consumption would be.

[0040] The embodiments of the present disclosure combine two approaches, i.e. the current control and the transistor gate width control, to ensure that the gain of the phase shifter is kept unchanged, greatly reduce the power consumption of the vector summer, and also reduces the difference between the maximum current and the minimum current of branches so that the phase shift value become less sensitive to circuit mismatch, thus improving the phase shift accuracy of the phase shifter.

[0041] According to an embodiment of the present disclosure, the first current source includes a plurality of current output circuits with the same or different current values, one or more of the plurality of current output circuits being used as a current source to output a current; and the second current source includes a plurality of current output circuits with the same or different current values, one or more of the plurality of current output circuits being used as a current source to output a current.

[0042] As shown in FIG. 6, the first current source includes a plurality of current output circuits with the same or different current values, one or more of the plurality of current output circuits being used as a current source to output a current; and the second current source includes a plurality of current output circuits with the same or different current values, one or more of the plurality of current output circuits being used as a current source to output a current.

[0043] The first gate width control circuit includes a first transistor array including two MOS transistor arrays arranged opposite each other, and the second gate width control circuit includes a second transistor array including two MOS transistor arrays arranged opposite each other.

[0044] As shown in FIG. 7, according to an embodiment of the present disclosure, the MOS transistor array is a combination of MOS transistors based on a Gilbert structure and includes a plurality of MOS transistor arrays connected in series, each MOS transistor array including three P-type MOS transistors.

[0045] In each MOS transistor group, a source of a first P-type MOS transistor, a source of a second P-type MOS transistor, and a drain of a third P-type MOS transistor are connected together, a drain of the first P-type MOS transistor and drains of first P-type MOS transistors of other groups are connected together, a drain of the second P-type MOS transistor and drains of second P-type MOS transistors of other groups are connected together, a source of the third P-type MOS transistor and sources of third P-type MOS transistors of other groups are connected together, and gates of the plurality of MOS transistors are connected together.

[0046] In an embodiment, gates of the first P-type MOS transistor, the second P-type MOS transistor, and the third P-type MOS transistor in each group are connected together.

[0047] As shown in FIG. 8, an embodiment of the present disclosure also provides a vector sum phase shifting method, including the following steps.

[0048] At S1010, a first reference input excitation, after being adjusted by a first current source, is passed through a first vector direction control circuit for vector direction determination and then to a first gate width control circuit for adjustment to generate a first output signal.

[0049] At S1020, a second reference input excitation, after being adjusted by a second current source, is passed through a second vector direction control circuit for vector direction determination and then to a second gate width control circuit for adjustment to generate a second output signal.

[0050] At S1030, the first output signal and the second output signal are vectorially summed.

Example Embodiment I

[0051] This embodiment explains the working process of a vector sum phase shifter as follows:

[0052] As shown in FIG. 4, according to the present disclosure, not only the current source units of the I channel and the Q channel are divided into binary arrays, but also the amplifying transistors are divided into M-bit binary arrays. The power consumption of the entire vector summer can be reduced to

[00005]$\frac{1}{2^{M-1}}$

of the original by the following control method:

[0053] Given that the I channel has a current of I.sub.1 and an amplifying transistor M.sub.1 with a width-to-length ratio of β.sub.1, the Q channel has a current of I.sub.2 and an amplifying transistor M.sub.2 with a width-to-length ratio of β.sub.2, and I.sub.1≥I.sub.2, I.sub.1+I.sub.2=C, then:

[00006]$\{\begin{array}{c}\frac{C}{2}\le I_1\le C\\ 0\le I_2\le \frac{C}{2}\end{array}\hspace{1em}$

[0054] 1. The current I.sub.1 is changed to

[00007]$I_1^a=\frac{I_1}{2^M},$

and the gate width of the transistor M.sub.1 is multiplied by 2.sup.M, that is, the width-to-length ratio is changed to β.sub.1.sup.a=β.sub.1*2.sup.M, then, ignoring the channel effect, the transconductance of the transistor M.sub.1 after adjustment is expressed as:

[00008]$\begin{array}{c}{g}_{m1}^a=\sqrt{2^{*}{K}^{*}{\beta }_1^a*I_1^a}\\ =\sqrt{2^{*}{K}^{*}{\beta }_1*2^M*\frac{I_1}{2^M}}\\ =g_{m1}\end{array}$

[0055] where K represents μ*C.sub.ox.

[0056] It can be seen that the transconductance of the transistor M.sub.1 remains unchanged after adjustment, but the I channel current becomes

[00009]$\frac{1}{2^M}$

of the previous; and as

[00010]$\frac{C}{2}\le I_1\le C,$

the I channel current after adjustment is no greater than

[00011]$\frac{C}{2^M}.$

[0057] 2. The current of the Q channel is adjusted based on conditions as follows:

[00012]$\{\begin{array}{c}{I}_2^a=I_2;{\beta }_2^a={\beta }_2\left(0\le I_2<\frac{C}{2^M}\right)\\ I_2^a=\frac{I_2}{2};{\beta }_2^a=2*{\beta }_2\left(\frac{C}{2^M}\le I_2<\frac{C}{2^{M-1}}\right)\\ I_2^a=\frac{I_2}{4};{\beta }_2^a=4*{\beta }_2\left(\frac{C}{2^{M-1}}\le I_2<\frac{C}{2^{M-2}}\right)\\ \mathrm{.Math.}\\ I_2^a=\frac{I_2}{2^{M-1}};{\beta }_2^a=2^{M-1}*{\beta }_2\left(\frac{C}{2^2}\le I_2\le \frac{C}{2}\right)\end{array}\hspace{1em}$

[0058] It can be seen that the transconductance of transistor M.sub.2 remains unchanged after adjustment, but the current of the Q channel is no greater than

[00013]$\frac{C}{2^M}$

after adjustment.

[0059] 3. After the adjustment in steps 1 and 2, while keeping g.sub.m1 and g.sub.m2 unchanged, the total current of the circuit is:

[00014]$C_{tot}=I_1^a+I_2^a\le \frac{c}{2^M}+\frac{c}{2^M}=\frac{c}{2^{M-1}}$

[0060] 4. If I1<I2, the adjustment may be made accordingly in the same way, and it can be seen that the power consumption of the entire vector summer is reduced to

[00015]$\frac{1}{2^{M-1}}$

of the previous power consumption after adjustment. For an N-bit phase shifter, the ratio of maximum current to minimum current decreases from

[00016]$\frac{1}{{\tan }^2\left(\frac{2*\pi }{2^N}\right)}\mathrm{to}\frac{1}{2^M*{\tan }^2\left(\frac{2^{*}\pi }{2^N}\right)};$

and after adjustment, the matching of the circuit has also been effectively improved.

Example Embodiment II

[0061] Hereinafter, an example where M=2 and N=6 is taken to describe an implementation of the present disclosure. In an embodiment, M can be any integer value between 0 and N, which can be adjusted as required, assuming that the total current at the vector summer before adjustment is C.

[0062] The structure of a transistor M.sub.1 is shown in FIG. 7. The corresponding relationship between phase shift value and gate width, power consumption, and total current according to a solution of the related art (before adjustment) is shown in Table 1. The corresponding relationship between phase shift value, gate width, power consumption, and total current according to the scheme of this embodiment (after adjustment) is shown in Table 2. The comparison between after-adjustment and before-adjustment is shown in Table 3. According to Table 3, the optimization of power consumption is obvious, and the ratio of maximum current to minimum current is greatly reduced, which reduces the requirement for circuit matching. In addition, the larger M is, the more the power consumption of the vector summer decreases, and accordingly, the smaller the ratio of maximum current to minimum current is.

TABLE-US-00001 TABLE 1 I Q Phase I Q channel channel shift channel channel gate gate Total current at value current current width width vector summer 0 C 0 β.sub.1 β.sub.2 C 5.625 0.9904 C 0.0096 C β.sub.1 β.sub.2 C 11.25 0.9619 C 0.0381 C β.sub.1 β.sub.2 C 16.875 0.9157 C 0.0843 C β.sub.1 β.sub.2 C 22.5 0.8536 C 0.1464 C β.sub.1 β.sub.2 C 28.125 0.7778 C 0.2222 C β.sub.1 β.sub.2 C 33.75 0.6913 C 0.3087 C β.sub.1 β.sub.2 C 39.375 0.5975 C 0.4025 C β.sub.1 β.sub.2 C 45   0.5 C   0.5 C β.sub.1 β.sub.2 C 50.625 0.4025 C 0.5975 C β.sub.1 β.sub.2 C 56.25 0.3087 C 0.6913 C β.sub.1 β.sub.2 C 61.875 0.2222 C 0.7778 C β.sub.1 β.sub.2 C 67.5 0.1464 C 0.8536 C β.sub.1 β.sub.2 C 73.125 0.0843 C 0.9157 C β.sub.1 β.sub.2 C 78.75 0.0381 C 0.9619 C β.sub.1 β.sub.2 C 84.375 0.0096 C 0.9904 C β.sub.1 β.sub.2 C 90 0 C β.sub.1 β.sub.2 C

TABLE-US-00002 TABLE 2 I Q Phase I Q channel channel shift channel channel gate gate Total current at value current current width width vector summer 0  0.25 C 0 4 β.sub.1 β.sub.2  0.25 C 5.625 0.2476 C 0.0096 C 4 β.sub.1 β.sub.2 0.2572 C 11.25 0.2405 C 0.0381 C 4 β.sub.1 β.sub.2 0.2786 C 16.875 0.2289 C 0.0843 C 4 β.sub.1 β.sub.2 0.3132 C 22.5 0.2134 C 0.1464 C 4 β.sub.1 β.sub.2 0.3598 C 28.125 0.1945 C 0.2222 C 4 β.sub.1 β.sub.2 0.4167 C 33.75 0.1728 C 0.1544 C 4 β.sub.1 2 β.sub.2 0.3272 C 39.375 0.1494 C 0.2013 C 4 β.sub.1 2 β.sub.2 0.3507 C 45  0.125 C  0.25 C 4 β.sub.1 2 β.sub.2  0.375 C 50.625 0.2013 C 0.1494 C 2 β.sub.1 4 β.sub.2 0.3507 C 56.25 0.1544 C 0.1728 C 2 β.sub.1 4 β.sub.2 0.3272 C 61.875 0.2222 C 0.1945 C β.sub.1 4 β.sub.2 0.4167 C 67.5 0.1464 C 0.2134 C β.sub.1 4 β.sub.2 0.3598 C 73.125 0.0843 C 0.2289 C β.sub.1 4 β.sub.2 0.3132 C 78.75 0.0381 C 0.2405 C β.sub.1 4 β.sub.2 0.2786 C 84.375 0.0096 C 0.2476 C β.sub.1 4 β.sub.2 0.2572 C 90 0  0.25 C β.sub.1 4 β.sub.2  0.25 C

TABLE-US-00003 TABLE 3 Ratio of maximum Total current to minimum current current Mainstream design (before C 103 adjustment) Design of the present <0.4167 C 26 disclosure M = 2 (after adjustment) Design of the present <0.1988 C 13 disclosure M = 3 (after adjustment) Design of the present <0.0982 C 6.5 disclosure M = 4 (after adjustment) Design of the present <0.0406 C 3.3 disclosure M = 5 (after adjustment)