Method for managing the memory space of a memory device and corresponding system

Abstract

A system includes a memory device that includes a first memory region to store first data at first addresses, and a second memory region to store, on command, either second data at second addresses or error correction code check bits associated with the first data at third addresses.

Claims

1. A system comprising: a memory device comprising a first memory region configured to store first data at first addresses, and a second memory region configured to store second data at second addresses when a signal command is set to a first value and configured to store error correction code check bits associated with the first data at third addresses when the signal command is set to a second value, the third addresses being truncated first addresses, and a processing circuit configured to determine the third addresses on the basis of the first addresses.

2. The system according to claim 1, furthermore comprising: an interface configured to receive the first data and first initial addresses associated with the first data, and the second data and second initial addresses associated with the second data, and deliver the first addresses and the second addresses on the basis of the first initial addresses and of the second initial addresses, an error correction code circuit configured to determine the error correction code check bits associated with the first data, and a control circuit configured to deliver, to the second memory region, either the second data and the second addresses or the error correction code check bits and the third addresses.

3. The system according to claim 1, wherein the first memory region comprises at least one first memory zone having a first memory size and the second memory region comprises a second memory zone also having the first memory size.

4. The system according to claim 3, wherein the at least one first memory zone and the second memory zone comprise rows, wherein the first data is stored in a first number of successive rows of the at least one first memory zone, and wherein the error correction code check bits associated with the first data are stored in a second number of rows of the second memory zone that is lower than the first number.

5. The system according to claim 4, wherein each row of the at least one first memory zone and each row of the second memory zone are configured to store words of p bytes, wherein the error correction code check bits associated with the first data stored in p successive rows of the at least one first memory zone are stored in the p bytes of a row of the second memory zone.

6. The system according to claim 5, wherein the first memory region contains k times p first memory zones and the second memory region comprises k second memory zones, k being an integer greater than or equal to 1.

7. The system according to claim 3, wherein the first memory region comprises a plurality of first memory zones each having the first memory size.

8. The system according to claim 1, wherein the memory device is a volatile memory device.

9. The system of claim 1, further comprising: an error correction code circuit configured to determine the error correction code check bits associated with the first data, and a control circuit configured to deliver, to the second memory region, either the second data and the second addresses or the error correction code check bits and the third addresses.

10. A memory device comprising: a plurality of memory regions comprising a first memory region configured to store first data at first addresses and a second memory region; an error correction code circuit configured to determine check bits associated with first data to be stored in the first memory region; and a control circuit configured to determine whether a signal command is set to a first value or to a second value different from the first value, deliver a second data to be stored in the second memory region at second addresses in response to determining that the signal command is set to the first value, and deliver the check bits to be stored in the second memory region at third addresses determined on the basis of the first addresses in response to determining that the signal command is set to the second value, the third addresses being truncated first addresses.

11. The memory device according to claim 10, wherein the first memory region comprises at least one first memory zone having a first memory size and the second memory region comprises a second memory zone also having the first memory size.

12. The memory device according to claim 11, further comprising a processing circuit configured to determine the third addresses for the check bits, wherein the at least one first memory zone and the second memory zone comprise rows, wherein the first data is stored in a first number of successive rows of the at least one first memory zone, and wherein the check bits associated with the first data are stored in a second number of rows of the second memory zone that is lower than the first number.

13. The memory device according to claim 12, wherein each row of the at least one first memory zone and each row of the second memory zone are configured to store words of p bytes, wherein the check bits associated with the first data stored in p successive rows of the at least one first memory zone are stored in the p bytes of a row of the second memory zone.

14. The memory device according to claim 13, wherein the first memory region contains k times p first memory zones and the second memory region comprises k second memory zones, k being an integer greater than or equal to 1.

15. A method for managing a memory space of a memory device, the method comprising: storing first data at first addresses of a first memory region of the memory device; in response to determining that a signal command is set to a first value, storing in a second memory region of the memory device, second data at second addresses; in response to determining that the signal command is set to a second value different from the first value, storing error correction code check bits associated with the first data at third addresses in the second memory region; and determining the third addresses on the basis of the first addresses, which includes truncating the first addresses.

16. The method according to claim 15, further comprising: receiving the first data and first initial addresses associated with the first data, and receiving the second data and second initial addresses associated with the second data; formulating the first addresses on the basis of the first initial addresses and formulating the second addresses on the basis of the second initial addresses; determining the error correction code check bits associated with the first data; determining the third addresses of the error correction code check bits; and in response to determining that the signal command is set to the first value or the second value, delivering to the second memory region either the second data and the second addresses or the error correction code check bits and the third addresses.

17. The method according to claim 15, wherein the first memory region comprises at least one first memory zone having a first memory size and the second memory region comprises a second memory zone also having the first memory size.

18. The method according to claim 17, wherein the at least one first memory zone and the second memory zone comprise rows, wherein the first data are stored in a first number of successive rows of the at least one first memory zone and the error correction code check bits associated with the first data are stored in a second number of rows of the second memory zone that is lower than the first number.

19. The method according to claim 18, wherein each row of the at least one first memory zone and each row of the second memory zone are configured to store words of p bytes, and the error correction code check bits associated with the first data stored in p successive rows of the at least one first memory zone are stored in the p bytes of a row of the second memory zone.

20. The method according to claim 19, wherein the first memory region comprises k times p first memory zones and the second memory region comprises k second memory zones, k being an integer greater than or equal to 1.

21. The method according to claim 17, wherein the first memory region comprises a plurality of memory zones each having the first memory size.

22. The method according to claim 16, wherein the memory device is a volatile memory device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and features of the invention will become apparent upon examining the detailed description of completely nonlimiting embodiments and modes of implementation of the invention and the appended drawings, in which:

(2) FIG. 1 illustrates one embodiment of a memory device according to the invention in a first configuration,

(3) FIG. 2 illustrates one embodiment of a memory device according to the invention in a second configuration,

(4) FIG. 3 illustrates one embodiment of a system according to the invention,

(5) FIG. 4 partially illustrates one mode of implementation of the method according to the invention,

(6) FIG. 5 partially illustrates one mode of implementation of the method according to the invention,

(7) FIG. 6 partially illustrates one mode of implementation of the method according to the invention, and

(8) FIG. 7 partially illustrates one exemplary implementation of the invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(9) Modes of implementation and embodiments of the invention relate to the management of the memory space of a memory device, in particular a volatile memory device, for example a static random access memory (SRAM), in particular when the use of an error correction code (ECC) is optional.

(10) According to one mode of implementation and embodiment, what is proposed is a memory capable of storing data and error correction code check bits and of possibly being able to reuse the memory space provided for these check bits, for the purpose of storing data if, in some applications, there is not provision to use an error correction code.

(11) According to one aspect, what is proposed is a system comprising a memory device containing a first memory region intended to store first data at first addresses and a second memory region intended to store, on command, either second data at second addresses or error correction code check bits associated with the first data at third addresses.

(12) In FIG. 1, the reference DMM denotes a memory device, in this case a volatile memory device, containing a first memory region DM1 and a second memory region DM2.

(13) The first memory region DM1 contains four memory zones sram1, sram2, sram3 and sram4 of identical memory size.

(14) In the example illustrated here, these memory zones are formed by separate static random access memories. That being said, it would also be able to be contemplated for these memory zones to be memory zones of one and the same memory.

(15) The second memory region DM2 contains a memory zone sram5, of memory size identical to that of memory zones sram1-sram4.

(16) In this case as well, the memory zone sram5 is a static random access memory.

(17) In the example described here, the width of the memory device is equal to 32 bits, that is to say that it is possible to store 32-bit data words each containing four bytes.

(18) The memory size is equal to n kbits, for example 64 kbits.

(19) The memory zones sram1-sram4 are intended to respectively store data Data-mem-cut1-4.

(20) In the configuration illustrated in FIG. 1, the memory zone sram5 is intended to contain the error correction code check bits associated with the data stored in the memory zones sram1-sram4.

(21) This is performed upon the command of a signal SCECC that in this case adopts the logic value 1, for example.

(22) FIG. 2 illustrates another configuration of the memory device DMM, in which the memory zone sram5 is this time intended to store second data Data-mem-cuts.

(23) This corresponds to the case in which a user may not wish to use an error correction code, but may wish by contrast to use the space available in the memory zone sram5 to store data there.

(24) In this case, the control signal SCECC is equal to o.

(25) Reference is now made more particularly to FIG. 3 in order to describe one embodiment of a system according to the invention.

(26) The system SYS includes an interface SRINT connected to a bus BSS that may have any conventional structure and be for example an AHB bus using a protocol described for example in the document AMBA 3 AHB-Lite Protocol V1.0 Specification, from ARM (2001, 2006).

(27) This bus conveys in particular the first data Data-mem-cut1-4, first initial addresses HADRR associated with the first data, possibly the second data Add-memory-cut5 and their second initial addresses HADRR, and other conventional bus signals, which are not shown here for the sake of simplicity.

(28) The interface SRINT, having a structure that is conventional and known per se, is configured so as to deliver first addresses associated with the first data Data-mem-cut1-4 and so as possibly to deliver second addresses associated with the second data Data-mem-cut5.

(29) These first and second addresses are respectively drawn from the first and second initial addresses HADRR that were conveyed on the bus BSS.

(30) The first and second addresses could be identical to the first initial addresses. That being said, depending on the architecture of the system, and in particular on the width of the memory zones, the first and second addresses may be obtained on the basis of the first and second initial addresses by truncating one or more bits.

(31) In the example described here, a 32-bit word formed of 4 bytes of 8 bits may be written to each row of a memory zone sram1, i equal to 1, 2, 3 or 4.

(32) Thus, in this example, the references Add-mem-cut1-4 denote the addresses of a row of the memory zones sram1-4, and the reference Mask-mem-cut1-4 denotes the number of the byte in the denoted row of the memory zone under consideration.

(33) The addresses Add-mem-cut1-4 and the masks Mask-mem-cut1-4 thus form said first addresses.

(34) Likewise, the address Add-mem-cut5 and the mask Mask-mem-cut5 form the second address associated with a second item of data Data-mem-cut5.

(35) The signals WEN-cut-1-4 and WEN-cut5 are conventional control signals for writing to the various memory zones, and the signals CSEN-cut1-4 and CSEN-cut5 are conventional signals for selecting the memory zone under consideration.

(36) The system SYS also includes an error correction code circuit MECC, having a structure that is conventional and known per se, configured so as to determine the check bits associated with said first data Data-mem-cut1-4.

(37) More precisely, for a four-byte word stored in a row of a memory zone sram1-4, the reference S denotes the s check bits associated with this 4-byte word.

(38) In the case of a 32-bit word, S is a 7-bit word. As a result, S may be stored in one byte of the memory zone sram5.

(39) If the width of the memory were to be 64 bits and not 32 bits, S would have a length of 8 bits, which could still be stored in one byte of the memory zone sram5.

(40) As is conventional, to write a new 32-bit word to a row of one of the memory zones sram1 to sram4, the word that is already stored in this row is first of all read.

(41) The error correction code circuit MECC then determines a syndrome on the basis of the data bits and of the set S of check bits.

(42) It is recalled here that a syndrome is the result of intermediate calculations performed during error correction, making it possible to detect and to locate the error.

(43) If a bit is defective, the MECC block effectively detects this defective bit and corrects it.

(44) Before writing the new word to the address of the previous word in the corresponding memory zone, the MECC block calculates the new set S of new check bits corresponding to the new bytes of data. In this respect, the new set S of check bits is calculated with the corrected value of the defective bit, where applicable.

(45) The new word is then written to the corresponding memory zone at the corresponding first address.

(46) With regard to the new set S of check bits, this is delivered to an input of a multiplexer MX, as illustrated in FIG. 3.

(47) The system SYS also includes processing circuit MT configured so as to determine third storage addresses for these check bits S.

(48) These check bits S will specifically be stored in the memory zone sram5.

(49) A third address in this case contains the address A-ecc of a row of the memory zone sram5 and a mask M-ecc for selecting one of the 4 bytes in said row.

(50) As will be seen in more detail hereinafter, these third addresses are determined on the basis of the first addresses, and more precisely on the basis of the row addresses Add-mem-cut1-4.

(51) The system SYS also includes control circuit MCMD configured so as to deliver, to the second memory region, that is to say in this case to the memory zone sram5, either the second data Data-mem-cut5 and the associated second addresses Add-mem-cut5, Mask-mem-cut5 or the check bits S and the third addresses A-ecc, M-ecc.

(52) The control circuit MCMD in this case includes a module BMCM, for example a logic checking unit delivering the control signal SCECC, and the multiplexer MX receiving this control signal SCECC on its control input.

(53) Of course, depending on the value of the signal SCECC, the signal WEN-cut5 and the signal CSEN-cut5 will also be delivered to the memory interface DM2INT coupled to the memory zone sram5.

(54) By contrast, the signals WEN-cut1-4 and CSEN-cut1-4 are, for their part, delivered only to the interface SM1INT coupled to the first memory region DM1.

(55) Reference is now made more particularly to FIGS. 4 to 7 in order to illustrate one mode of implementation of the method according to the invention.

(56) FIG. 4 more particularly illustrates the obtaining of the first addresses associated with the first data intended to be stored in the memory zones sram1-sram4 on the basis of the first initial addresses HADRR received by the memory interface SRINT.

(57) In the example described here, the initial addresses HADDR are addresses coded on 18 bits b0-b17.

(58) The left-hand part of FIG. 4 illustrates these addresses in hexadecimal format.

(59) The first addresses Add-mem-cut are obtained by truncating the two least significant bits b0, b1 of the initial addresses.

(60) The right-hand part of FIG. 4 thus illustrates these addresses Add-mem-cut in hexadecimal format.

(61) More precisely, the value 0000 is the start address of the zone sram1, whereas the address 3FFF is the end address of this memory zone sram1.

(62) The address 4000 is the start address of the memory zone sram2, whereas the address 7FFF is the end address of this memory zone sram2.

(63) The address 8000 is the start address of the memory zone sram3, whereas the address BFFF is the end address of this memory zone sram3.

(64) Lastly, the address C000 is the start address of the memory zone sram4, whereas the address FFFF is the end address of this memory zone sram4.

(65) Of course, the memory addresses Add-mem-cut5 associated with the data possibly intended to be stored in the memory zone sram5 are obtained in the same way as what has just been described.

(66) FIG. 5 illustrates one example of obtaining the third addresses A-ecc on the basis of the first addresses Add-mem-cut.

(67) More precisely, in this case as well, the addresses Add-mem-cut are truncated by two bits in order to obtain the address A-ecc of the corresponding row in the memory zone sram5.

(68) More precisely, this truncation is a truncation of the two least significant bits b0-b1 of the address Add-mem-cut.

(69) The check bits S associated with the data stored in the memory zone sram1 will thus be written between the addresses 0000 and 0FFF of the memory zone sram5.

(70) The check bits associated with the data written to the memory zone sram2 will be stored between the addresses 1000 and 1FFF of the memory zone sram5.

(71) The check bits associated with the data written to the memory zone sram3 will be stored between the addresses 2000 and 2FFF of the memory zone sram5.

(72) Lastly, the check bits associated with the data written to the memory zone sram4 will be stored between the addresses 3000 and 3FFF of the memory zone sram5.

(73) Lastly, as illustrated in FIG. 6, the mask M-ecc depends on the value of the two least significant bits b1, b0 of the address Add-mem-cut.

(74) More precisely, if these two bits b1, b0 are equal to 0, then the first byte of M-ecc is equal to 1, the other bits being equal to 0, this meaning that the first byte of the corresponding row is selected to store the check bits S.

(75) If the two bits b1, b0 have respective values of 0 and 1, then this time it is the second byte of the mask M-ecc that has the value 1, this meaning that the second byte of the row is selected to store the check bits S.

(76) If the bits b1, b0 have respective values of 1 and 0, then this time it is the third byte of M-ecc that has the value 1, this corresponding to a selection of the third byte of the corresponding row to store the check bits S.

(77) Lastly, if the two bits b1 and b0 both have the value 1, then it is the fourth byte of M-ecc that has the value 1, this corresponding to a selection of the fourth byte of the corresponding row to store the check bits.

(78) Of course, this technique of determining M-ecc is also applicable to determining Mask-mem-cut5-4 and Mask-mem-cut5, so as to select, for each byte of a data word to be stored, the corresponding byte in the addressed row.

(79) Thus, for example if it is desired to store a data byte at the initial address HADDR equal to 0x2001ABC8, the first address will be equal, after truncating the initial address, to 6AF2, this corresponding to a first address Add-mem-cut2 of a row of the second memory zone sram2.

(80) With regard to the 7-bit word forming the word S of the check bits that is associated with the new 32-bit word stored in the row, the address A-ecc of the corresponding row in the memory zone sram5, after truncating the first address Add-mem-cut2, has the value 1ABC.

(81) The mask M-ecc associated with this row address, since the two least significant bits b1, b0 of the first address have respective values of 1 and 0, indicates a selection of the third byte of this row to store this check word S.

(82) Reference is now made more particularly to FIG. 7 in order to illustrate one exemplary implementation of the method according to the invention.

(83) In this example, it is assumed that all of the memory zones sram1 to sram2 and sram5 have a memory size of 64 kbits with a word width of 32 bits.

(84) As a result, each memory zone contains 2048 rows, each row being able to contain a 32-bit (4-byte) word.

(85) The error correction code is applied. Each check word associated with a 32-bit data word contains 7 check bits.

(86) By applying the abovementioned address and mask determination rules, it is seen that the set S11 of check bits associated with the four bytes OCT01, OCT11, OCT21 and OCT31 of the first row of the memory zone sram1 will be stored in the byte OCT35 of the first row of the memory zone sram5.

(87) Likewise, the check bit word S21 associated with the four bytes OCT02, OCT12, OCT22 and OCT32 of the second row of the memory zone sram1 will be stored in the byte OCT25 of the first row of the memory zone sram5.

(88) The check bit word S31 associated with the four bytes OCT03, OCT13, OCT23 and OCT33 of the third row of the memory zone sram1 will be stored in the byte OCT15 of the first row of the memory zone sram5.

(89) Lastly, the check bit word S41 associated with the four bytes OCT04, OCT14, OCT24 and OCT34 of the fourth row of the memory zone sram1 will be stored in the byte OCT05 of the first row of the memory zone sram5.

(90) Also, this process of storing the various check bit words associated with the various rows will continue.

(91) Generally speaking, the four check bit words associated with the four words of four consecutive rows of a memory zone sram1, i varying between 1 and 4, will be stored in just one and the same row of the memory zone sram5.

(92) Therefore, the check words associated with the 2048 rows of the memory zone sram1 will be stored in 512 rows of the memory zone sram5.

(93) Also, the 512 following rows of the memory zone sram5 will be dedicated to storing the check bit words Si2 associated with the data stored in the memory zone sram2.