DOUBLE DATA RATE (DDR) QUAD SWITCHED MULTIBIT DIGITAL TO ANALOG CONVERTER AND CONTINUOUS TIME SIGMA-DELTA MODULATOR

Abstract

A quad signal generator circuit generates four 2.sup.N-1 bit control signals in response to a 2.sup.N-1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2.sup.N-1 unit DAC elements, with each unit DAC element including four switching circuits controlled by corresponding bits of the four 2.sup.N-1 bit control signals. Outputs of the 2.sup.N-1 unit DAC elements are summed to generate an analog output signal. The quad signal generator circuit controls a time delay applied to clock signals relative to the 2.sup.N-1 bit thermometer coded signal and a time delay applied to the 2.sup.N-1 bit thermometer coded signal relative to the delayed clock signals in logically generating the four 2.sup.N-1 bit control signals. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2.sup.N-1 bit thermometer coded signal.

Claims

1. A circuit, comprising: a digital-to-analog converter (DAC) circuit having 2.sup.N-1 unit resistive DAC elements, wherein each unit resistive DAC element includes four switching circuits controlled by corresponding bits of four 2.sup.N-1 bit control signals, and wherein outputs of the 2.sup.N-1 unit resistive DAC elements are summed to generate an analog output signal; and a quad signal generator circuit configured to generate the four 2.sup.N-1 bit control signals in response to a 2.sup.N-1 bit thermometer coded input signal, wherein the quad signal generator circuit comprises: a clock phase circuit configured to generate first and second clock signals that are 180° out of phase with each other and apply a first delay to set clock edges of the first and second clock signals to trail logic switching of the 2.sup.N-1 bit thermometer coded input signal; a first circuit configured to logically combine the 2.sup.N-1 bit thermometer coded input signal with the first clock signal to generate a first one of the four 2.sup.N-1 bit control signals; a second circuit configured to logically combine a delay of the 2.sup.N-1 bit thermometer coded input signal with the second clock signal to generate a second one of the four 2.sup.N-1 bit control signals, wherein the second circuit applies a second delay to set the logic switching of the delayed 2.sup.N-1 bit thermometer coded input signal to trail the clock edges of the first and second clock signals; a third circuit configured to logically combine a logical inversion of the 2.sup.N-1 bit thermometer coded input signal with the first clock signal to generate a third one of the four 2.sup.N-1 bit control signals; and a fourth circuit configured to logically combine a delay of the logical inversion of the 2.sup.N-1 bit thermometer coded input signal with the second clock signal to generate a fourth one of the four 2.sup.N-1 bit control signals, wherein the fourth circuit applies a third delay to set the logic switching of the delayed logical inversion of the 2.sup.N-1 bit thermometer coded input signal to trail the clock edges of the first and second clock signals.

2. The circuit of claim 1, wherein the clock phase circuit of the quad signal generator circuit further applies a frequency division to frequency divide a sampling clock having clock edges aligned with logic switching of the 2.sup.N-1 bit thermometer coded input signal to generate the first and second clock signals.

3. The circuit of claim 2, wherein the frequency division is divide by two.

4. The circuit of claim 1, wherein the clock phase circuit of the quad signal generator circuit derives the first and second clock signals from a sampling clock having clock edges aligned with logic switching of the 2.sup.N-1 bit thermometer coded input signal.

5. The circuit of claim 4, wherein the first delay is less than one half of a clock period of the sampling clock.

6. The circuit of claim 5, wherein the second and third delays are each less than one half of the clock period of the sampling clock.

7. The circuit of claim 6, wherein a sum of the first delay and one of the second and third delays is less than one half of the clock period of the sampling clock.

8. The circuit of claim 4, wherein the second and third delays are equal.

9. The circuit of claim 4, wherein the second and third delays are each less than one half of a clock period of the sampling clock.

10. The circuit of claim 1, wherein each switching circuit of said four switching circuits of each unit resistive DAC element comprises: a first switching circuit configured to switch a first common node between a first and second reference voltages in response to said third one of the four 2.sup.N-1 bit control signals and a logical inversion of said first one of the four 2.sup.N-1 bit control signals; a second switching circuit configured to switch a second common node between the first and second reference voltages in response to the fourth one of the four 2.sup.N-1 bit control signals and a logical inversion of the second one of the four 2.sup.N-1 bit control signals; a third switching circuit configured to switch a third common node between the first and second reference voltages in response to the first one of the four 2.sup.N-1 bit control signals and a logical inversion of the third one of the four 2.sup.N-1 bit control signals; and a fourth switching circuit configured to switch a fourth common node between the first and second reference voltages in response to the second one of the four 2.sup.N-1 bit control signals and a logical inversion of the fourth one of the four 2.sup.N-1 bit control signals.

11. The circuit of claim 10, further comprising: a first resistive circuit coupled between the first common node and a first summing output node for providing a first component of the analog output signal; a second resistive circuit coupled between the second common node and the first summing output node for providing the first component of the analog output signal; a third resistive circuit coupled between the third common node and a second summing output node for providing a second component of the analog output signal; and a fourth resistive circuit coupled between the fourth common node and the second summing output node for providing the second component of the analog output signal.

12. The circuit of claim 11, wherein the first and second components are differential currents of the analog output signal.

13. The circuit of claim 1, wherein the 2.sup.N-1 bit thermometer coded input signal is generated with data weighted averaging (DWA).

14. The circuit of claim 13, further including a DWA circuit configured to apply data weighted averaging to a received 2.sup.N-1 bit thermometer coded signal in order to generate the 2.sup.N-1 bit thermometer coded input signal.

15. The circuit of claim 14, further including a multi-bit quantization circuit configured to generate the 2.sup.N-1 bit thermometer coded signal.

16. The circuit of claim 1, further comprising a loop filter circuit configured to generate a difference signal from a difference between an analog input signal and said analog output signal and filter the difference signal to generate a change signal.

17. The circuit of claim 16, further comprising a multi-bit quantization circuit configured to quantize the change signal and generate a 2.sup.N-1 bit thermometer coded signal from which the 2.sup.N-1 bit thermometer coded input signal is generated.

18. The circuit of claim 17, further comprising a data weighted averaging (DWA) circuit configured to apply data weighted averaging to the 2.sup.N-1 bit thermometer coded signal in order to generate the 2.sup.N-1 bit thermometer coded input signal.

19. The circuit of claim 1, wherein the first delay is less than one half of a clock period of the first and second clock signals.

20. The circuit of claim 19, wherein the second and third delays are each less than one half of the clock period of the first and second clock signals.

21. The circuit of claim 20, wherein a sum of the first delay and one of the second and third delays is less than one half of the clock period of the first and second clock signals.

22. The circuit of claim 1, wherein the second and third delays are equal.

23. The circuit of claim 1, wherein the second and third delays are each less than one half of a clock period of the first and second clock signals.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which:

[0017] FIG. 1 is a time domain block diagram of a conventional sigma-delta analog-to-digital converter circuit with multi bit quantization;

[0018] FIG. 2 is a time domain block diagram of a conventional sigma-delta analog-to-digital converter circuit with multi bit quantization and data weighted averaging;

[0019] FIG. 3A is a time domain block diagram of a continuous time sigma-delta analog-to-digital converter circuit with a multi bit quantizer, data weighted averaging and a quad signal generator controlling a quad switched digital-to-analog converter;

[0020] FIG. 3B is a circuit diagram for a differential signal implementation of the circuit of FIG. 3A using a third-order modulator;

[0021] FIG. 4 is a block diagram of a digital-to-analog converter (DAC) circuit in differential signaling form;

[0022] FIG. 5 is a block diagram of a quad signal generator circuit as used in with circuit of FIG. 4; and

[0023] FIG. 6A is a timing diagram illustrating the double data rate (DDR) quad switching operation of the quad signal generator circuit of FIG. 5;

[0024] FIG. 6B is a timing diagram illustrating a half data rate (HDR) quad switching operation.

DETAILED DESCRIPTION

[0025] Reference is now made to FIG. 3A which shows a time domain block diagram of a continuous time sigma-delta analog-to-digital converter (modulator) circuit 100 with a multi bit quantizer, data weighted averaging and a quad signal generator controlling a quad switched digital-to-analog converter. The circuit 100 includes a continuous time sigma-delta modulator circuit 12 (illustrated here as a first-order circuit, but it being understood that the loop filter of the modulator can be of any order suited to the circuit application requirements; see, FIG. 3B) having an input configured to receive an analog input signal A and an output configured to generate a digital output signal B comprised of a stream of multi-bit thermometer coded data words. The thermometer coded values in the pulse stream of the signal B at a sampling rate fs are processed in a decimator circuit 14 (comprising a low pass filter and down sampler) to generate an equivalent digital signal C of the input signal A with a required resolution and a required output word rate fd, where fd<<fs, set by a decimation factor.

[0026] The first order sigma-delta modulator circuit 12 comprises a difference amplifier 20 (or summation circuit) having a first (non-inverting) input that receives the analog input signal A and a second (inverting) input that receives an analog feedback signal D. The difference amplifier 20 outputs an analog difference signal vdif in response to a difference between the analog input signal A and the analog feedback signal D (i.e., vdif(t)=A(t)−D(t)). The analog difference signal vdif is integrated by an integrator circuit 22 (of the loop filter, here of first order type, without limitation) to generate a change signal vc having a slope and magnitude that is dependent on the sign and magnitude of the analog difference signal vdif. An N-bit quantization circuit 24 samples the change signal vc in response to a clock CLK at the sampling rate fs and generates the digital output signal B as a 2.sup.N-1 bit thermometer coded output word for each sample (where N is an integer N>1). A circuit 30 that implements a data weighted averaging (DWA) algorithm receives the 2.sup.N-1 bit thermometer coded output word and outputs a 2.sup.N-1 bit output DWA word providing for first order mismatch shaping of DAC elements. A quad signal generator circuit 104 receives the 2.sup.N-1 bit output DWA word and the sampling clock CLK and generates four 2.sup.N-1 bit control words DP1, DP2, DM1 and DM2 whose data values change at the same rate as the rate of the sampling clock CLK. A DAC circuit 126 includes 2.sup.N-1 unit resistive DAC elements (UE) that are respectively driven by corresponding bits of the 2.sup.N-1 bits of the control words DP1, DP2, DM1 and DM2 to generate currents which are summed at the output of the DAC circuit to produce an analog signal for the analog feedback signal D. The decimator circuit 14 low pass filters and down samples the 2.sup.N-1 bit code words in the stream of the digital output signal B to generate a digital signal C comprised of the stream of multi-bit (M-bit, the required resolution, where is an integer M>>N) digital words are generated at an output word rate fd set by a decimation factor.

[0027] The implementation illustrated in FIG. 3A is a simplification. In a preferred implementation, the analog signal processing portions of the circuit 100 are constructed as fully differential circuits. FIG. 3B shows a circuit diagram for a differential signal implementation of the circuit of FIG. 3A using a third-order modulator. The loop filter is formed by operational amplifiers OP1, OP2 and OP3 to provide the difference amplifier 20 and integrator circuit 22 for the third-order implementation of the sigma-delta modulator circuit 12 in a configuration with cascaded integrators having feed forward as well as feedback (CIFF-FB). Because of the choice for a third-order implementation with CIFF-FB, two DACs 126 are needed. Each DAC 126 receives the 2.sup.N-1 bits of the control words DP1, DP2, DM1 and DM2 output from the quad signal generator circuit 104 and provides the differential output signal D (Outm and Outp). The operational amplifier OP1 receives the signals A (Inm and Inp) and D1 (Outm1 and Outp1 from one of the DACs) as differential signals. The operational amplifier OP3 receives the signal D2 (Outm2 and Outp2 from the other of the DACs) as a differential signal in combination with the differential signal output from the operational amplifier OP2 and the differential input signal A (Inp and Inm). The quantization circuit 24 receives the signal vc output from the integrator circuit 22 as a differential signal.

[0028] In the differential signaling context as shown in FIG. 3B, FIG. 4 shows a block diagram of the DAC circuit 126 as a differential circuit. The DAC circuit 126 includes 2.sup.N-1 unit resistive DAC elements (UE) 110(1)-110(2.sup.N-1) that are selectively actuated in response to the control word output of the quad signal generator circuit 104 to generate the analog feedback signal D. Each unit resistive DAC element 110 receives the corresponding bit from each of the control words DP1<2.sup.N-1:1>, DP2<2.sup.N-1:1>, DM1<2.sup.N-1:1> and DM2<2.sup.N-1:1>. For example, unit resistive DAC element 110(1) receives the first bits DP1(1), DP2(1), DM1(1) and DM2(1), unit resistive DAC element 110(2) receives the second bits DP1(2), DP2(2), DM1(2) and DM2(2), . . . , and the unit resistive DAC element 110(2.sup.N-1) receives the 2.sup.N-1 th bits DP1(2.sup.N-1), DP2(2.sup.N-1), DM1(2.sup.N-1) and DM2(2.sup.N-1). The quad signal generator circuit 104 generates the bits of the control words DP1<2.sup.N-1:1>, DP2<2.sup.N-1:1>, DM1<2.sup.N-1:1> and DM2<2.sup.N-1:1> from the 2.sup.N-1 bit output DWA word in a manner to be described in detail herein. The bits of the control words DP1<2.sup.N-1:1>, DP2<2.sup.N-1:1>, DM1<2.sup.N-1:1> and DM2<2.sup.N-1:1> change at the same rate as the rate of the sampling clock CLK.

[0029] For each given one X, where X is from 1 to 2.sup.N-1, the unit resistive DAC element 110(X) includes a first CMOS inverter (switching) circuit formed by a pMOS transistor 142 and an nMOS transistor 144 whose source-drain paths are coupled in series between a first reference voltage Vrefp and a second reference voltage Vrefm. The first switching circuit switches between the first and second reference voltages in response to certain ones of the control words where: the gate of the pMOS transistor 142 receives the bit DP1B(X) which is the logical inversion (generated by inverter 146) of the bit DP1(X) of the control word DP1<2.sup.N-1:1>. The gate of the nMOS transistor 144 receives the bit DM1(X) of the control word DM1<2.sup.N-1:1>. The unit resistive DAC element 110(X) also includes a second CMOS inverter (switching) circuit formed by a pMOS transistor 152 and an nMOS transistor 154 whose source-drain paths are coupled in series between the first reference voltage Vrefp and the second reference voltage Vrefm. The second switching circuit switches between the first and second reference voltages in response to certain ones of the control words where: the gate of the pMOS transistor 152 receives the bit DP2B(X) (generated by inverter 156) which is the logical inversion of the bit DP2(X) of the control word DP2<2.sup.N-1:1>. The gate of the nMOS transistor 124 receives the bit DM2(X) of the control word DM2<2.sup.N-1:1>. The common drain terminals of the transistors 142 and 144 at node 160 are connected through a resistor 161 to a first output node 164 of the unit resistive DAC element 110(X). The common drain terminals of transistors 152 and 154 at node 163 are connected through a resistor 162 to the first output node 164 of the unit resistive DAC element 110(X). A first output current signal is generated at the first output node 164.

[0030] The unit resistive DAC element 110(X) further includes a third CMOS inverter (switching) circuit formed by a pMOS transistor 172 and an nMOS transistor 174 whose source-drain paths are coupled in series between the first reference voltage Vrefp and the second reference voltage Vrefm. The third switching circuit switches between the first and second reference voltages in response to certain ones of the control words where: the gate of the pMOS transistor 172 receives the bit DM1B(X) (generated by inverter 176) which is the logical inversion of the bit DM1(X) of the control word DM1<2.sup.N-1:1>. The gate of the nMOS transistor 174 receives the bit DP1(X) of the control word DP1<2.sup.N-1:1>. The unit resistive DAC element 110(X) also includes a fourth CMOS inverter (switching) circuit formed by a pMOS transistor 182 and an nMOS transistor 184 whose source-drain paths are coupled in series between the first reference voltage Vrefp and the second reference voltage Vrefm. The fourth switching circuit switches between the first and second reference voltages in response to certain ones of the control words where: the gate of the pMOS transistor 182 receives the bit DM2B(X) (generated by inverter 186) which is the logical inversion of the bit DM2(X) of the control word DM2<2.sup.N-1:1>. The gate of the nMOS transistor 184 receives the bit DP2(X) of the control word DP2<2.sup.N-1:1>. The common drain terminals of the transistors 172 and 174 at node 190 are connected through a resistor 191 to a second output node 194 of the unit resistive DAC element 110(X). The common drain terminals of transistors 182 and 184 at node 193 are connected through a resistor 192 to the second output node 194 of the unit resistive DAC element 110(X). A second output current signal is generated at the second output node 194.

[0031] The inclusion of a resistor (161, 162, 191, 192) in the output current path from each CMOS inverter (switching) circuit provides an operational advantage. It will be noted that the circuit nodes for the first reference voltage Vrefp and the second reference voltage Vrefm will typically be connected to external pins (pads) of the integrated circuit device. The reference voltages will be applied to these pins. Because the circuit nodes are external, there will be some parasitic resistances in their paths. The use of separate output resistors for each CMOS inverter (switching) circuit, as opposed to the use of a shared resistance for each pair of CMOS inverter (switching) circuits, reduces the sensitivity of the dynamic performance of the modulator to the presence of the parasitic resistances.

[0032] The first reference voltage Vrefp and the second reference voltage Vrefm are selected by the circuit designer based on the design voltages for the circuit. In an embodiment, for example, the first reference voltage Vrefp=1.1V and the second reference voltage Vrefm=0V. Any suitable regulator voltage generator circuit can be used to provide first reference voltage Vrefp and the second reference voltage Vrefm.

[0033] The first output current signals generated at the first output nodes 164 of the unit resistive DAC elements 110(1)-110(2.sup.N-1) are connected together at a summing node to generate a first net output DAC current providing a first component Outp of the differential analog feedback signal D. The second output current signals at the second output nodes 194 of the unit resistive DAC elements 110(1)-110(2.sup.N-1) are connected together at a summing node to generate a second net output DAC current providing a second component Outm of the differential analog feedback signal D. In this implementation, the analog feedback signal D is a differential current signal formed by the Outp and Outm components. The Outp and Outm components forming the analog feedback signal D are then input to the second (inverting) differential signal inputs of the difference amplifier 20. In the implementation of FIG. 3B, the Outp and Outm components forming the analog feedback signal D correspond to the components Outpx and Outmx of signal Dx (where x is 1 or 2 depending on the particular DAC).

[0034] FIG. 5 shows a block diagram of the quad signal generator circuit 104. The sampling clock CLK input to the quad signal generator circuit 104 is processed by a clock phase circuit 200 to output a pair of 180° out of phase clock signals DCLK and DCLKB. In an embodiment, the clock DCLK and its logical inverse (i.e., 180° out of phase) clock DCLKB are at the same frequency as the sampling clock CLK. In another embodiment, the clock DCLK and its logical inverse (i.e., 180° out of phase) clock DCLKB are at a different frequency than the sampling clock CLK (for example, at half frequency with the quad signal generator circuit 104 further including a frequency divider to divide by two). The clock phase circuit 200 further applies a timing delay that ensures that the edges of the DCLK/DCLB clocks trail the switching edge transition of the DWAout<2.sup.N-1:1> word. In other words, the temporally aligned edges of the DCLK/DCLB clocks lag by an amount of the timing delay the corresponding switching edge transition of the DWAout<2.sup.N-1:1>word generated in response to the edge of the sampling clock CLK. The length of delay applied by the clock phase circuit 200 is less than one-half a clock period of the DCLK/DCLB clocks and, in particular, is less than one-half a clock period of the sampling clock CLK.

[0035] It is important to address concerns with timing misalignment in order to avoid the generation of glitches in the control signals DP1(X), DP2(X), DM1(X) and DM2(X). The quad signal generator circuit 104 is configured to control timing alignment by adjusting slight delays in the DWAout<2.sup.N-1:1> word relative to the DCLK clock and/or DCLKB clock in order to ensure that no glitches are generated.

[0036] The 2.sup.N-1 bit output DWA word (DWAout<2.sup.N-1:1>) received from the DWA circuit 102 is logically inverted by circuit 202 to generate an inverted 2.sup.N-1 bit output DWA word (DWAoutB<2.sup.N-1:1>). The quad control words DP1<2.sup.N-1:1>, DP2<2.sup.N-1:1>, DM1<2.sup.N-1:1> and DM2<2.sup.N-1:1> are generated by logically combining the DWAout<2.sup.N-1:1> word, DWAoutB<2.sup.N-1:1> word, DCLK clock and DCLKB clock as follows. The control word DP1<2.sup.N-1:1> is generated by logically ANDing 210 the DWAout<2.sup.N-1:1> word with the DCLK clock. The control word DP2<2.sup.N-1:1> is generated by delaying the DWAout<2.sup.N-1:1> word using a buffer delay circuit 230 and logically ANDing 214 the delayed DWAout<2.sup.N-1:1> word with the DCLKB clock. The control word DM1<2.sup.N-1:1> is generated by logically ANDing 218 the DWAoutB<2.sup.N-1:1> word with the DCLK clock. The control word DM2<2.sup.N-1:1> is generated by delaying the DWAoutB<2.sup.N-1:1> word using a buffer delay circuit 232 and logically ANDing 222 the delayed DWAoutB<2.sup.N-1:1> word with the DCLKB clock.

[0037] In an embodiment, each of the buffer delay circuits 230 and 232 may comprise a plurality of series connected buffer/inverter circuits, where the number of such circuits sets the length of the applied signal delay. In each case, the buffer delay circuits 230 and 232 each apply a timing delay that ensures that the switching edge transition of the delayed DWAout<2.sup.N-1:1> word trails the edges of the DCLK/DCLB clocks trail. In other words, the switching edge transition of the delayed DWAout<2.sup.N-1:1> word lags by the length of the applied signal delay the temporally aligned edges of the DCLK/DCLB clocks. It will also be understood that the length of the applied signal delay may, in an embodiment, be dynamically controlled (for example, in response to voltage and temperature variation during circuit operation). Still further, the length of the applied signal delay may be set during a calibration operation to account for process variation. The length of delay applied by each of the buffer delay circuits 230 and 232 is typically identical and is less than one-half a clock period of the DCLK/DCLB clocks and, in particular, is less than one-half a clock period of the sampling clock CLK.

[0038] In a preferred implementation, a total length of a sum of the length of delay applied by the clock phase circuit 200 and the length of either delay applied by one of the buffer delay circuits 230 and 232 is less than one-half a clock period of the DCLK/DCLB clocks and, in particular, is less than one-half a clock period of the sampling clock CLK.

[0039] Delaying the DCLK/DCLB clocks to trail the switching edge transition of the DWAout<2.sup.N-1:1> word ensures that there are no glitches in the control signals DP1(X) and DM1(X). The delays introduced by the buffer delay circuits 230, 232 further ensure that the switching edge transition of the delayed DWAout<2.sup.N-1:1> word used in the generation of the control signals DP2(X) and DM2(X) trail the edges of the DCLK/DCLB clocks so that there are no glitches in the control signals DP2(X) and DM2(X). By exercising control over timing alignment, this solution obviates the need to latch the control signals DP1(X), DP2(X), DM1(X) and DM2(X) and supports operation where the excess loop delay (ELD) is maintained at less than one period Ts of the sampling clock CLK (it is preferred that the ELD satisfy the following constraint: 0.5Ts<ELD<0.75Ts).

[0040] FIG. 6A shows a timing diagram for operation of the quad signal generator circuit 104 operating to provide for double data rate (DDR) quad switching with respect to an example data signal of <11001010>. For comparison purposes, FIG. 6B shows a timing diagram for the same data signal in using half data rate (HDR) quad switching.

[0041] To summarize, a quad signal generator circuit generates four 2.sup.N-1 bit control signals in response to a 2.sup.N-1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2.sup.N-1 unit DAC elements, with each unit DAC element including four resistors and four switching circuits controlled by corresponding bits of the four 2.sup.N-1 bit control signals. Outputs of the 2.sup.N-1 unit DAC elements are summed to generate an analog output signal. The quad signal generator circuit controls a time delay applied to clock signals relative to the 2.sup.N-1 bit thermometer coded signal and a time delay applied to the 2.sup.N-1 bit thermometer coded signal relative to the delayed clock signals in logically generating the four 2.sup.N-1 bit control signals. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2.sup.N-1 bit thermometer coded signal.

[0042] The outputs of the 2.sup.N-1 unit DAC elements are summed at virtual ground nodes of first and third integrators of a third order four-bit CIFFB continuous time Sigma Delta modulator. The multi bit quantizer and DAC are used in a Sigma Delta ADC to achieve higher SQNR at low OSR as well as to reduce jitter noise.

[0043] The multi bit DAC non linearity increases noise floor as well as introduces harmonic distortions in ADC output. Hence, the dynamic performances (SNR, SFDR, THD) of the ADC is severely degraded. To provide for a more linear multi bit DAC linear, DWA is used to minimize the effects of mismatch in DAC elements. With DWA, the DAC elements are switched at every rising edge of the clock. Due to DWA, the data dependent switching is significantly higher, and as a result increased the noise floor and introduced distortions in the modulator output spectrum. The double data rate (DDR) quad switched multi bit DAC and quad signal generation(to have minimum delay to minimize the ELD effects and no glitches) in order to achieve excellent dynamic performance of about 100 dB.

[0044] Although disclosed herein in the context of a continuous time delta sigma modulator, it will be understood that the disclosed circuit and operation herein is also applicable to discrete time modulators.

[0045] While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.