Power supply circuit

Abstract

An output terminal of a power supply circuit is coupled to a load. A control circuit charges multiple intermediate capacitors using an input voltage in a time-sharing manner. Furthermore, the control circuit selects at least one intermediate capacitor that is not being charged from among the multiple intermediate capacitors, and couples the intermediate capacitor thus selected to an output capacitor.

Claims

1. A power supply circuit comprising: an input terminal structured to receive a DC input voltage; an output terminal to be coupled to a load, a plurality of intermediate capacitors, an output capacitor coupled to the output terminal; and a control circuit structured to charge the plurality of intermediate capacitors using the input voltage in a time-sharing manner, to select at least one intermediate capacitor that is not being charged from among the plurality of intermediate capacitors, and to couple the intermediate capacitor thus selected to the output capacitor, wherein the plurality of intermediate capacitors comprises first intermediate capacitors and second intermediate capacitors, wherein the control circuit comprises: a first high-side switch arranged between the first intermediate capacitor and the input terminal; a second high-side switch arranged between the second intermediate capacitor and the input terminal; a first low-side switch arranged between the first intermediate capacitor and the output capacitor, a second low-side switch arranged between the second intermediate capacitor and the output capacitor; and a timing generator structured to control the first high-side switch, the second high-side switch, the first low-side switch, and the second low-side switch according to a clock, wherein, during a first charging period with one edge of the clock as a start point, the timing generator turns on the first high-side switch and the second low-side switch, and wherein, during a second charging period with the other edge of the clock as a start point, the timing generator turns on the second high-side switch and the first low-side switch.

2. A power supply circuit comprising: an input terminal structured to receive a DC input voltage; an output terminal to be coupled to a load; a plurality of intermediate capacitors; an output capacitor coupled to the output terminal; and a control circuit structured to charge the plurality of intermediate capacitors using the input voltage in a time-sharing manner, to select at least one intermediate capacitor that is not being charged from among the plurality of intermediate capacitors, and to couple the intermediate capacitor thus selected to the output capacitor, wherein the plurality of intermediate capacitors comprises first intermediate capacitors and second intermediate capacitors, wherein the control circuit comprises: a first high-side switch arranged between the first intermediate capacitor and the input terminal; a second high-side switch arranged between the second intermediate capacitor and the input terminal, a first low-side switch arranged between the first intermediate capacitor and the output capacitor; a second low-side switch arranged between the second intermediate capacitor and the output capacitor, and a timing generator structured to control the first high-side switch, the second high-side switch, the first low-side switch, and the second low-side switch according to a clock, wherein, during a first period with one edge of the clock as a start point, the timing generator turns on the first low-side switch, wherein, during a second period with the other edge of the clock as a start point, the timing generator turns on the second low-side switch, wherein, during a half-cycle of the clock delayed so as to include the first period, the timing generator turns on the second high-side switch, and wherein, during a half-cycle of the clock delayed so as to include the second period, the timing generator turns on the first high-side switch.

3. The power supply circuit according to claim 1, wherein the load comprises an oscillator structured to generate the clock, wherein the timing generator comprises a delay line structured to delay the clock, and wherein a delay amount provided by the delay line defines a length of an on time of the first low-side switch and the second low-side switch.

4. The power supply circuit according to claim 3, wherein the delay amount provided by the delay line is fixed.

5. The power supply circuit according to claim 3, wherein the delay line is structured as a replica of a delay circuit included in the oscillator.

6. The power supply circuit according to claim 5, wherein the delay line is structured to receive a supply of a control code that corresponds to a control code to be supplied to the delay circuit included in the oscillator.

7. The power supply circuit according to claim 3, wherein, in a case in which the power supply circuit is also operated as a low-pass filter, and the oscillator is operated with noise characteristics as a high-pass filter, a cutoff frequency of the low-pass filter is lower than a cutoff frequency of the high-pass filter.

8. An integrated circuit comprising: a PLL circuit structured to generate a clock; and a power supply circuit structured to supply a power supply voltage to the PLL circuit, wherein the power supply circuit comprises: an input terminal structured to receive a DC input voltage; an output terminal coupled to a power supply line of the PLL circuit; a first intermediate capacitor; a second intermediate capacitor; an output capacitor coupled to the output terminal; a first high-side switch arranged between the first intermediate capacitor and the input terminal; a second high-side switch arranged between the second intermediate capacitor and the input terminal; a first low-side switch arranged between the first intermediate capacitor and the output terminal; a second low-side switch arranged between the second intermediate capacitor and the output terminal; and a timing generator structured to control the first high-side switch, the second high-side switch, the first low-side switch, and the second low-side switch, based on the clock; wherein the PLL circuit comprises: a first delay circuit structured to adjust a delay with a relatively low precision; and a second delay circuit structured to adjust a delay with a relatively high precision, wherein the integrated circuit comprises two of the power supply circuits, wherein one from among the two power supply circuits supplies a power supply voltage to the first delay circuit, and wherein the other from among the two power supply circuits supplies a power supply voltage to the second delay circuit.

9. The integrated circuit according to claim 8, wherein the timing generator is structured to be switchable between (i) a first charging state in which the first high-side switch is turned on and the second high-side switch is turned off, (ii) a second charging state in which the first high-side switch is turned off and the second high-side switch is turned on, and (iii) a non-charging state in which both the first high-side switch and the second high-side switch are turned off, and to sequentially repeat the first charging state, the non-charging state, the second charging state, and the non-charging state.

10. The integrated circuit according to claim 9, wherein, in the first charging state, the timing generator couples the second intermediate capacitor to the output capacitor, and wherein, in the second charging state, the timing generator couples the first intermediate capacitor to the output capacitor.

11. The integrated circuit according to claim 8, wherein the timing generator is structured to sequentially and alternately repeat (i) a first charging state in which the first high-side switch is turned on and the second high-side switch is turned off, and (ii) a second charging state in which the first high-side switch is turned off and the second high-side switch is turned on.

12. The integrated circuit according to claim 11, wherein, in a part of a time period of the first charging state, the timing generator turns on the second low-side switch, and wherein, in a part of a time period of the second charging state, the timing generator turns on the first low-side switch.

13. The power supply circuit according to claim 2, wherein the load comprises an oscillator structured to generate the clock, wherein the timing generator comprises a delay line structured to delay the clock, and wherein a delay amount provided by the delay line defines a length of an on time of the first low-side switch and the second low-side switch.

14. The power supply circuit according to claim 13, wherein the delay amount provided by the delay line is fixed.

15. The power supply circuit according to claim 13, wherein the delay line is structured as a replica of a delay circuit included in the oscillator.

16. The power supply circuit according to claim 15, wherein the delay line is structured to receive a supply of a control code that corresponds to a control code to be supplied to the delay circuit included in the oscillator.

17. The power supply circuit according to claim 13, wherein, in a case in which the power supply circuit is also operated as a low-pass filter, and the oscillator is operated with noise characteristics as a high-pass filter, a cutoff frequency of the low-pass filter is lower than a cutoff frequency of the high-pass filter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments will now be described, by way of example only, with reference to the accompanying drawings which are meant to be exemplary, not limiting, and wherein like elements are numbered alike in several Figures, in which:

(2) FIGS. 1A through FIG. 1C are block diagrams each showing an LSI;

(3) FIG. 2 is a circuit diagram showing an architecture disclosed in Non-patent document 1;

(4) FIG. 3 is a circuit diagram showing an integrated circuit including a power supply circuit according to an embodiment;

(5) FIG. 4 is a circuit diagram showing a power supply circuit according to an embodiment;

(6) FIG. 5 is a circuit diagram showing a timing generator according to a first example;

(7) FIG. 6 is an operation waveform diagram showing the operation of a power supply circuit according to the first example;

(8) FIG. 7 is a circuit diagram showing a power supply circuit according to a second example;

(9) FIG. 8 is an operation waveform diagram showing the operation of the power supply circuit according to the second example;

(10) FIGS. 9A and FIG. 9B are equivalent circuit diagrams each showing the power supply circuit;

(11) FIG. 10 is a circuit diagram showing an integrated circuit according to an example;

(12) FIG. 11A is an equivalent circuit diagram showing the integrated circuit, and FIG. 11B is a diagram showing the frequency characteristics of the integrated circuit as a whole;

(13) FIG. 12 is a circuit diagram showing an integrated circuit according to an example;

(14) FIG. 13 is a diagram showing results of measurement of the phase noise characteristics; and

(15) FIGS. 14A and FIG. 14B are diagrams each showing the time frequency waveforms (simulation results) of the power supply voltage V.sub.DD, the output voltage V.sub.OUT, and the frequency of a clock CLK.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments

(16) Description will be made below regarding the present invention based on preferred embodiments with reference to the drawings. The same or similar components, members, and processes are denoted by the same reference numerals, and redundant description thereof will be omitted as appropriate. The embodiments have been described for exemplary purposes only, and are by no means intended to restrict the present invention. Also, it is not necessarily essential for the present invention that all the features or a combination thereof be provided as described in the embodiments.

(17) In the present specification, a state represented by the phrase “the member A is coupled to the member B” includes a state in which the member A is indirectly coupled to the member B via another member that does not substantially affect the electric connection between them, or that does not damage the functions or effects of the connection between them, in addition to a state in which they are physically and directly coupled.

(18) Similarly, a state represented by the phrase “the member C is provided between the member A and the member B” includes a state in which the member A is indirectly coupled to the member C, or the member B is indirectly coupled to the member C via another member that does not substantially affect the electric connection between them, or that does not damage the functions or effects of the connection between them, in addition to a state in which they are directly coupled.

(19) FIG. 3 is a circuit diagram showing an integrated circuit 200 including a power supply circuit 100 according to an embodiment. The integrated circuit 200 includes circuit blocks 202 and 204 in addition to the power supply circuit 100. The first circuit block 202 includes a circuit that serves as a power supply noise source and/or a circuit having high noise resistance. The second circuit block 204 is configured as a circuit that should avoid power supply noise, i.e., a circuit having poor power supply noise resistance regardless of whether it is configured as a digital circuit or an analog circuit.

(20) An external power supply voltage V.sub.DD is supplied to a power supply pin VDD of the integrated circuit 200. The power supply voltage V.sub.DD includes a noise component due to a power supply that generates the power supply voltage V.sub.DD or a power supply noise component due to the circuit block 202.

(21) The power supply circuit 100 receives the DC power supply voltage V.sub.DD (input voltage V.sub.IN) via its input terminal 102. The power supply circuit 100 removes power supply noise from the power supply voltage V.sub.DD, and outputs a power supply voltage V.sub.OUT thus subjected to noise removal via an output terminal 104 thereof. The power supply voltage V.sub.OUT is supplied to the second circuit block 204.

(22) The power supply circuit 100 includes multiple intermediate capacitors C.sub.1 through C.sub.N (N≥2), an output capacitor C.sub.OUT, and a control circuit 110.

(23) The multiple intermediate capacitors C.sub.1 through C.sub.N and the output capacitor C.sub.OUT are each arranged such that one end is grounded. Furthermore, the other end of the output capacitor C.sub.OUT is coupled to the output terminal 104.

(24) The control circuit 110 is coupled to the input terminal 102, and to each of the other ends of the multiple intermediate capacitors C.sub.1 through C.sub.N and the output capacitor C.sub.OUT.

(25) The control circuit 110 charges the multiple intermediate capacitors C.sub.1 through C.sub.N using the input voltage V.sub.IN in a time-sharing manner. Furthermore, the control circuit 110 selects at least one intermediate capacitor that is not being charged from among the multiple intermediate capacitors C.sub.1 through C.sub.N, and couples the intermediate capacitor thus selected to the output capacitor C.sub.OUT.

(26) The above is the configuration of the power supply circuit 100. With the power supply circuit 100, the output capacitor C.sub.OUT is not directly coupled to the input terminal 102 in any period. Instead, at least one intermediate capacitor in a state in which it is disconnected from the input terminal 102 (non-charging state) is selected from among the multiple intermediate capacitors C.sub.1 through C.sub.N, and only the intermediate capacitor thus selected is coupled to the output capacitor C.sub.OUT. As a result, power supply noise superimposed on the input voltage V.sub.IN is not directly supplied to the output terminal 104. This allows the power supply noise to be removed.

(27) The power supply circuit 100 is configured with a circuit area that is smaller than that of an LDO. Such an arrangement is capable of suppressing an increase in the chip area and an increase in costs. Furthermore, unlike such an LDO, the power supply circuit 100 involves no feedback control operation. Such an arrangement has an advantage of allowing the power supply circuit 100 to be designed in a simple manner.

(28) The present invention encompasses various kinds of apparatuses and methods that can be regarded as a block configuration or a circuit configuration shown in FIG. 3, or that can be derived from the aforementioned description. That is to say, the present invention is not restricted to a specific configuration. More specific description will be made below regarding example configurations and examples for clarification and ease of understanding of the essence of the present invention and the operation. That is to say, the following description will by no means be intended to restrict the technical scope of the present invention.

(29) FIG. 4 is a circuit diagram showing the power supply circuit 100 according to an example. In addition to the intermediate capacitors C.sub.1 through C.sub.N and the output capacitor C.sub.OUT, the power supply circuit 100 includes multiple high-side switches SWH, multiple low-side switches SWL, and a timing generator 120, which correspond to the control circuit 110. The number N of the intermediate capacitors is not restricted in particular. Description will be made regarding an example in which N=2. In this example, “C.sub.1” represents a first intermediate capacitor, and “C.sub.2” represents a second intermediate capacitor.

(30) The multiple high-side switches SWH.sub.# (#=1 through N) are each arranged between the input terminal 102 and the corresponding intermediate capacitor C.sub.#. The multiple low-side switches SWL.sub.# (#=1 through N) are each arranged between the output terminal 104 and the corresponding intermediate capacitor C.sub.#.

(31) The timing generator 120 generates upper-side gate signals HG.sub.1 through HG.sub.N, and lower-side gate signals LG.sub.1 through LG.sub.N, so as to control the multiple high-side switches SWH.sub.1 through SWH.sub.N, and the multiple low-side switches SWL.sub.1 through SWL.sub.N.

(32) For example, the switches SWH and SWL may each be configured as a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In this case, when the gate signals HG and LG are set to the high level, the switches SWH and SWL are turned off. Conversely, when the gate signals HG and LG are set to the low level, the switches SWH and SWL are turned on.

(33) Various kinds of examples can be made with respect to the configuration of the timing generator 120 and the timing control operation. Description will be made below regarding several such examples.

FIRST EXAMPLE

(34) The control circuit 110 is switchable between a first charging state ϕ.sub.1, a second charging state ϕ.sub.2, and a non-charging state ϕ.sub.NC. First, description will be made regarding the operation of the high-side circuit configuration. First charging state ϕ.sub.1

(35) In the first charging state ϕ.sub.1, the first intermediate capacitor C.sub.1 is charged by the input voltage V.sub.IN.

(36) SWH.sub.1=ON

(37) SWH.sub.2=OFF Second charging state ϕ.sub.2

(38) In the second charging state ϕ.sub.2, the second intermediate capacitor C.sub.2 is charged by the input voltage V.sub.IN.

(39) SWH.sub.1=OFF

(40) SWH.sub.2=ON Non-charging state ϕ.sub.NC

(41) In the non-charging state ϕ.sub.NC, both the first intermediate capacitor C.sub.1 and the second intermediate capacitor C.sub.2 are not charged.

(42) SWH.sub.1=OFF

(43) SWH.sub.2=OFF

(44) The control circuit 110 sequentially repeats the first charging state ϕ.sub.1, the non-charging state ϕ.sub.NC, the second charging state ϕ.sub.2, and the non-charging state ϕ.sub.NC.

(45) Next, description will be made regarding the operation of the low-side circuit configuration. First charging state ϕ.sub.1

(46) The second intermediate capacitor C.sub.2 is coupled to the output capacitor C.sub.OUT.

(47) SWL.sub.1=OFF

(48) SWL.sub.2=ON Second charging state ϕ.sub.2

(49) The first intermediate capacitor C.sub.1 is coupled to the output capacitor C.sub.OUT.

(50) SWL.sub.1=ON

(51) SWL.sub.2=OFF Non-charging state ϕ.sub.NC

(52) Both the first intermediate capacitor C.sub.1 and the second intermediate capacitor C.sub.2 are disconnected from the output capacitor C.sub.OUT.

(53) SWL.sub.1=OFF

(54) SWL.sub.2=OFF

(55) FIG. 5 is a circuit diagram showing a timing generator 120A according to the first example. During the first charging period with one edge (positive edge) from among the positive edge and the negative edge of the clock CLK as a start point, the timing generator 120A turns on the first high-side switch SWH.sub.1 and the second low-side switch SWL.sub.2. During the second charging period with the other edge (negative edge) from among the positive edge and the negative edge of the clock CLK as a start point, the timing generator 120A turns on the second high-side switch SWH.sub.2 and the first low-side switch SWL.sub.1.

(56) The timing generator 120A includes a delay line 122, an EX-NOR gate 124, and OR gates 126 and 128. The delay line 122 applies a delay to the clock CLK. Specifically, the delay line 122 applies a delay amount τ that is shorter than a half-cycle of the clock CLK. The delay line 122 may be configured as an inverter chain. Also, other kinds of delay circuits may be employed.

(57) The EX-NOR gate 124 generates the EX-NOR (Exclusive-NOR) of the clock CLK before the delay and the clock CLKd after the delay. An output Sp of the EX-NOR gate 124 is configured as a pulse signal, which is set to the low level for a period of the delay time τ with the positive edge or the negative edge of the clock CLK as a start point.

(58) The OR gate 126 is arranged such that the delayed clock CLKd is input to one input thereof and the output Sp of the EX-NOR gate is input to the other input thereof. During a period of the delay time τ from the positive edge of the original clock CLK, the output S1 of the OR gate 126 is set to the low level. The gate signals HG.sub.1 and LG.sub.2 are generated based on the output S1 of the OR gate 126, so as to control the switches SWH.sub.1 and SWL.sub.2.

(59) The OR gate 128 is arranged such that the inverted signal of the delayed clock CLKd is input to one input thereof and the output Sp of the EX-NOR gate is input to the other input thereof. During a period of the delay time τ from the negative edge of the original clock CLK, the output S2 of the OR gate 128 is set to the low level. The gate signals HG.sub.2 and LG.sub.1 are generated based on the output S2 of the OR gate 128, so as to control the switches SWH.sub.2 and SWL.sub.1. It can be clearly understood by those skilled in this art that various kinds of modifications may be made for the timing generator 120A that are capable of supporting the same function, which are encompassed in the technical scope of the present invention.

(60) FIG. 6 is an operation waveform diagram showing the operation of the power supply circuit 100 according to the first example. Here, “V.sub.A” and “V.sub.B” represent the voltage waveforms of the first intermediate capacitor C.sub.1 and the second intermediate capacitor C.sub.2, respectively. “V.sub.OUT” indicates the output voltage across the output capacitor C.sub.OUT.

(61) In the first charging state ϕ.sub.1, the first intermediate capacitor C.sub.1 is charged by the input voltage V.sub.IN, thereby raising the voltage V.sub.A. In this stage, a power supply noise component is superimposed on the voltage V.sub.A. During this period, the second capacitor C.sub.2 is coupled to the output capacitor C.sub.OUT. In this state, the charge stored in the first intermediate capacitor C.sub.2 flows to the output capacitor C.sub.OUT. This charges the output capacitor OUT, thereby raising the output voltage V.sub.OUT.

(62) Subsequently, in the non-charging state ϕ.sub.NC, the output capacitor C.sub.OUT is discharged by a load current, thereby lowering the output voltage V.sub.OUT. In this state, no charge flow occurs in either the first intermediate capacitor C.sub.1 or the second intermediate capacitor C.sub.2. Accordingly, the voltages V.sub.A and V.sub.B are each maintained at a constant level.

(63) Subsequently, in the second charging state ϕ.sub.2, the second intermediate capacitor C.sub.2 is charged by the input voltage V.sub.IN, thereby raising the voltage V.sub.B. During this period, the first intermediate capacitor C.sub.1 is coupled to the output capacitor C.sub.OUT. In this state, the charge stored in the first intermediate capacitor C.sub.1 flows to the output capacitor C.sub.OUT. This charges the output capacitor C.sub.OUT, thereby raising the output voltage V.sub.OUT.

(64) Subsequently, in the non-charging state ϕ.sub.NC, the output capacitor C.sub.OUT is discharged by the load current, thereby lowering the output voltage V.sub.OUTT Charge flow occurs in neither the first intermediate capacitor C.sub.1 mor the second intermediate capacitor C.sub.2. Accordingly, the voltages V.sub.A and V.sub.B are each maintained at a constant level.

(65) The power supply circuit 100 according to the first example repeats this operation. With the first example, the output voltage V.sub.OUT thus generated includes no power supply noise that is included in the input voltage V.sub.IN.

(66) It should be noted that the non-charging state ϕ.sub.NC may be designed to be shorter than the first charging state ϕ.sub.1 and the second charging state ϕ.sub.2. Ideally, the non-charging state ϕ.sub.NC may be omitted. However, in actuality, in a case in which the non-charging state ϕ.sub.NC is designed to be excessively short, such an arrangement has the potential to cause timing mismatching, leading to a situation in which the input voltage V.sub.IN including the power supply noise is directly input to the output terminal 104. In other words, in a case of inserting such a non-charging state ϕ.sub.NC, this arrangement provides relief from the need for severe timing design.

SECOND EXAMPLE

(67) First, description will be made regarding the operation of the high-side switches. The control circuit 110 is configured to be switchable between the first charging state ϕ.sub.1 and the second charging state ϕ.sub.2. First charging state ϕ.sub.1

(68) In the first charging state ϕ.sub.1, the first intermediate capacitor C.sub.1 is charged by the input voltage V.sub.IN.

(69) SWH.sub.1=ON

(70) SWH.sub.2=OFF Second charging state ϕ.sub.2

(71) In the second charging state ϕ.sub.2, the second intermediate capacitor C.sub.2 is charged by the input voltage V.sub.IN.

(72) SWH.sub.1=OFF

(73) SWH.sub.2=ON

(74) The control circuit 110 sequentially and alternately repeats the first charging state ϕ.sub.1 and the second charging state ϕ.sub.2.

(75) Next, description will be made regarding the operation of the low-side switches.

(76) During a part of the time period of the first charging state ϕ.sub.1, the control circuit 110 turns on the second low-side switch SWL.sub.2 so as to couple the second intermediate capacitor C.sub.2 to the output capacitor C.sub.OUT.

(77) Furthermore, during a part of the time period of the second charging state ϕ.sub.2, the first low-side switch SWL.sub.1 is turned on so as to couple the first intermediate capacitor C.sub.1 to the output capacitor C.sub.OUT.

(78) FIG. 7 is a circuit diagram showing a power supply circuit 100B according to a second example. During the first period T.sub.1, a timing generator 120B turns on the first low-side switch SWL.sub.1 with one edge (negative edge) from among the positive and negative edges of the clock CLK as a start point. Furthermore, during the second period T.sub.2, the timing generator 120B turns on the second low-side switch SWL.sub.2 with the other edge (positive edge) from among the positive and negative edges of the clock CLK as a start point.

(79) Furthermore, during a half-cycle of the clock CLK delayed such that it includes the first period T.sub.1, the timing generator 120B turns on the second high-side switch SWH.sub.2. Moreover, during a half-cycle of the clock CLK delayed such that it includes the second period T.sub.2, the timing generator 120B turns on the first high-side switch SWH.sub.1.

(80) The delay line 122 and the EX-NOR gate 124 are each configured to generate the pulse signal Sp in the same manner as in FIG. 5.

(81) A delay line 136 delays the clock CLK so as to generate the HG.sub.1 signal. An inverter 134 inverts the clock CLK. A delay line 138 delays the inverted clock CLKb so as to generate the HG.sub.2 signal.

(82) An OR gate 130 generates the LG.sub.1 signal based on the logical OR of CLK and Sp. An OR gate 132 generates the LG.sub.2 signal based on the logical OR of CLKb and Sp. It can be clearly understood by those skilled in this art that various modifications may be made for the timing generator 120B that support the same functions, which are encompassed in the technical scope of the present invention.

(83) FIG. 8 is an operation waveform diagram showing the operation of the power supply circuit 100B according to the second example. A digital circuit that operates in synchronization with the clock CLK is activated with an edge of the clock as a trigger, which generates an internal state transition. Accordingly, from a microscopic viewpoint, in some cases, the load current I.sub.LOAD flows in an intermittent manner. That is to say, during a part of the clock cycle (active section), the load current I.sub.LOAD flows. On the other hand, during the other part of the clock cycle (inactive section), the load current I.sub.LOAD does not flow. In this case, the output voltage V.sub.OUT decreases in the active section. On the other hand, in the inactive section, the output voltage V.sub.OUT is maintained at a constant level.

(84) In comparison between the first example and the second example, the timing generator 120A shown in FIG. 5 does not require the delay lines 136 and 138 shown in FIG. 7B. This allows the timing generator 120A shown in FIG. 5 to be configured with a reduced circuit area.

(85) With the first and second examples, in a case in which the delay amount τ to be provided by the delay line 136 is fixedly designed, this arrangement provides the following effects. When fluctuation occurs in the temperature or the power supply voltage, this changes the delay amount τ, which increases the pulse width of the pulse signal Sp. This changes the charging time in which the intermediate capacitor is charged or the charging time in which the output capacitor is charged. This provides a feedback control operation so as to suppress the fluctuation in the output voltage V.sub.OUT. For example, when the power supply voltage V.sub.DD (V.sub.IN) falls, this increases the delay amount provided by the delay line 136. This increases the charging time, thereby offsetting the reduction in the input voltage V.sub.IN. Furthermore, when the circuit current rises due to an increase in the clock frequency, an equivalent resistance value R.sub.EQ formed by the switch and the intermediate capacitor is reduced. Accordingly, this arrangement provides a feedback control operation so as to offset a reduction in the input voltage V.sub.IN in the same manner.

(86) FIGS. 9A and 9B are equivalent circuit diagrams each showing the power supply circuit 100. Description will be made with reference to FIG. 9A with the on resistance of each of the high-side switch SWH.sub.# and the low-side switch SWL.sub.# as R.sub.ON, with the switching frequency as f.sub.SW, and with the on time as T.sub.ON (delay time τ described above). With this arrangement, in a case in which the on time T.sub.ON is sufficiently long so as to allow the capacitors C.sub.# and C.sub.OUT to be charged, i.e., in a case in which T.sub.ON>(R.sub.ON×C[#, OUT]), a circuit formed of the high-side switch SWH.sub.# and the capacitor C.sub.# can be represented by the following equivalent resistance R.sub.EQ based on the charge conservation law.
R.sub.EQ=1/(f.sub.SW×C.sub.#).

(87) Accordingly, the output capacitor C.sub.OUT and the equivalent resistance R.sub.EQ formed of the high-side switch SWH.sub.# and the capacitor C.sub.# form a first-order low-pass filter having a cutoff frequency represented by the following Expression.
fc=1/(2π.Math.R.sub.EQ.Math.C.sub.OUT)=1/(2π/f.sub.SW.Math.C.sub.OUT/C.sub.#)

(88) The cutoff frequency fc can be controlled using the switching frequency f.sub.SW.

(89) Description will be made with reference to FIG. 9B. FIG. 9B is an equivalent circuit diagram in a case in which the on time T.sub.ON is not sufficiently long to charge the capacitors C.sub.# and C.sub.OUT, i.e., in a case in which T.sub.ON<(R.sub.ON×C[#, OUT]). In this case, the high-side switches SWH.sub.# and the low-side switches SWL.sub.# are each represented by the following equivalent resistance R.sub.EQ.
R.sub.EQ=R.sub.ON/(T.sub.ON×f.sub.SW)

(90) Here, (T.sub.ON×f.sub.SW) represents the ratio of the on time with respect to the cycle (i.e., duty ratio).

(91) Accordingly, the equivalent resistance R.sub.EQ of the high-side switch SWH.sub.# and the capacitor C.sub.# forms a first-order low-pass filter having a cutoff frequency f.sub.CH represented by f.sub.CH=1/(2π.Math.R.sub.EQ.Math.C.sub.#).

(92) In this case, the cutoff frequency f.sub.CH does not depend on the switching frequency. Instead, the cutoff frequency f.sub.CH can be controlled using the duty ratio.

(93) Furthermore, the output capacitor C.sub.OUT and an equivalent resistance R.sub.EQ of the low-side switch SWL.sub.# also form a first-order low-pass filter having a cutoff frequency f.sub.CL represented by f.sub.CL=1/(2π.Math.R.sub.EQ.Math.C.sub.OUT).

(94) In this case, the cutoff frequency f.sub.CL does not depend on the switching frequency. Instead, the cutoff frequency can be controlled using the duty ratio.

(95) As an overall circuit configuration of the power supply circuit 100, a series connection of the two first-order low-pass filter stages (i.e., a second-order filter) is formed.

(96) In the first or second example, in a case in which the delay amount τ is changed in conjunction with the cycle of the clock CLK, such an arrangement provides the following effects.

(97) The delay amount τ of the delay line 136 corresponds to the on time T.sub.ON. Accordingly, by controlling the cycle of the clock CLK and the on period T.sub.ON in conjunction, such an arrangement is capable of maintaining the duty ratio at a constant level, thereby maintaining the cutoff frequency provided by the power supply circuit 100 that also functions as a low-pass filter.

(98) In addition, the control operation described in the first example has the following advantage as compared with the second example. That is to say, with the second example, the high-side switches are switched at a duty ratio of 50%. Accordingly, the low-pass filter provides a relatively high cutoff frequency f.sub.CH. In contrast, with the first example, the high-side switches are switched at a lower duty ratio. This allows the cutoff frequency f.sub.CH of the low-pass filter to be reduced. This allows a lower-frequency power supply noise component to be removed.

(99) FIG. 10 is a circuit diagram showing an integrated circuit 300 according to an example. The integrated circuit 300 includes a digital circuit 302 having high noise resistance, a PLL circuit 310, and a power supply circuit 100.

(100) The PLL circuit 310 includes a variable-frequency oscillator 312 and a feedback circuit 314. The PLL circuit 310 generates a system clock CLK having a frequency obtained by multiplying the frequency of a reference clock REFCLK, and supplies the system clock CLK to the digital circuit 302.

(101) The variable-frequency oscillator 312 is configured as a VCO (Voltage Controlled Oscillator) or a DCO (Digital Controlled Oscillator). The variable-frequency oscillator 312 includes a delay circuit 316 configured such that its output is fed back to its input. The clock CLK generated by the variable-frequency oscillator 312 is fed back to the feedback circuit 314. The feedback circuit 314 generates a control voltage V.sub.CTRL (or control code D.sub.CTRL) based on the reference clock REFCLK, and adjusts the delay amount of the delay circuit 316.

(102) The digital circuit 302 and the feedback circuit 314 are each configured as a circuit having high noise resistance. The power supply voltage V.sub.DD is directly supplied via the power supply pin VDD to the digital circuit 302 and the feedback circuit 314.

(103) In contrast, in the variable-frequency oscillator 312, power supply noise appears as phase noise of the clock CLK. That is to say, the variable-frequency oscillator 312 has poor power supply noise resistance. Accordingly, the output voltage V.sub.OUT of the power supply circuit 100 is supplied to the power supply terminal of the variable-frequency oscillator 312.

(104) The power supply circuit 100 is configured to switch its state based on the clock CLK generated by the variable-frequency oscillator 312. It should be noted that, in a case in which the timing generator 120 of the power supply circuit 100 has the configuration shown in FIG. 5 or FIG. 7, the delay line 122 may preferably be configured as a replica of the delay circuit 316. Furthermore, the delay amount of the delay line 122 may preferably be controlled such that it follows the delay amount of the delay circuit 316. As described with reference to FIG. 9, this arrangement is capable of maintaining the cutoff frequency provided by the power supply circuit 100 that also functions as a low-pass filter at a constant level.

(105) FIG. 11A is an equivalent circuit diagram showing an integrated circuit 300. With a typical second-order PLL, the noise characteristics of a variable-frequency oscillator 312 (frequency characteristics of phase noise with respect to the frequency of the power supply noise) is represented by a transfer function of the second-order high-pass filter characteristics H.sub.HPF(s). On the other hand, as described above, the power supply circuit 100 can be represented by a transfer function of the low-pass filter characteristics H.sub.LPF(s).

(106) Accordingly, as shown in FIG. 11B, by determining an operating condition such that the cutoff frequency of the low-pass filter is lower than the cutoff frequency fc′ of the high-pass filter, such an arrangement is capable of appropriately removing the phase noise of the clock CLK.

(107) FIG. 12 is a circuit diagram showing an integrated circuit 400 according to an example. The integrated circuit 400 includes a digital circuit 402, a PLL circuit 410, and power supply circuits 100.sub.C and 100.sub.F. A variable-frequency oscillator 412 of the PLL circuit 410 includes two delay circuits 416.sub.C and 416.sub.F coupled in series. The delay circuit 416.sub.C provides a delay that is controllable with a relatively low resolution. The delay circuit 416.sub.F provides a delay that is controllable with a relatively high resolution. That is to say, the variable-frequency oscillator 412 adjusts the oscillation frequency with low resolution by means of the delay circuit 416.sub.C. Furthermore, the variable-frequency oscillator 412 adjusts the oscillation frequency with high resolution by means of the delay circuit 416.sub.F. The delay circuits 416.sub.C and 416.sub.F have different configurations according to the delay range. For example, the first-stage delay circuit 416.sub.C may be configured including multiple logic gates that each provide a unit delay such that they are coupled so as to form a multi-stage delay circuit. Furthermore, the number of the logic gates through which a given signal passes may be changed according to a control code. On the other hand, the second-stage delay circuit 416.sub.F may be configured such that a variable capacitor is coupled to a clock propagation line. Furthermore, the capacitance of the variable capacitor may be adjusted.

(108) The power supply circuit 100.sub.C supplies an output voltage V.sub.OUTC to the delay circuit 416.sub.C. The clock to be used to control the state transition of the power supply circuit 100.sub.C may be taken from the output of the corresponding delay circuit 416.sub.C. Similarly, the power supply circuit 100.sub.F supplies an output voltage V.sub.OUTF to the delay circuit 416.sub.F. The clock to be used to control the state transition of the power supply circuit 100.sub.F may be taken from the output of the corresponding delay circuit 416.sub.F.

(109) In a case in which the timing generator 120 of the power supply circuit 100.sub.C has the configuration shown in FIG. 5 or FIG. 7, the delay line 122 may preferably be configured as a replica of the delay circuit 416.sub.C. Furthermore, a corresponding control code may preferably be supplied to the delay line 122 and the delay circuit 416.sub.C such that the delay amount of the delay line 122 follows the delay amount of the delay circuit 416.sub.C.

(110) Similarly, in a case in which the timing generator 120 of the power supply circuit 100.sub.F has the configuration shown in FIG. 5 or FIG. 7, the delay line 122 may preferably be configured as a replica of the delay circuit 416.sub.F. Furthermore, the delay amount of the delay line 122 may preferably be controlled such that it follows the delay amount of the delay circuit 416.sub.F.

(111) The above is the configuration of the integrated circuit 400.

(112) FIG. 13 is a diagram showing the measurement results of the phase noise characteristics. The solid line indicates the characteristics in a case in which power supply noise having a frequency of 10 kHz and an amplitude of 0.1 V is superimposed on the power supply voltage V.sub.DD. FIG. 13 also shows the characteristics in a case in which the power supply circuit 100 is omitted. As can be understood based on such a comparison between them, in a case in which the power supply circuit 100 is provided, such an arrangement provides dramatically improved phase noise characteristics (26 dB).

(113) FIGS. 14A and FIG. 14B are diagrams each showing time frequency waveforms (simulation results) of the power supply voltage V.sub.DD, the output voltage V.sub.OUT, and the clock CLK. FIG. 14A shows the waveforms in a case in which the power supply circuit 100 is omitted. FIG. 14B shows the waveforms in a case in which the power supply circuit 100 is provided. Description will be made regarding an example in which the clock CLK has a frequency f.sub.OSC of 200 MHz, and the power supply noise has a frequency of 50 MHz. Furthermore, in this example, the noise has an amplitude of 0.1 V, the power supply voltage V.sub.DD is set to 1.5 V, and the temperature is 25° C.

(114) As can be understood based on a comparison between FIGS. 14A and FIG. 14B, in a case in which the power supply circuit 100 is provided, this arrangement allows the frequency fluctuation to be reduced to 1/20. The amount of fluctuation can be adjusted by adjusting the duty ratio of the switch control signal and the capacitance value employed in the power supply circuit 100.

(115) The above-described embodiments have been described for exemplary purposes only, and are by no means intended to be interpreted restrictively. Rather, it can be readily conceived by those skilled in this art that various modifications may be made by making various combinations of the aforementioned components or processes, which are also encompassed in the technical scope of the present invention. Description will be made below regarding such modifications.

First Modification

(116) The layout (topology) of the multiple switches included in the power supply circuit 100 is not restricted to such an arrangement shown in FIG. 4. Various kinds of other switch layouts may be employed so as to allow the input terminal 102, the multiple intermediate capacitors C.sub.1 through C.sub.N, and the output capacitor C.sub.OUT to be appropriately coupled and disconnected, which can be clearly understood by those skilled in this art.

Second Modification

(117) Similarly, the configuration of the timing generator 120 is not restricted to such an arrangement shown in FIG. 5 or FIG. 7. Also, the operation sequence of the power supply circuit 100 is not restricted to such an arrangement shown in FIG. 6 or FIG. 8.

Third Modification

(118) The load circuit of the power supply circuit 100 is not restricted to such a digital circuit. Also, the load circuit of the power supply circuit 100 may be configured as an analog circuit. That is to say, the circuit configuration of the load circuit of the power supply circuit 100 is not restricted in particular so long as it is configured as a circuit that consumes electric power in synchronization with a clock cycle.

(119) Description has been made regarding the present invention with reference to the embodiments using specific terms. However, the above-described embodiments show only the mechanisms and applications of the present invention for exemplary purposes only, and are by no means intended to be interpreted restrictively. Rather, various modifications and various changes in the layout can be made without departing from the spirit and scope of the present invention defined in appended claims.