Surge current suppression circuit

Abstract

A surge current suppression circuit includes a switch, a bypass resistor, a detection resistor, and a comparator. The switch is coupled to a first end of an energy storage capacitor in series, wherein a second end of the energy storage capacitor is coupled to a load and receives an input power source. The bypass resistor is coupled to the switch in parallel. The detection resistor is coupled to the switch in series to generate a detection voltage according to a capacitor current flowing through the energy storage capacitor. The comparator compares the detection voltage with a reference voltage to generate a control signal. When the detection voltage is greater than the reference voltage, the control signal controls the switch to be turned off. When the detection voltage is less than the reference voltage, the control signal controls the main switch to be turned on.

Claims

1. A surge current suppression circuit comprising: a switch coupled to a first end of an energy storage capacitor in series, wherein a second end of the energy storage capacitor is coupled to a load and configured to receive an input power source, wherein the energy storage capacitor is configured to stabilize the input power source provided to the load, a bypass resistor coupled to the switch in parallel, a detection resistor coupled to the switch in series, and configured to generate a detection voltage according to a capacitor current flowing through the energy storage capacitor, and a comparator configured to compare the detection voltage with a reference voltage to generate a control signal, wherein when the detection voltage is greater than the reference voltage, the switch is turned off by the control signal; when the detection voltage is less than the reference voltage, the switch is turned on by the control signal.

2. The surge current suppression circuit in claim 1, wherein when the switch is turned off, the capacitor current flows through the detection resistor through the bypass resistor so as to reduce the capacitor current.

3. The surge current suppression circuit in claim 1, wherein when the capacitor current is greater than or equal to a upper threshold current, the detection voltage is greater than the reference voltage; when the capacitor current is less than or equal to a lower threshold current, the detection voltage is less than the reference voltage.

4. The surge current suppression circuit in claim 1, further comprising: an amplifier configured to amplify the detection voltage and output the amplified detection voltage to the comparator.

5. The surge current suppression circuit in claim 4, wherein a first end of the switch is coupled to the second end of the energy storage capacitor and a first end of the bypass resistor; a second end of the switch is coupled to a second end of the bypass resistor and a first end of the detection resistor.

6. The surge current suppression circuit in claim 5, wherein the first end and a second end of the detection resistor are respectively coupled to a first input end and a second input end of the amplifier; an output end of the amplifier is coupled to a first input end of the comparator; a second input end of the comparator is configured to receive the reference voltage and an output end of the comparator is coupled to a control end of the switch.

7. The surge current suppression circuit in claim 1, wherein in response to a transient voltage change of the input power source; when the capacitor current is greater than or equal to the upper threshold current, the comparator is configured to control the switch to be turned off, and the capacitor current flows through the bypass resistor so that the capacitor current is decreased; when the capacitor current is less or equal to the lower threshold current, the comparator is configured to control the switch to be turned on, and the capacitor current flows through the switch so that the capacitor current is increased.

8. The surge current suppression circuit in claim 1, further comprising: a hysteresis unit coupled between an output end of the comparator and an input end of the comparator which configured to receive the reference voltage, wherein the hysteresis unit is configured to provide a stable output within a voltage range increased at the input end of the comparator.

9. The surge current suppression circuit in claim 8, wherein the hysteresis unit comprises: a resistor, and a diode coupled to the resistor in series; wherein an anode of the diode is coupled to the output end of the comparator and a cathode of the diode is coupled to the input end of the comparator.

10. A power circuit configured to provide an input power source to a load, the power circuit comprising: an energy storage capacitor coupled to the input power source and the load, wherein the energy storage capacitor is configured to stabilize the input power source provided to the load, and a capacitor current flowing through the energy storage capacitor, and a surge current suppression circuit coupled to the energy storage capacitor in series, wherein in response to a transient voltage change of the input power source; when the capacitor current is greater than or equal to an upper threshold current, the surge current suppression circuit is configured to control the capacitor current to be decreased; when the capacitor current is less than or equal to a lower threshold current, the surge current suppression circuit is configured to control the capacitor current to be increased.

11. The power circuit in claim 10, wherein the surge current suppression circuit comprises: a switch coupled to a first end of the energy storage capacitor in series, wherein a second end of the energy storage capacitor is coupled to the load and configured to receive an input power source, a bypass resistor coupled to the switch in parallel, a detection resistor coupled to the switch in series, and configured to generate a detection voltage according to a capacitor current flowing through the energy storage capacitor, and a comparator configured to compare the detection voltage with a reference voltage to generate a control signal, wherein when the detection voltage is greater than the reference voltage, the switch is turned off by the control signal; when the detection voltage is less than the reference voltage, the switch is turned on by the control signal.

12. The power circuit in claim 11, wherein when the switch is turned off, the capacitor current flows through the detection resistor through the bypass resistor so as to decrease the capacitor current.

13. The power circuit in claim 11, wherein when the capacitor current is greater than or equal to the upper threshold current, the detection voltage is greater than the reference voltage; when the capacitor current is less than or equal to the lower threshold current, the detection voltage is less than the reference voltage.

14. The power circuit in claim 11, wherein the surge current suppression circuit further comprises: an amplifier configured to amplify the detection voltage and output the amplified detection voltage to the comparator.

15. The power circuit in claim 11, wherein in response to a transient voltage change of the input power source; when the capacitor current is greater than or equal to the upper threshold current, the comparator is configured to control the switch to be turned off, and the capacitor current flows through the bypass resistor so that the capacitor current is decreased; when the capacitor current is less or equal to the lower threshold current, the comparator is configured to control the switch to be turned on, and the capacitor current flows through the switch so that the capacitor current is increased.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) The present disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawing as follows:

(2) FIG. 1 is a circuit diagram of a power supply system of the related art.

(3) FIG. 2 is a voltage and current waveform of the power supply system that power down and power back occurs in FIG. 1.

(4) FIG. 3 is a block circuit diagram of a power supply system having a surge current suppression circuit according to the present disclosure.

(5) FIG. 4 is a circuit diagram of the surge current suppression circuit according to an embodiment of the present disclosure.

(6) FIG. 5 is a voltage and current waveform of the power supply system having the surge current suppression circuit according to the present disclosure.

DETAILED DESCRIPTION

(7) Reference will now be made to the drawing figures to describe the present disclosure in detail. It will be understood that the drawing figures and exemplified embodiments of present disclosure are not limited to the details thereof.

(8) Please refer to FIG. 3, which shows a block circuit diagram of a power supply system having a surge current suppression circuit according to the present disclosure. The surge current suppression circuit 10 is applied to a power supply system shown in FIG. 1. That is, the current suppression circuit 10 is applied to a circuit structure having an input power source Vdc coupled to an energy storage capacitor C1 and a load R.sub.L. Two ends of the current suppression circuit 10 are coupled between one end (point A) of the energy storage capacitor C1 and a ground end (point B), that is, the current suppression circuit 10 and the energy storage capacitor C1 are coupled on the same path.

(9) Please refer to FIG. 4, which shows a circuit diagram of the surge current suppression circuit according to an embodiment of the present disclosure. The current suppression circuit 10 mainly includes a main switch Q1, a bypass resistor Rb, a detection resistor R.sub.inrush, and a comparator Cv. The bypass resistor Rb is coupled to the main switch Q1 in parallel to form a parallel-connected structure. Take a metal-oxide-semiconductor field-effect transistor (MOSFET) as the main switch Q1 for example, the bypass resistor Rb is coupled between a drain and a source of the MOSFET in parallel. The detection resistor R.sub.inrush is coupled to the parallel-connected structure in series. The detection resistor R.sub.inrush generates a detection voltage V.sub.inrush according to a capacitor current I.sub.C1 flowing through the energy storage capacitor C1. That is, the detection voltage V.sub.inrush across two ends of the detection resistor R.sub.inrush is equal to the product of the capacitor current I.sub.C1 and the detection resistor R.sub.inrush (i.e., V.sub.inrush=I.sub.C1×R.sub.inrush). Therefore, if the capacitor current I.sub.C1 is larger, the obtained detection voltage V.sub.inrush is also larger, and vice versa.

(10) The comparator Cv receives the detection voltage V.sub.inrush and a reference voltage Vref, and compares the detection voltage V.sub.inrush with the reference voltage Vref. In particular, the reference voltage Vref is an adjustable reference voltage, which can be obtained by dividing a power voltage VCP by using a voltage dividing circuit, but this is not a limitation of the present disclosure.

(11) In addition, the current suppression circuit 10 further includes a hysteresis unit, and the hysteresis unit is composed of a diode Dh and a resistor Rh. Specifically, a cathode of the diode Dh is coupled to one end of the resistor Rh to form a series-connected structure of the hysteresis unit. One end of the series-connected structure (i.e., an anode end of the diode Dh) is coupled an output end of the comparator Cv, and the other end of the series-connected structure (i.e., the other end of the resistor Rh) is coupled to a non-inverting input end of the comparator Cv.

(12) When a voltage received by an inverting input end of the comparator Cv is greater than a voltage received by the non-inverting input end, the comparator Cv outputs a low-level voltage (i.e., a ground voltage). The low-level voltage makes the diode Dh be reversed-biased and turned off, and therefore the hysteresis unit is equivalent to an open-circuit state. In this state, the voltage received by the non-inverting input end of the comparator Cv is not affected. On the contrary, when the voltage received by the inverting input end of the comparator Cv is less than the voltage received by the non-inverting input end, the comparator Cv outputs a high-level voltage (i.e., the power voltage VCP). The high-level voltage makes the diode Dh be forward-biased and turned on, and therefore it is equivalent to add the resistor Rh to the non-inverting input end of the comparator Cv. Accordingly, the power voltage VCP is divided by the resistor Rh and an input resistor Ri to increase the voltage received by the non-inverting input end.

(13) Therefore, through the hysteresis unit, the inverting input end of the comparator Cv can provide a stable output within the aforementioned increased voltage range (i.e., the hysteresis range). Accordingly, the two input ends of the comparator Cv can be changed from the comparison of “voltage point” to the comparison of “voltage range” (hysteresis range). It is to allow the voltage received by the inverting input of the comparator Cv to fluctuate within the hysteresis range and still obtain a stable output.

(14) When the capacitor current I.sub.C1 flowing through the energy storage capacitor C1 is greater than or equal to a upper threshold current, the detection voltage V.sub.inrush is greater than the reference voltage Vref so that the comparator Cv controls the main switch Q1 to be turned off. At this condition, the capacitor current I.sub.C1 flows through the bypass resistor Rb connected to the main switch Q1 in parallel to be decreased so as to achieve the suppression of the capacitor current I.sub.C1 that is greater than or equal to the upper threshold current. On the contrary, when the capacitor current I.sub.C1 is less than or equal to a lower threshold current, the detection voltage V.sub.inrush is less than the reference voltage Vref so that the comparator Cv controls the main switch Q1 to be turned on. At this condition, the capacitor current I.sub.C1 flows through the main switch Q1 to be increased. In particular, the upper threshold current is greater than the lower threshold current. Therefore, by directly controlling the main switch Q1 to be turned on or turned off, the capacitor current I.sub.C1 flows through different current paths. Due to different resistance values of the different current paths, the magnitude of the capacitor current I.sub.C1 is effectively adjusted so that the capacitor current I.sub.C1 that is instantaneously returned after a power failure can be effectively suppressed and controlled.

(15) In one embodiment, the surge current suppression circuit 10 further includes a voltage amplifier Av. Two input ends of the voltage amplifier Av are coupled to the detection resistor R.sub.inrush and an output end of the voltage amplifier Av is coupled to the comparator Cv. In particular, two input ends of the voltage amplifier Av are respectively coupled to two ends of the detection resistor R.sub.inrush to amplify the detection voltage V.sub.inrush in a differential amplification manner.

(16) The function of the surge current suppression circuit 10 in the case of a change in a transient voltage in response to the input power will be described hereinafter. In this embodiment, a transient voltage change of the input power refers to a condition in which the input power source Vdc is instantaneously powered down and then back. Specifically, the input power source Vdc instantaneously powered down and then back means the input power source Vdc drops from the normal working voltage to the abnormal working voltage within a time, and then returns to the normal working voltage. For example, the input power source Vdc drops from a normal working voltage (for example, 127 volts to 370 volts) to an abnormal voltage (for example, 0 volt to 100 volts) within 10 milliseconds to 20 milliseconds, and then returns to the normal working voltage (i.e., 127 volts to 370 volts), but this is not a limitation of the present disclosure. In other embodiments, the input power source Vdc may be obtained by converting an AC power source through a rectifier. The condition that the input power source Vdc is instantaneously powered down and then back may be, for example that the AC power source drops from a normal working voltage (for example, 90 volts to 264 volts) to an abnormal voltage (for example, 0 volt to 70 volts), and then returns to the normal working voltage (i.e., 90 volts to 264 volts) so that the input power Vdc is corresponding to the change of the AC power, but the present disclosure is not limited thereto.

(17) Please refer to FIG. 4 and FIG. 5. FIG. 5 shows a voltage and current waveform of the power supply system having the surge current suppression circuit according to the present disclosure.

(18) It is assumed that the input power source Vdc of the power supply system drops at a time t1, and therefore the power required by the load R.sub.L is provided by the energy storage capacitor C1. When the energy storage capacitor C1 is drawn by the load R.sub.L, the output voltage Vb gradually decreases. At a time t2, the input power source Vdc returns to the normal working voltage. At this condition, the output voltage Vb gradually increases. Since the capacitor current I.sub.C1 flowing through the energy storage capacitor C1 is suppressed, the degree of increase (slope) of the output voltage Vb is smaller than that of the output voltage Vb shown in FIG. 2. Since the capacitor current I.sub.C1 is suppressed, it can be seen from FIG. 5 that the capacitor current I.sub.C1 does not increase instantaneously with the surge of the capacitor current I.sub.C1 shown in FIG. 2. The description of suppression and adjustment of the capacitor current I.sub.C1 is as follows.

(19) When the output voltage Vb is instantaneously increased, the capacitor current I.sub.C1 is instantaneously increased. However, since the capacitor current I.sub.C1 is greater than or equal to the upper threshold current, for example but not limited to 15 amps, the detection voltage V.sub.inrush is greater than the reference voltage Vref assumed to be 1 volt. In one embodiment, the detection resistor R.sub.inrush is about 0.01 ohms, and therefore the detection voltage V.sub.inrush is about 0.15 volts. Further, the detection voltage V.sub.inrush is amplified by the voltage amplifier Av, and it is assumed that a gain voltage Vx of the voltage amplifier Av is about 1.5 volts. Since the gain voltage Vx is greater than the reference voltage Vref, the comparator Cv outputs a gate control voltage Vg1 with a low-level voltage. Since the gate control voltage Vg1 fails to drive the main switch Q1 to be turned on, the capacitor current I.sub.C1 flows through the bypass resistor Rb so that the capacitor current I.sub.C1 is decreased. Therefore, the capacitor current I.sub.C1 is suppressed, and the capacitor current I.sub.C1 is prevented from instantaneously increasing in a surge manner.

(20) During the reduction of the capacitor current I.sub.C1, if the capacitor current I.sub.C1 is less than or equal to the lower threshold current, for example but not limited to 8 amps, the gain voltage Vx obtained after the detection voltage V.sub.inrush is amplified by the voltage amplifier Av is 0.8 volts. Since the gain voltage Vx is less than the reference voltage Vref, the comparator Cv outputs the gate control voltage Vg1 with a high-level voltage. The gate control voltage Vg1 drives the main switch Q1 to be turned on, the capacitor current I.sub.C1 flows through the main switch Q1. Since an on-resistance RDS(on) of the main switch Q1 is relatively small compared to the bypass resistance Rb (for example but not limited to about 25 ohms), the capacitor current I.sub.C1 flowing through the main switch Q1 will increase. However, once the capacitor current I.sub.C1 increases to be greater than or equal to the upper threshold current, the comparator Cv outputs the low-voltage gate control voltage Vg1 again to turn off the main switch Q1 so that the capacitor current I.sub.C1 flowing through the bypass resistor Rb again is suppressed. Accordingly, the capacitor current I.sub.C1 presents a steady-state oscillation during the increase and decrease as shown in FIG. 5. Until the surge energy is released, the capacitor current I.sub.C1 returns to the steady-state current. Therefore, the surge current suppression circuit 10 can achieve the effect that the surge current caused by the input power source during the hold-up time can be greatly suppressed.

(21) In conclusion, the present disclosure has following features and advantages:

(22) 1. The surge current can be suppressed and adjusted by using simple switches, detection resistors, and comparison circuits.

(23) 2. The main switch can be directly turned on and turned off to make the capacitor current flow through the current paths of different resistance values so as to effectively adjust the magnitude of the capacitor current and the capacitor current that is instantaneously returned after power failure can be effectively suppressed and controlled.

(24) Although the present disclosure has been described with reference to the preferred embodiment thereof, it will be understood that the present disclosure is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the present disclosure as defined in the appended claims.