Switched capacitor circuit and capacitive DAC

Abstract

A switched capacitor circuit includes an output capacitor, a first transmission switch, a first reference buffer, a second transmission switch, a second reference buffer and a charge compensation circuit. The output capacitor includes a first terminal and a second terminal, wherein the first terminal is coupled to an output terminal of the switched capacitor circuit, and the second terminal is coupled to a reference node. The first transmission switch is coupled to the reference node. The first reference buffer is coupled to the first transmission switch. The second transmission switch is coupled to the reference node. The second reference buffer is coupled to the second transmission switch. The charge compensation circuit is coupled to the reference node.

Claims

1. A switched capacitor circuit, comprising: an output capacitor, comprising: a first terminal, coupled to an output terminal of the switched capacitor circuit; and a second terminal, coupled to a reference node; a first transmission switch, coupled to the reference node; a first reference buffer, coupled to the first transmission switch; a second transmission switch, coupled to the reference node; a second reference buffer, coupled to the second transmission switch; and a charge compensation circuit, coupled between the first transmission switch, the second transmission switch and the output capacitor.

2. The switched capacitor circuit of claim 1, wherein the charge compensation circuit is configured to charge or discharge the output capacitor according to a voltage change on the reference node.

3. The switched capacitor circuit of claim 1, wherein the charge compensation circuit is configured to charge the output capacitor by receiving electric charges from a first power supply node.

4. The switched capacitor circuit of claim 1, wherein the charge compensation circuit is configured to discharge the output capacitor by releasing electric charges to a second power supply node.

5. The switched capacitor circuit of claim 1, wherein the charge compensation circuit is configured to charge the output capacitor when the reference node is switched from a second voltage supplied through the second reference buffer to a first voltage supplied through the first reference buffer, wherein the first voltage is higher than the second voltage.

6. The switched capacitor circuit of claim 1, wherein the charge compensation circuit is configured to discharge the output capacitor when the reference node is switched from a first voltage supplied through the first reference buffer to a second voltage supplied through the second reference buffer, wherein the second voltage is lower than the first voltage.

7. The switched capacitor circuit of claim 1, wherein the charge compensation circuit comprises: a compensation capacitor, comprising: a first terminal, coupled to the reference node; and a second terminal; a first compensation switch, coupled to the second terminal of the compensation capacitor; and a second compensation switch, coupled to the second terminal of the compensation capacitor.

8. The switched capacitor circuit of claim 7, wherein the first compensation switch is further coupled to a first power supply node, and the second compensation switch is further coupled to a second power supply node.

9. The switched capacitor circuit of claim 8, wherein the first compensation switch is turned on to receive electric charges from the first power supply node when the first transmission switch is turned on and the reference node receives a first voltage from the first reference buffer.

10. The switched capacitor circuit of claim 8, wherein the second compensation switch is turned on to release electric charges to the second power supply node when the second transmission switch is turned on and the reference node receives a second voltage from the second reference buffer.

11. The switched capacitor circuit of claim 7, wherein the charge compensation circuit further comprises: a third compensation switch, coupled between the reference node and the compensation capacitor.

12. The switched capacitor circuit of claim 11, wherein the third compensation switch is turned on when a voltage of the reference node is switched.

13. The switched capacitor circuit of claim 1, wherein the charge compensation circuit comprises: a first compensation switch, coupled between the reference node and a first power supply node; and a second compensation switch, coupled between the reference node and a second power supply node.

14. The switched capacitor circuit of claim 13, wherein the first compensation switch is turned on when the reference node is switched from a second voltage to a first voltage higher than the second voltage, allowing the output capacitor to receive electric charges from the first power supply node.

15. The switched capacitor circuit of claim 13, wherein the second compensation switch is turned on when the reference node is switched from a first voltage to a second voltage lower than the first voltage, allowing the output capacitor to release electric charges to the second power supply node.

16. The switched capacitor circuit of claim 1, wherein the charge compensation circuit comprises: a first compensation switch, coupled to the reference node; a first current source, coupled between the first compensation switch and a first power supply node; a second compensation switch, coupled to the reference node; and a second current source, coupled between the second compensation switch and a second power supply node.

17. The switched capacitor circuit of claim 16, wherein the first compensation switch is turned on when the reference node is switched from a second voltage to a first voltage higher than the second voltage, allowing the output capacitor to receive electric charges from the first current source.

18. The switched capacitor circuit of claim 16, wherein the second compensation switch is turned on when the reference node is switched from a first voltage to a second voltage lower than the first voltage, allowing the output capacitor to release electric charges to the second current source.

19. A capacitive digital-to-analog converter (DAC), comprising: a plurality of switched capacitor circuits, each comprising: an output capacitor, comprising: a first terminal, coupled to an output terminal of the capacitive DAC; and a second terminal, coupled to a reference node; a first transmission switch, coupled between the reference node and a first reference buffer; a second transmission switch, coupled between the reference node and a second reference buffer; and a charge compensation circuit, coupled between the first transmission switch, the second transmission switch and the output capacitor.

20. The capacitive DAC of claim 19, wherein the charge compensation circuit is configured to charge or discharge the output capacitor according to a voltage change on the reference node.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic diagram of a general switched capacitor circuit.

(2) FIG. 2 is an exemplary waveform diagram of the operations of the switched capacitor circuit.

(3) FIGS. 3 and 4 are schematic diagrams of a switched capacitor circuit according to an embodiment of the present invention.

(4) FIGS. 5 and 6 are schematic diagrams of the switched capacitor circuit with an implementation of the charge compensation circuit according to an embodiment of the present invention.

(5) FIG. 7 is an exemplary waveform diagram of the operations of the switched capacitor circuit shown in FIGS. 5 and 6.

(6) FIGS. 8 and 9 are schematic diagrams of the switched capacitor circuit with a further implementation of the charge compensation circuit according to an embodiment of the present invention.

(7) FIG. 10 is an exemplary waveform diagram of the operations of the switched capacitor circuit shown in FIGS. 8 and 9.

(8) FIGS. 11 and 12 are schematic diagrams of the switched capacitor circuit with another implementation of the charge compensation circuit according to an embodiment of the present invention.

(9) FIG. 13 is an exemplary waveform diagram of the operations of the switched capacitor circuit shown in FIGS. 11 and 12.

(10) FIGS. 14 and 15 are schematic diagrams of the switched capacitor circuit with an additional implementation of the charge compensation circuit according to an embodiment of the present invention.

(11) FIG. 16 is a schematic diagram of a general capacitive DAC.

(12) FIG. 17 is a schematic diagram of a capacitive DAC according to an embodiment of the present invention.

DETAILED DESCRIPTION

(13) Please refer to FIG. 1, which is a schematic diagram of a general switched capacitor circuit 10. As shown in FIG. 1, the switched capacitor circuit 10 includes an output capacitor C.sub.A, transmission switches S.sub.A and S.sub.B, and reference buffers BUF.sub.A and BUF.sub.B. A load circuit 100 may not be included in the switched capacitor circuit 10, but shown in FIG. 1 to facilitate the illustration. The load circuit 100 generally refers to a circuit device or module that operates by receiving a switching voltage from the switched capacitor circuit 10.

(14) In the switched capacitor circuit 10, the output capacitor C.sub.A is configured to provide an output voltage V.sub.OUT for the load circuit 100 to realize various applications. In detail, a first terminal of the output capacitor C.sub.A is coupled to the output terminal of the switched capacitor circuit 10, and a second terminal of the output capacitor C.sub.A is coupled to a reference node N.sub.R. The transmission switches S.sub.A and S.sub.B are respectively coupled to the output capacitor C.sub.A through the reference node N.sub.R. Another terminal of the transmission switches S.sub.A and S.sub.B are coupled to the reference buffers BUF.sub.A and BUF.sub.B, respectively. The transmission switches S.sub.A and S.sub.B may be implemented with transmission gates, transistors, or any other possible circuit elements or modules. Each of the reference buffers BUF.sub.A and BUF.sub.B may be implemented with an operational amplifier connected as a buffer, where the operational amplifier is served to provide output capability (or called driving capability) to output a specific voltage. In this embodiment, the reference buffer BUF.sub.A and the transmission switch S.sub.A are configured to output a voltage V.sub.A, and the reference buffer BUF.sub.B and the transmission switch S.sub.B are configured to output a voltage V.sub.B.

(15) FIG. 2 is an exemplary waveform diagram of the operations of the switched capacitor circuit 10. FIG. 2 illustrates the waveforms of control signals for the transmission switches S.sub.A and S.sub.B. In order to output the switching output voltage V.sub.OUT through the first terminal of the output capacitor C.sub.A, the second terminal of the output capacitor C.sub.A may alternately receive the voltages V.sub.A and V.sub.B through the reference node N.sub.R. With the control of the switches S.sub.A and S.sub.B, the reference node N.sub.R may be switched from the voltage V.sub.A to the voltage V.sub.B or switched from the voltage V.sub.B to the voltage V.sub.A. During the switching operations, the reference buffers BUF.sub.A and BUF.sub.B are configured to charge or discharge the reference node N.sub.R, in order to push or pull the electric charges stored in the output capacitor C.sub.A.

(16) As shown in FIG. 2, the control signals for the transmission switches S.sub.A and S.sub.B are complementary signals, to ensure that the reference node N.sub.R is configured to receive one of the voltages V.sub.A and V.sub.B at each time point. In this embodiment, the control signals at a higher level may turn on (connect) the corresponding switches and at a lower level may turn off (disconnect) the corresponding switches. At the time point T.sub.A, the switch S.sub.A is turned off and the switch S.sub.B is turned on, allowing the reference node N.sub.R to receive the voltage V.sub.B. Subsequently, at the time point T.sub.B, the switch S.sub.A is turned on and the switch S.sub.B is turned off, allowing the reference node N.sub.R to receive the voltage V.sub.A. Supposing that the voltage V.sub.A is higher than the voltage V.sub.B, when the reference node N.sub.R is switched from the lower voltage V.sub.B to the higher voltage V.sub.A (e.g., from T.sub.A to T.sub.B), the electric charges for charging the output capacitor C.sub.A are entirely received from the reference buffer BUF.sub.A. For example, if the amount of electric charges supplied from the reference buffer BUF.sub.A is Q.sub.R, and the amount of electric charges for driving the reference node N.sub.R to rise to the voltage V.sub.A from the voltage V.sub.B is Q.sub.A, the electric charge amount Q.sub.R may be equal to Q.sub.A (i.e., Q.sub.R=Q.sub.A).

(17) From the time point T.sub.B to the time point T.sub.C, the statuses of the switches S.sub.A and S.sub.B do not change; that is, the second terminal of the output capacitor C.sub.A and the reference node N.sub.R are kept at the voltage V.sub.A, and no charging or discharging operation is performed.

(18) At the time point T.sub.C, the switch S.sub.A is turned on and the switch S.sub.B is turned off, allowing the reference node N.sub.R to receive the voltage V.sub.A. Subsequently, at the time point T.sub.D, the switch S.sub.A is turned off and the switch S.sub.B is turned on, allowing the reference node N.sub.R to receive the voltage V.sub.B. When the reference node N.sub.R is switched from the higher voltage V.sub.A to the lower voltage V.sub.B (e.g., from T.sub.C to T.sub.D), the electric charges from the output capacitor C.sub.A are entirely released through the reference buffer BUF.sub.B. For example, if the amount of electric charges released through the reference buffer BUF.sub.B is Q.sub.R, and the amount of electric charges for driving the reference node N.sub.R to fall to the voltage V.sub.B from the voltage V.sub.A is Q.sub.A, the electric charge amount Q.sub.R may be equal to Q.sub.A (i.e., Q.sub.R=Q.sub.A).

(19) During the switching operations from the time point T.sub.A to T.sub.B and from the time point T.sub.C to T.sub.B, the reference buffer BUF.sub.A supplies the required electric charges to the output capacitor C.sub.A, and the reference buffer BUF.sub.B releases the additional electric charges from the output capacitor C.sub.A. In order to achieve faster switching on the output voltage V.sub.OUT, the output capacitor C.sub.A should be charged and discharged more rapidly. Therefore, the output capability of the reference buffers BUF.sub.A and BUF.sub.B should be stronger, so that the voltage at the reference node N.sub.R can be settled more rapidly in the switching operations. However, the stronger output capability of the reference buffers BUF.sub.A and BUF.sub.B is usually accompanied by larger current consumption, higher power requirement and higher design difficulty.

(20) Please refer to FIGS. 3 and 4, which are schematic diagrams of a switched capacitor circuit 30 according to an embodiment of the present invention. As shown in FIGS. 3 and 4, the circuit structure of the switched capacitor circuit 30 is similar to the circuit structure of the switched capacitor circuit 10 shown in FIG. 1, so signals and elements having similar functions are denoted by the same symbols. The difference between the switched capacitor circuit 30 and the switched capacitor circuit 10 is that, the switched capacitor circuit 30 further includes a charge compensation circuit 300. The charge compensation circuit 300 is coupled to the reference node N.sub.R, for supplying several electric charges to the output capacitor C.sub.A or releasing several electric charges from the output capacitor C.sub.A in order to reduce the burden of the reference buffers BUF.sub.A and BUF.sub.B. The operations of the charge compensation circuit 300 may be performed according to the voltage change on the reference node N.sub.R. In detail, if the reference node N.sub.R needs to be switched from a lower voltage (e.g., V.sub.B) to a higher voltage (e.g., V.sub.A), the charge compensation circuit 300 may charge the output capacitor C.sub.A and drive the voltage of the reference node N.sub.R to increase. If the reference node N.sub.R needs to be switched from a higher voltage (e.g., V.sub.A) to a lower voltage (e.g., V.sub.B), the charge compensation circuit 300 may discharge the output capacitor C.sub.A and drive the voltage of the reference node N.sub.R to decrease.

(21) In an embodiment, the charge compensation circuit 300 may be coupled to a first power supply node for receiving a first supply voltage V.sub.DD, which may be a positive supply voltage of the circuit system. The charge compensation circuit 300 may also be coupled to a second power supply node for receiving a second supply voltage V.sub.SS, which may be a negative supply voltage or a ground voltage of the circuit system. In general, the first supply voltage V.sub.DD may be a voltage having the highest level in the circuit system, and the second supply voltage V.sub.SS may be a voltage having the lowest level in the circuit system. The supply voltages V.sub.DD and V.sub.SS are usually supplied from the most powerful voltage sources of the circuit system, which are capable of rapidly sourcing or sinking electric charges, and thus will be preferable for fast driving the switched capacitor circuit 30 to switch the output voltage V.sub.OUT.

(22) FIG. 3 illustrates a charging operation of the charge compensation circuit 300. When the reference node N.sub.R needs to be switched from the lower voltage V.sub.B to the higher voltage V.sub.A (e.g., from T.sub.A to T.sub.B as shown in FIG. 2), a charging path between the first power supply node that supplies the first supply voltage V.sub.DD and the reference node N.sub.R may be conducted; hence, the charge compensation circuit 300 may supply electric charges to charge the output capacitor C.sub.A by receiving the electric charges from the first power supply node. In this embodiment, the amount of electric charges received from the first power supply node may be Q.sub.C. Since the amount of electric charges that drive the reference node N.sub.R to rise to the voltage V.sub.A from the voltage V.sub.B is Q.sub.A, the total electric charge amount Q.sub.R required for the reference buffer BUF.sub.A to charge the output capacitor C.sub.A may be reduced to Q.sub.A minus Q.sub.C (i.e., Q.sub.R=Q.sub.A−Q.sub.C).

(23) FIG. 4 illustrates a discharging operation of the charge compensation circuit 300. When the reference node N.sub.R needs to be switched from the higher voltage V.sub.A to the lower voltage V.sub.B (e.g., from T.sub.C to T.sub.D as shown in FIG. 2), a discharging path between the second power supply node that supplies the second supply voltage V.sub.SS and the reference node N.sub.R may be conducted; hence, the charge compensation circuit 300 may discharge the output capacitor C.sub.A by releasing the electric charges to the second power supply node. Similarly, the amount of electric charges released to the second power supply node may be Q.sub.C. Since the amount of electric charges that drive the reference node N.sub.R to fall to the voltage V.sub.B from the voltage V.sub.A is Q.sub.A, the total electric charge amount Q.sub.R required for the reference buffer BUF.sub.B to discharge the output capacitor C.sub.A may be reduced to Q.sub.A minus Q.sub.C (i.e., Q.sub.R=Q.sub.A−Q.sub.C).

(24) In such a situation, the amount of electric charges processed by the reference buffers BUF.sub.A and BUF.sub.B may be reduced; hence, the requirements of output capability of the reference buffers BUF.sub.A and BUF.sub.B may thereby be reduced. Since the charge compensation circuit 300 is able to provide parts of the electric charges for the output capacitor C.sub.A, the settling time of the output voltage V.sub.OUT may be reduced under identical output capability of the reference buffers BUF.sub.A and BUF.sub.B. Therefore, the operation speed of the switched capacitor circuit 30 may be accelerated.

(25) Please refer to FIGS. 5 and 6, which are schematic diagrams of the switched capacitor circuit 30 with an implementation of the charge compensation circuit 300 according to an embodiment of the present invention. As shown in FIGS. 5 and 6, the charge compensation circuit 300 may include a compensation capacitor C.sub.B and two compensation switches S.sub.1 and S.sub.2. A first terminal of the compensation capacitor C.sub.B is coupled to the reference node N.sub.R, and a second terminal of the compensation capacitor C.sub.B is coupled to the compensation switches S.sub.1 and S.sub.2. The compensation switch S.sub.1 is further coupled to the first power supply node for receiving the first supply voltage V.sub.DD, and the compensation switch S.sub.2 is further coupled to the second power supply node for receiving the second supply voltage V.sub.SS.

(26) FIG. 7 is an exemplary waveform diagram of the operations of the switched capacitor circuit 30 shown in FIGS. 5 and 6. FIG. 7 illustrates the waveforms of control signals for the transmission switches S.sub.A and S.sub.B and the compensation switches S.sub.1 and S.sub.2, where those control signals at a higher level may turn on (connect) the corresponding switches and at a lower level may turnoff (disconnect) the corresponding switches. The detailed operations of the transmission switches S.sub.A and S.sub.B are similar to those of the switched capacitor circuit 10 as described in the above paragraphs, and will not be repeated herein. The control signals for the compensation switches S.sub.1 and S.sub.2 are complementary signals, to ensure that the compensation capacitor C.sub.B is configured to receive one of the supply voltages V.sub.DD and V.sub.SS at each time point. In this embodiment, the control signals for the compensation switch S.sub.1 and the transmission switch S.sub.A are identical; hence, when the transmission switch S.sub.A is turned on and the reference node N.sub.R receives the voltage V.sub.A from the reference buffer BUF.sub.A, the compensation switch S.sub.1 is turned on to allow the compensation capacitor C.sub.B to receive the first supply voltage V.sub.DD. Similarly, the control signals for the compensation switch S.sub.2 and the transmission switch S.sub.B are identical; hence, when the transmission switch S.sub.B is turned on and the reference node N.sub.R receives the voltage V.sub.B from the reference buffer BUF.sub.B, the compensation switch S.sub.2 is turned on to allow the compensation capacitor C.sub.B to receive the second supply voltage V.sub.SS.

(27) Please continue to refer to FIG. 7 together with FIG. 5, which illustrates a charging operation of the charge compensation circuit 300. At the time point T.sub.A, the switch S.sub.1 is turned off and the switch S.sub.2 is turned on, allowing the second terminal of the compensation capacitor C.sub.B to be coupled to the second power supply node to receive the second supply voltage V.sub.SS. Subsequently, at the time point T.sub.B, the switch S.sub.1 is turned on and the switch S.sub.2 is turned off, allowing the second terminal of the compensation capacitor C.sub.B to be coupled to the first power supply node to receive the first supply voltage V.sub.DD. Therefore, from the time point T.sub.A to T.sub.B, the reference node N.sub.R is switched from the voltage V.sub.B to the voltage V.sub.A, and meanwhile, the second terminal of the compensation capacitor C.sub.B is switched from the second supply voltage V.sub.SS to the first supply voltage V.sub.DD. The rising voltage level of the compensation capacitor C.sub.B may provide electric charges to drive the voltage of the reference node N.sub.R to increase.

(28) In such a situation, the charge compensation circuit 300 may supply electric charges to the output capacitor C.sub.A (i.e., Q.sub.C) by coupling of the compensation capacitor C.sub.B, and the rest electric charges are received from the reference buffer BUF.sub.A. Therefore, the amount of electric charges required to be supplied from the reference buffer BUF.sub.A (i.e., Q.sub.R) may be reduced to the total amount of electric charges required for driving the output capacitor C.sub.A (i.e., Q.sub.A) minus the compensation electric charges supplied from the charge compensation circuit 300; that is, Q.sub.R=Q.sub.A-Q.sub.C. As a result, the reference buffer BUF.sub.A may not need to have larger output capability, so that the power consumption of the reference buffer BUF.sub.A may be reduced. Also, the settling speed of the voltages of the switched capacitor circuit 30 may be improved due to the strong output capability of the charge compensation circuit 300.

(29) In this embodiment, the voltage on the second terminal of the compensation capacitor C.sub.B is boosted from the second supply voltage V.sub.SS to the first supply voltage V.sub.DD. Based on the capacitance formula Q=C×ΔV, the electric charges coupled from the compensation capacitor C.sub.B (Q) may be equal to the capacitance value of the compensation capacitor C.sub.B (C) multiplied by the voltage difference received by the compensation capacitor C.sub.B (ΔV). Therefore, the supplied electric charges may be well controlled based on the capacitance value and/or the voltage change of the compensation capacitor C.sub.B. For example, the electric charge amount Q.sub.C supplied from the charge compensation circuit 300 may be configured to approach the total amount of electric charges required for driving the output capacitor C.sub.A, so that the loading of the reference buffer BUF.sub.A may be minimized. In another embodiment, the first supply voltage V.sub.DD and/or the second supply voltage V.sub.SS may be supplied from a specific voltage generator and thus have a predefined voltage, to control the charge compensation circuit 300 to output an appropriate amount of electric charges to the output capacitor C.sub.A. In such a situation, the first supply voltage V.sub.DD and/or the second supply voltage V.sub.SS may not need to have the highest or the lowest voltage level in the circuit system.

(30) Please continue to refer to FIG. 7 together with FIG. 6, which illustrates a discharging operation of the charge compensation circuit 300. At the time point T.sub.C, the switch S.sub.1 is turned on and the switch S.sub.2 is turned off, allowing the second terminal of the compensation capacitor C.sub.B to be coupled to the first power supply node to receive the first supply voltage V.sub.DD. Subsequently, at the time point T.sub.D, the switch S.sub.1 is turned off and the switch S.sub.2 is turned on, allowing the second terminal of the compensation capacitor C.sub.B to be coupled to the second power supply node to receive the second supply voltage V.sub.SS. Therefore, from the time point T.sub.C to T.sub.D, the reference node N.sub.R is switched from the voltage V.sub.A to the voltage V.sub.B, and meanwhile, the second terminal of the compensation capacitor C.sub.B is switched from the first supply voltage V.sub.DD to the second supply voltage V.sub.SS. The falling voltage level of the compensation capacitor C.sub.B may release electric charges to drive the voltage of the reference node N.sub.R to decrease.

(31) In such a situation, the charge compensation circuit 300 may draw electric charges from the output capacitor C.sub.A (i.e., Q.sub.C) by coupling of the compensation capacitor C.sub.B, and the rest electric charges are released through the reference buffer BUF.sub.B. Therefore, the amount of electric charges required to be released through the reference buffer BUF.sub.B (i.e., Q.sub.R) may be reduced to the total amount of electric charges required for driving the output capacitor C.sub.A (i.e., Q.sub.A) minus the compensation electric charges drawn by the charge compensation circuit 300; that is, Q.sub.R=Q.sub.A−Q.sub.C. As a result, the reference buffer BUF.sub.B may not need to have larger output capability, so that the power consumption of the reference buffer BUF.sub.B may be reduced. Also, the settling speed of the voltages of the switched capacitor circuit 30 may be improved due to the strong output capability of the charge compensation circuit 300.

(32) Please refer to FIGS. 8 and 9, which are schematic diagrams of the switched capacitor circuit 30 with a further implementation of the charge compensation circuit 300 according to an embodiment of the present invention. As shown in FIGS. 8 and 9, in addition to the compensation capacitor C.sub.B and the compensation switches S.sub.1 and S.sub.2, the charge compensation circuit 300 further includes a compensation switch S.sub.3. The compensation switch S.sub.3 is coupled between the reference node N.sub.R and the compensation capacitor C.sub.B. In this embodiment, the implementations of the compensation capacitor C.sub.B and the compensation switches S.sub.1 and S.sub.2 and the flow of electric charges are similar to those of the embodiments shown in FIGS. 5 and 6, and will not be narrated herein.

(33) FIG. 10 is an exemplary waveform diagram of the operations of the switched capacitor circuit 30 shown in FIGS. 8 and 9. FIG. 10 illustrates the waveforms of control signals for the transmission switches S.sub.A and S.sub.B and the compensation switches S.sub.1, S.sub.2 and S.sub.3, where those control signals at a higher level may turn on (connect) the corresponding switches and at a lower level may turnoff (disconnect) the corresponding switches. The detailed operations of the transmission switches S.sub.A and S.sub.B and the compensation switches S.sub.1 and S.sub.2 are similar to those of the switched capacitor circuits as described in the above paragraphs, and will not be repeated herein.

(34) As shown in FIG. 10, the compensation switch S.sub.3 is turned on to connect the compensation capacitor C.sub.B to the output capacitor C.sub.A at the voltage switching time, where the transmission switches S.sub.A and S.sub.B and the compensation switches S.sub.1 and S.sub.2 change their statuses and the voltage of the reference node N.sub.R is switched from V.sub.B to V.sub.A or from V.sub.A to V.sub.B. With the turned-on compensation switch S.sub.3, the electric charges required for the output capacitor C.sub.A may be coupled from or to the compensation capacitor C.sub.B. At the time when these switches do not change their statuses and the voltage of the reference node N.sub.R is constant, the compensation switch S.sub.3 may be turned off.

(35) As mentioned above, the electric charges of the charge compensation circuit 300 may be supplied from the first supply voltage V.sub.DD and released to the second supply voltage V.sub.SS. The supply voltages V.sub.DD and V.sub.SS are usually received from the global voltage sources of the circuit system. The global voltage sources are configured to supply voltages to the entire circuit system, and thus may usually have non-ignorable power noises. In order to prevent the power noises from being coupled through the compensation capacitor C.sub.B to interfere with the voltage of the reference node N.sub.R, it is preferable to dispose a switch to isolate the power noises on the global voltage sources. Therefore, the compensation switch S.sub.3 may be turned off at the time when the voltage of the reference node N.sub.R and the output voltage of the switched capacitor circuit 30 remain constant, in order to improve the stability of the voltages.

(36) Please refer to FIGS. 11 and 12, which are schematic diagrams of the switched capacitor circuit 30 with another implementation of the charge compensation circuit 300 according to an embodiment of the present invention. As shown in FIGS. 11 and 12, the charge compensation circuit 300 may include two compensation switches S.sub.1 and S.sub.2. The compensation switch S.sub.1 is coupled between the reference node N.sub.R and the first power supply node for receiving the first supply voltage V.sub.DD, and the compensation switch S.sub.2 is coupled between the reference node N.sub.R and the second power supply node for receiving the second supply voltage V.sub.SS.

(37) FIG. 13 is an exemplary waveform diagram of the operations of the switched capacitor circuit 30 shown in FIGS. 11 and 12. FIG. 13 illustrates the waveforms of control signals for the transmission switches S.sub.A and S.sub.B and the compensation switches S.sub.1 and S.sub.2, where those control signals at a higher level may turn on (connect) the corresponding switches and at a lower level may turn off (disconnect) the corresponding switches. The detailed operations of the transmission switches S.sub.A and S.sub.B are similar to those of the switched capacitor circuit 10 as described in the above paragraphs, and will not be repeated herein.

(38) Please continue to refer to FIG. 13 together with FIG. 11, which illustrates a charging operation of the charge compensation circuit 300. At the time point T.sub.A, the switch S.sub.A is turned off and the switch S.sub.B is turned on, and the voltage of the reference node N.sub.R is V.sub.B. At the time point T.sub.B, the switch S.sub.A is turned on and the switch S.sub.B is turned off, and the voltage of the reference node N.sub.R is V.sub.A. From the time point T.sub.A to T.sub.B where the reference node N.sub.R is switched from the lower voltage V.sub.B to the higher voltage V.sub.A, there is a small time period in which the compensation switch S.sub.1 is turned on, and meanwhile, the transmission switches S.sub.A and S.sub.B may be turned off. At this moment, the output capacitor C.sub.A may receive electric charges from the first power supply node, so that the reference node N.sub.R may be charged to the first supply voltage V.sub.DD. Subsequently, the switch S.sub.A is turned on and the switch S.sub.1 is turned off at the time point T.sub.B, and the reference node N.sub.R is coupled to the reference buffer BUF.sub.A for receiving the voltage V.sub.A.

(39) In such a situation, the charge compensation circuit 300 may supply electric charges to the output capacitor C.sub.A (i.e., Q.sub.C), allowing the reference node N.sub.R to be charged to the first supply voltage V.sub.DD. Supposing that the first supply voltage V.sub.DD is higher than the voltage V.sub.A, the reference buffer BUF.sub.A should release electric charges from the output capacitor C.sub.A, to drive the reference node N.sub.R to fall to the voltage V.sub.A from the first supply voltage V.sub.DD, and the released electric charge amount is Q.sub.R. Therefore, the amount of electric charges required to be released through the reference buffer BUF.sub.A may be equal to the compensation electric charges supplied from the charge compensation circuit 300 minus the total amount of electric charges required for driving the reference node N.sub.R to the voltage V.sub.A from the voltage V.sub.B (i.e., Q.sub.A); that is, Q.sub.R=Q.sub.C-Q.sub.A. If the voltage V.sub.A is close to the first supply voltage V.sub.DD (which means that the electric charge amount Q.sub.A is close to Q.sub.C), the reference buffer BUF.sub.A may not need to have larger output capability, so that the power consumption of the reference buffer BUF.sub.A may be reduced. Also, the settling speed of the voltages of the switched capacitor circuit 30 may be improved due to the strong output capability of the charge compensation circuit 300.

(40) In another embodiment, with an even shorter turned-on pulse of the compensation switch S.sub.1 between the time point T.sub.A and T.sub.B, or if the first supply voltage V.sub.DD is lower than the voltage V.sub.A, the charge compensation circuit 300 may only supply partial electric charges for the output capacitor C.sub.A, and the reset electric charges are supplied from the reference buffer BUF.sub.A to allow the reference node N.sub.R to reach its target voltage V.sub.A. In this manner, the requirement of output capability of the reference buffer BUF.sub.A may also be reduced, so that the power consumption of the reference buffer BUF.sub.A may be reduced. Also, the settling speed of the voltages of the switched capacitor circuit 30 may still be improved.

(41) Please continue to refer to FIG. 13 together with FIG. 12, which illustrates a discharging operation of the charge compensation circuit 300. At the time point T.sub.C, the switch S.sub.A is turned on and the switch S.sub.B is turned off, and the voltage of the reference node N.sub.R is V.sub.A. At the time point T.sub.D, the switch S.sub.A is turned off and the switch S.sub.B is turned on, and the voltage of the reference node N.sub.R is V.sub.B. From the time point T.sub.C to T.sub.D where the reference node N.sub.R is switched from the higher voltage V.sub.A to the lower voltage V.sub.B, there is a small time period in which the compensation switch S.sub.2 is turned on, and meanwhile, the transmission switches S.sub.A and S.sub.B may be turned off. At this moment, electric charges on the output capacitor C.sub.A may be released to the second power supply node, so that the reference node N.sub.R may be discharged to the second supply voltage V.sub.SS. Subsequently, the switch Sp is turned on and the switch S.sub.2 is turned off at the time point T.sub.D, and the reference node N.sub.R is coupled to the reference buffer BUF.sub.B for receiving the voltage V.sub.B.

(42) In such a situation, the charge compensation circuit 300 may release electric charges from the output capacitor C.sub.A (i.e., Q.sub.C), allowing the reference node N.sub.R to be discharged to the second supply voltage V.sub.SS. Supposing that the second supply voltage V.sub.SS is lower than the voltage V.sub.B, the reference buffer BUF.sub.B should supply electric charges to the output capacitor C.sub.A, to drive the reference node N.sub.R to rise to the voltage V.sub.B from the second supply voltage V.sub.SS, and the supplied electric charge amount is Q.sub.R. Therefore, the amount of electric charges required to be supplied from the reference buffer BUF.sub.B may be equal to the compensation electric charges released through the charge compensation circuit 300 minus the total amount of electric charges required for driving the reference node N.sub.R to the voltage V.sub.B from the voltage V.sub.A (i.e., Q.sub.A); that is, Q.sub.R=Q.sub.C−Q.sub.A. If the voltage V.sub.B is close to the second supply voltage V.sub.SS (which means that the electric charge amount Q.sub.A is close to Q.sub.C), the reference buffer BUF.sub.B may not need to have larger output capability, so that the power consumption of the reference buffer BUF.sub.B may be reduced. Also, the settling speed of the voltages of the switched capacitor circuit 30 may be improved due to the strong output capability of the charge compensation circuit 300.

(43) In another embodiment, with an even shorter turned-on pulse of the compensation switch S.sub.2 between the time point T.sub.C and T.sub.D, or if the second supply voltage V.sub.SS is higher than the voltage V.sub.B, the charge compensation circuit 300 may only release partial electric charges from the output capacitor C.sub.A, and the reset electric charges are released through the reference buffer BUF.sub.B to allow the reference node N.sub.R to reach its target voltage V.sub.B. In this manner, the requirement of output capability of the reference buffer BUF.sub.B may also be reduced, so that the power consumption of the reference buffer BUF.sub.B may be reduced. Also, the settling speed of the voltages of the switched capacitor circuit 30 may still be improved.

(44) Please refer to FIGS. 14 and 15, which are schematic diagrams of the switched capacitor circuit 30 with an additional implementation of the charge compensation circuit 300 according to an embodiment of the present invention. As shown in FIGS. 14 and 15, the charge compensation circuit 300 may include two compensation switches S.sub.1 and S.sub.2 and two current sources I.sub.1 and I.sub.2. The compensation switches S.sub.1 and S.sub.2 are coupled to the reference node N.sub.R. The current source I.sub.1 is coupled between the compensation switch S.sub.1 and the first power supply node. The current source I.sub.2 is coupled between the compensation switch S.sub.2 and the second power supply node.

(45) The waveforms regarding the operations of the switched capacitor circuit 30 shown in FIGS. 14 and 15 are similar to those shown in FIG. 13, where the waveforms of control signals for the transmission switches S.sub.A and S.sub.B and the compensation switches S.sub.1 and S.sub.2 are illustrated. The detailed operations of the transmission switches S.sub.A and S.sub.B are similar to those of the switched capacitor circuit 10 as described in the above paragraphs, and will not be repeated herein.

(46) Please continue to refer to FIG. 13 together with FIG. 14, which illustrates a charging operation of the charge compensation circuit 300. At the time point T.sub.A, the switch S.sub.A is turned off and the switch S.sub.B is turned on, and the voltage of the reference node N.sub.R is V.sub.B. At the time point T.sub.B, the switch S.sub.A is turned on and the switch S.sub.B is turned off, and the voltage of the reference node N.sub.R is V.sub.A. From the time point T.sub.A to T.sub.B where the reference node N.sub.R is switched from the lower voltage V.sub.B to the higher voltage V.sub.A, there is a small time period in which the compensation switch S.sub.1 is turned on, and meanwhile, the transmission switches S.sub.A and S.sub.B may be turned off. At this moment, the output capacitor C.sub.A may receive electric charges from the current source I.sub.1, and the amount of received electric charges may be determined based on the turned-on pulse length of the compensation switch S.sub.1. Subsequently, the switch S.sub.A is turned on and the switch S.sub.1 is turned off at the time point T.sub.B, and the reference node N.sub.R is coupled to the reference buffer BUF.sub.A for receiving the voltage V.sub.A. At this moment, the current source I.sub.1 may be cut off through the turned-off switch S.sub.1, in order to prevent redundant current consumption.

(47) In such a situation, the charge compensation circuit 300 may supply electric charges to the output capacitor C.sub.A (i.e., Q.sub.C) by charging the output capacitor C.sub.A with the current source I.sub.1, and the rest electric charges are received from the reference buffer BUF.sub.A. Therefore, the amount of electric charges required to be supplied from the reference buffer BUF.sub.A (i.e., Q.sub.R) may be reduced to the total amount of electric charges required for driving the output capacitor C.sub.A (i.e., Q.sub.A) minus the compensation electric charges supplied from the charge compensation circuit 300; that is, Q.sub.R=Q.sub.A−Q.sub.C. As a result, the reference buffer BUF.sub.A may not need to have larger output capability, so that the power consumption of the reference buffer BUF.sub.A may be reduced. Also, the settling speed of the voltages of the switched capacitor circuit 30 may be improved due to the strong output capability of the charge compensation circuit 300.

(48) Please continue to refer to FIG. 13 together with FIG. 15, which illustrates a discharging operation of the charge compensation circuit 300. At the time point T.sub.C, the switch S.sub.A is turned on and the switch S.sub.B is turned off, and the voltage of the reference node N.sub.R is V.sub.A. At the time point T.sub.B, the switch S.sub.A is turned off and the switch S.sub.B is turned on, and the voltage of the reference node N.sub.R is V.sub.B. From the time point T.sub.C to T.sub.B where the reference node N.sub.R is switched from the higher voltage V.sub.A to the lower voltage V.sub.B, there is a small time period in which the compensation switch S.sub.2 is turned on, and meanwhile, the transmission switches S.sub.A and S.sub.B may be turned off. At this moment, electric charges on the output capacitor C.sub.A may be released through the current source I.sub.2, and the amount of released electric charges may be determined according to the turned-on pulse length of the compensation switch S.sub.2. Subsequently, the switch S.sub.D is turned on and the switch S.sub.2 is turned off at the time point T.sub.D, and the reference node N.sub.R is coupled to the reference buffer BUF.sub.B for receiving the voltage V.sub.B. At this moment, the current source I.sub.2 may be cut off through the turned-off switch S.sub.2, in order to prevent redundant current consumption.

(49) In such a situation, the charge compensation circuit 300 may draw electric charges from the output capacitor C.sub.A (i.e., Q.sub.C) by discharging the output capacitor C.sub.A with the current source I.sub.2, and the rest electric charges are released through the reference buffer BUF.sub.B. Therefore, the amount of electric charges required to be released through the reference buffer BUF.sub.B (i.e., Q.sub.R) may be reduced to the total amount of electric charges required for driving the output capacitor C.sub.A (i.e., Q.sub.A) minus the compensation electric charges drawn by the charge compensation circuit 300; that is, Q.sub.R=Q.sub.A-Q.sub.C. As a result, the reference buffer BUF.sub.B may not need to have larger output capability, so that the power consumption of the reference buffer BUF.sub.B may be reduced. Also, the settling speed of the voltages of the switched capacitor circuit 30 may be improved due to the strong output capability of the charge compensation circuit 300.

(50) Please refer to FIG. 16, which is a schematic diagram of a general capacitive digital-to-analog converter (DAC) 1600. As shown in FIG. 16, the capacitive DAC 1600 is composed of a plurality of switched capacitor circuits, each of which includes an output capacitor (C.sub.AN−C.sub.A0) and two transmission switches (S.sub.NA−S.sub.0A, S.sub.NB−S.sub.0D). The switched capacitor circuit has a circuit structure similar to the switched capacitor circuit 10 as shown in FIG. 1. In detail, the first terminal of the output capacitor C.sub.AN−C.sub.A0 is commonly coupled to the output terminal of the capacitive DAC 1600. The transmission switches S.sub.NA−S.sub.0A are respectively coupled between the second terminal of the output capacitors C.sub.AN−C.sub.A0 and a first input terminal for receiving the voltage V.sub.A through a reference buffer (not illustrated in FIG. 16 for brevity). The transmission switches S.sub.NB−S.sub.OB are respectively coupled between the second terminal of the output capacitors C.sub.AN−C.sub.A0 and a second input terminal for receiving the voltage V.sub.B through another reference buffer (not illustrated in FIG. 16 for brevity). The transmission switches S.sub.NA−S.sub.0A and S.sub.NB−S.sub.OB allow the second terminal of the output capacitors C.sub.AN−C.sub.A0 to be switched between the voltages V.sub.A and V.sub.B. Taking the output capacitor C.sub.AN as an example, the second terminal of the output capacitor C.sub.AN is configured to receive the voltage V.sub.A when the switch S.sub.NA is turned on and the switch S.sub.NB is turned off, and configured to receive the voltage V.sub.B when the switch S.sub.NA is turned off and the switch S.sub.NB is turned on. The output terminal of capacitive DAC 1600 is further coupled to a reset terminal for receiving a reset voltage V.sub.RESET through a reset switch S.sub.RESET.

(51) In the capacitive DAC 1600, the capacitance values of the output capacitors C.sub.AN−C.sub.A0 are arranged to be binary weighted. In other words, the capacitance value of each output capacitor may be twice the capacitance value of its adjacent output capacitor (e.g., C.sub.AN=2×C.sub.A(N−1), C.sub.A(N−1)=2×C.sub.A(N−2), . . . , C.sub.A1=2×C.sub.A0). The input digital data may be converted into control signals for controlling the transmission switches S.sub.NA−S.sub.0A and S.sub.NB−S.sub.OB, to switch the voltages at the second terminal of the output capacitors C.sub.AN−C.sub.A0, which further couple the electric charges to their first terminal to generate the output voltage V.sub.OUT of the capacitive DAC 1600. In this example, the electric charges for voltage switching are entirely supplied from or released through the reference buffers that provide the voltages V.sub.A and V.sub.B, and these two reference buffers are shared by all of the switched capacitor circuits. Due to the great number of switched capacitor circuits driven by the reference buffers and the large capacitance values of the output capacitors under the binary weighted arrangement, the output capability of the reference buffers should be quite strong in order to satisfy the requirements of electric charge amount in the capacitive DAC 1600.

(52) Please refer to FIG. 17, which is a schematic diagram of a capacitive DAC 1700 according to an embodiment of the present invention. As shown in FIG. 17, the circuit structure of the capacitive DAC 1700 is similar to the circuit structure of the capacitive DAC 1600 shown in FIG. 16, so signals and elements having similar functions are denoted by the same symbols. The difference between the capacitive DAC 1700 and the capacitive DAC 1600 is that, in the capacitive DAC 1700, each switched capacitor circuit further includes a charge compensation circuit. The charge compensation circuit is coupled to the second terminal of the corresponding output capacitor C.sub.AN−C.sub.A0, for compensating electric charges for the output capacitor C.sub.AN−C.sub.A0.

(53) During the voltage switching operations, the charge compensation circuit may charge or discharge the output capacitor C.sub.AN−C.sub.A0 according to the voltage change. For example, when the output capacitor is switched from the lower voltage V.sub.B to the higher voltage V.sub.A, the charge compensation circuit is configured to supply electric charges from the first supply voltage V.sub.DD to charge the output capacitor. When the output capacitor is switched from the higher voltage V.sub.A to the lower voltage V.sub.B, the charge compensation circuit is configured to release electric charges to the second supply voltage V.sub.SS to discharge the output capacitor. As a result, partial of the electric charges are supplied from or released to the charge compensation circuit, and the output capability of the reference buffers may be reduced, which leads to less power consumption of the reference buffers. Also, the settling speed of the voltages of the switched capacitor circuit may be improved due to the strong output capability of the charge compensation circuit. Note that the detailed implementations and operations of the switched capacitor circuits of the capacitive DAC 1700 and the related charge compensation circuit are similar to those shown in FIGS. 3 and 4, and the embodiments for various implementations of the charge compensation circuit described in this disclosure are all applicable to the capacitive DAC 1700.

(54) Please note that the present invention aims at providing a switched capacitor circuit having a charge compensation circuit capable of supplying or releasing electric charges. Those skilled in the art may make modifications and alterations accordingly. For example, in the above embodiments, the electric charges of the charge compensation circuit are supplied from the first supply voltage V.sub.DD and released to the second supply voltage V.sub.SS. These supply voltages may be the highest or lowest voltage level supplied by the global voltage sources of the circuit system. In another embodiment, the supply voltages V.sub.DD and/or V.sub.SS may have any appropriate level generated from a specific voltage source or voltage generator. As long as the supply voltage is capable of compensating the required electric charges and the driving capability of the charge compensation circuit is strong enough, any appropriate voltage level may be feasible. Note that the steady state voltage of the reference node is received from the reference buffer, not determined by the charge compensation circuit.

(55) In addition, in the embodiments of the present invention, the first terminal of the output capacitor is coupled to the output terminal of the switched capacitor circuit and the capacitive DAC, and the second terminal of the output capacitor is coupled to the reference node, the transmission switches and the charge compensation circuit. In an exemplary embodiment, the top plate of the output capacitor may be implemented as its first terminal, and the bottom plate of the output capacitor may be implemented as its second terminal. Alternatively, the top plate of the output capacitor may be implemented as its second terminal, and the bottom plate of the output capacitor may be implemented as its first terminal.

(56) To sum up, the present invention provides a switched capacitor circuit having a charge compensation circuit capable of supplying or releasing electric charges, where the switched capacitor circuit is applicable to a capacitive DAC or any other circuit module. The charge compensation circuit may supply or release electric charges for the output capacitor of the switched capacitor circuit, where the electric charges may be pushed or pulled through the reference buffer originally. Therefore, the burden on the reference buffer may be reduced, which decreases the requirements of output capability of the reference buffer, so that the power consumption of the reference buffer may also be saved. In addition, due to the strong driving capability of the charge compensation circuit, the settling speed of the voltage of the output capacitor may be accelerated, which increases the operation speed of the switched capacitor circuit and the capacitive DAC.

(57) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.