Planarization of backside emitting VCSEL and method of manufacturing the same for array application

Abstract

A method of forming a flip chip backside Vertical Cavity Surface Emitting Laser (VCSEL) package comprising: forming a VCSEL pillar array; applying a dielectric layer to the VCSEL pillar array, the dielectric layer filling trenches in between pillars forming the VCSEL pillar array and covering the pillars; planarizing the VCSEL pillar array to remove the dielectric layer covering the pillars exposing a metal layer on a top surface of the pillars; applying a metal coating on the metal layer on a top surface of the pillars, the metal layer defining a contact pattern of the VCSEL pillar array; and applying solder on the metal coating to flip chip mount the VCSEL pillar array to a substrate package.

Claims

1. A method of forming a flip chip backside emitting Vertical Cavity Surface Emitting Laser (VCSEL) package comprising: forming a VCSEL pillar array comprising: forming a first mirror device on a substrate; forming an active layer applied directly on the first mirror device generating light; forming a second mirror device directly attached to the active layer; applying a metal layer on the second mirror device; and forming a plurality of pillars, wherein the second mirror device is directly attached to the active layer across an entire width of each pillar, each pillar exposing a portion of the first mirror device, the active region and the second mirror device, wherein each pillar has a diameter between 5-50 μm; applying a dielectric layer to the VCSEL pillar array, the dielectric layer filling trenches in between VCSEL pillars forming the VCSEL pillar array, covering the VCSEL pillars and the metal layer; planarizing the VCSEL pillar array to remove the dielectric layer covering the VCSEL pillars exposing the metal layer on a top surface of the VCSEL pillars; applying a metal coating on the metal layer on the top surface of the VCSEL pillars, the metal layer defining a contact pattern of the VCSEL pillar array, wherein the metal coating attaches a plurality of VCSEL pillars together, and applying solder on the metal coating to flip chip mount the VCSEL pillar array to a substrate package.

2. The method of claim 1, comprising forming electrical connections around a perimeter of the VCSEL pillar array connecting a back side of the substrate of the VCSEL array and the substrate package.

3. The method of claim 2, wherein forming the electrical connections comprises forming is at least one wrap around connection.

4. The method of claim 2, wherein forming the electrical connections comprises forming at least one conductive via.

5. The method of claim 1, wherein forming a VCSEL pillar array comprises forming a plurality of pillars by directional Inductive Coupled Plasma-Reactive Ion Etcher (ICP-RIE).

6. The method of claim 1, wherein the dielectric layer is one of a Polyimide, Benzocyclobutene (BCB) or a solvent based chemical dielectric film.

7. The method of claim 1, wherein planarizing the VCSEL pillar array to remove the dielectric layer covering the pillars comprises applying a chemical mechanical polishing (CMP) process to the VCSEL array, wherein the metal layer is a CMP index and polish stopper.

8. The method of claim 1, comprising attaching an optical accessory to a backside of the VCSEL array.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present application is further detailed with respect to the following drawings. These figures are not intended to limit the scope of the present application but rather illustrate certain attributes thereof. The same reference numbers will be used throughout the drawings to refer to the same or like parts.

(2) FIGS. 1A-1E are cross-sectional views showing exemplary embodiments of forming a VCSEL pillar array for flip chip mounting in accordance with one aspect of the present application; and

(3) FIGS. 2A-2B are cross-sectional views showing exemplary embodiments of forming a flip chip backside emitting VCSEL package using the VCSEL pillar array formed in FIGS. 1A-1E in accordance with one aspect of the present application.

DESCRIPTION OF THE APPLICATION

(4) The description set forth below in connection with the appended drawings is intended as a description of presently preferred embodiments of the disclosure and is not intended to represent the only forms in which the present disclosure can be constructed and/or utilized. The description sets forth the functions and the sequence of steps for constructing and operating the disclosure in connection with the illustrated embodiments. It is to be understood, however, that the same or equivalent functions and sequences can be accomplished by different embodiments that are also intended to be encompassed within the spirit and scope of this disclosure.

(5) Referring to FIGS. 1A-4B, an exemplary embodiment of a method for forming a flip chip backside emitting VCSEL package 10 may be seen. The VCSEL package 10 has multiple advantages over the prior art designs namely: (1) flip-chip configuration with one step reflow assembly process, (2) planarization of etched trenches forming a VCSEL array of the VCSEL package 10 for ease of subsequent photolithography and metal related manufacturing processes, and (3) backside illuminating VCSEL with options of aperture lens and other optical arrangements on the backside of the wafer. In accordance with one embodiment, the wavelength of the present embodiment of the VCSEL package 10 is 940 nm or 1120 nm or 1400 nm for 3D sensing applications or 980 nm for power applications such as fiber pump lasers.

(6) Referring to FIG. 1A, the VCSEL array 12 may be formed on a substrate 14. The substrate 14 may be a gallium arsenide (GaAs) substrate 14 or similar material. Materials 16 may be deposited on the substrate 14 to form the VCSEL array 12. In accordance with one embodiment, a pair of Distributed Braggs Reflectors (DBR) 18 and 20 may be formed on the substrate 14 and runs parallel to the substrate 14. The DBRs 18 and 20 may be formed of a plurality of layers. The DBRs 18 and 20 may be formed by disposing multiple layers of alternating materials with varying optical impedances. In general, the multiple layers alternate between high and low optical impedances.

(7) An active region 22 may be formed between the pair of DBRs 18 and 20. The active region 22 may be formed of one or more quantum wells for laser light generation. Metal contact layer 24 may be formed on the materials 16. In the present embodiment, the metal contact layer 24 may be formed on top of the DBR 18.

(8) The VCSEL array 12 may then be formed. The VCSEL array 12 may be formed in a manner described in co-pending patent application entitled “PILLAR CONFINED BACKSIDE ILLUMINATING VCSEL”, having Ser. No. 16/208,958, in the name of Yi-Ching Pao, Majid Riaziat, Ta-Chung Wu, Wilson Kyi and James Pao and which is incorporated herein by reference in its entirety.

(9) As may be seen in FIG. 1B, the VCSEL array 12 may be formed by etching a plurality of pillars 26. The pillars 26 may be isolated from one another by a trench 28 formed in between. The pillars 26 may be etched to a depth exposing a portion of the DBR 20, the active region 22 and the DBR 18. In the present embodiment, a highly directional ICP (Inductive Coupled Plasma) reactive ion etcher (RIE) may be used to etch highly anisotropic pillars 26. By using ICP-RIE, the pillars 26 may have a cylinder type of cross-sectional profile having close to straight side walls. In accordance with one embodiment, the pillars 26 may have a profile in the 5-50 μm diameter range. Etching by using ICP-RIE may be important since if wet chemical isotropic etchant is used, the side walls of the pillars 26 may be tapered which may present issues when small diameter VCSELs are to be fabricated. Thus, the pillars 26 should be etched by ICP-RIE with an anisotropic straight wall profile.

(10) A coating 30 may be applied to the VCSEL array 12. The coating 30 may be a spin-on glass dielectric such as Polyimide, Benzocyclobutene (BCB) or any solvent based chemical dielectric film. The coating 30 may be applied to flow into the trenches 28 and cover the etched surfaces of the pillars 26 forming the VCSEL array 12.

(11) A chemical mechanical polishing (CMP) process may be applied to the VCSEL array 12 as shown in FIG. 1D. The CMP process is a process of smoothing surfaces with the combination of chemical and mechanical forces. The CMP process may be used to expose the metal contacts 24. The metal contacts 24 may act as the polishing or etch stopper as shown in FIG. 1D.

(12) Once the surface of the VCSEL array 12 is CMP planarized exposing the metal contacts 24, an over coat of metal 32 may be deposited as shown in FIG. 1E. The over coat of metal 32 may serve as both electric and thermal connections and also as a solder adhesion base as will be described below.

(13) As shown in FIGS. 1E and 2A, once the surface of the VCSEL array 12 is CMP planarized, an over coat of metal 32 may be deposited to define a contact pattern 32A. Different groups of pillars 26 may be attached together to form the contact pattern 32A. In the present embodiment, all of the pillars 26 in an interior of the VCSEL array 12 may be coupled together, while the pillars 26 on the perimeter are not. As stated above, the contact pattern 32A may serve as both electric and thermal connections and also as a solder adhesion base.

(14) A solder or conductive epoxy 34 (hereinafter solder 34) may be applied to the contact pattern 32A as may be seen in FIG. 2B. The VCSEL array 12 may be flip-chip mounted to a package substrate 36 forming the backside emitting VCSEL package 10.

(15) Since the present embodiment is designed for backside illumination VCSEL, a flip-chip configuration may be required. In the prior art, the flip-chip mounting is based on dedicated solder bumps or solder over the VCSEL pillars or mesas which are placed over the VCSEL pillars (or mesas). In the present embodiment, the VCSEL array 12 has the solder coverage over the top of each and every VCSEL pillar 32. This is done by electric-chemical plating a thin layer of solder 34 such as Au—Sn on top of the contact pattern 32A, and then turn the VCSEL array 12 upside down to meet and join (through a furnace re-flow process) the receiving end of metal pads 38 on the package substrate 36 or heat sinking substrate side. The VCSEL array 12 may have an aperture lens and other optical arrangements 42 attached to the backside of the VCSEL array 12.

(16) The VCSEL package 10 may use a backside illuminating VCSEL array 12 configured in a flip-chip arrangement and may use electrical connections 40 such as vias or wrap around connections to reach the back side of the substrate 14, metal contacts and/or optical arrangement 42 without the need of any bond wires in the assembly and packaging process as described in co-pending patent application entitled “FLIP CHIP BACKSIDE EMITTING VCSEL PACKAGE”, having Ser. No. 16/239,083, in the name of Yi-Ching Pao and which is incorporated herein by reference in its entirety.

(17) The present embodiments describe a backside emitting VCSEL array 12 configured with Flip-chip arrangement plus the use of planarization of the etched trenches 30 in between the pillars 26 to ease the subsequent photolithography and metal deposition processes. Complete assembly to attach the VCSEL array 12 and make all needed electrical connections to the package substrate 36 may be done by a simple solder reflow process with solder tip “over” the VCSEL pillar 26 and also the electrical connections 40 such as vias or wrap around connections. This feature eliminates the need of a typical two-step process of die attach first and wire bonding the next, which simplify the assembly and packaging process into one re-flow process plus it can drastically reduce the footprint of the package size by eliminating the lengthy bond wires and extended bond pads outside the chip area. This arrangement greatly increases the yield of the packaged VCSEL array 12 and at the same time reduce the form factors and footprint of the VCSEL package 10 dramatically.

(18) The bond wire arrangement generally requires bond pads to extend outside the footprint of the VCSEL array 12. The bond wire arrangement may extend the footprint of the whole assembly by 2× the actual size of the VCSEL array 12 in any given dimension. Thus, in a two-dimensional (X and Y) arrangement this means the footprint of the VCSEL package 10 may be as large as 4× of the actual VCSEL array 12. This large footprint required by the prior art is a major concern in any space limited handheld applications such as handset and any mobile device.

(19) While embodiments of the disclosure have been described in terms of various specific embodiments, those skilled in the art will recognize that the embodiments of the disclosure may be practiced with modifications within the spirit and scope of the claims.