RECONFIGURABLE DEVICE BASED DEEP NEURAL NETWORK SYSTEM AND METHOD

Abstract

Provided herein in some embodiments is a deep neural network (DNN) system based on a reconfigurable device such as a field programmable gate arrays (FPGA) configured to use lesser computational resources when training a DNN while maintaining its performance and accuracy levels. Said DNN system may further be used to train a DNN in an increased, rapid pace hence providing real-time operation tailored to the various needs of the user. The reconfigurable device of said DNN system may be dynamically reprogrammed before or during training sessions, or, alternatively, may be programed “on-the-fly” before or during training sessions while adjusting its datapath in response to monitored operational parameters of the DNN system. Such datapath adjustments ensure that multiplications performed during convolution do not include data with under-threshold values, but rather only data with above-threshold value, thereby reducing processing time and computing resources as well as required memory bandwidth.

Claims

1. A reconfigurable device based deep neural network training acceleration system, comprising: (i) a reconfigurable device; (ii) a controller; (iii) a library; (iv) an HW configuration selector, wherein the HW configuration selector is configured to automatically select HW configurations from the library, wherein the controller is configured to control the running of a training dataset, wherein the system is reconfigured on-the-fly by using the selected HW configurations to modify the datapath of the reconfigurable device, and wherein said reconfiguration is adapted to a use-case to which said system is to be applied.

2-4. (canceled)

5. The system of claim 1 wherein the system is dynamically reconfigured.

6. The system of claim 5, wherein the dynamically reconfiguration of said system is driven by the model weight values.

7. The system of claim 1, wherein a training monitor sources HW configurations from the HW configuration selector in accordance with relation between performance and accuracy.

8. The system of claim 1, wherein the system further comprising a synthesizer configured to synthesize HW configurations to be stored in the library.

9. The system of claim 1, wherein the system further comprising a synthesizer configured to synthesize HW configurations that are not found in the library.

10. The system of claim 1, wherein the deep neural network architecture is configured to be altered by altering the physical configuration of the reconfigurable device.

11. The system of claim 1, wherein the selected HW configuration is predesigned.

12. The system of claim 1, wherein the deep neural network is a convolutional neural network.

13-14. (canceled)

15. The system of claim 1, wherein the selected HW configuration is a convolution layer.

16. The system of claim 1, wherein the selected HW configuration is a pooling layer.

17. The system of claim 1, wherein the selected HW configuration is a fully connected layer.

18. The system of claim 1, wherein the selected HW configuration is any feed forward layer.

19. The system of claim 1, wherein the selected HW configuration is any kind of deep neural network arrangement.

20. The system of claim 1, wherein several HW configurations are combined.

21. A method for applying sparse training acceleration using a reconfigurable device based deep neural network system, comprising the steps of: (i) generating multiple partial feature maps by applying each filter over a selected data element, (ii) repeating the process for each data element until all the feature maps have been completed, (iii) conducting unstructured sparse amplification of the kernels with the data elements, such that data elements or kernels with an under-threshold value are not multiplied.

22. The method of claim 21, wherein the steps are conducted following a selection of a predesigned sparse HW configuration.

23. The method of claim 21, wherein the steps are conducted following a selection of a sparse HW configuration synthesized on-the-fly.

24. The method of claim 21, wherein data elements or kernels with a value of zero are not multiplied.

25. The method of claim 21, wherein a training monitor monitors the neural network unstructured sparse training and in turn initiates the controller to determine the threshold value below it data elements or kernels are not multiplied.

26. The method of claim 21, wherein the data in the data elements is used to adjust the kernels in the deep neural network system.

27. The method of claim 21, wherein a controller determines whether to conduct step (iii) in accordance with the incidence of an under-threshold value in the kernels and/or data elements.

28. A method for applying normal training acceleration using a reconfigurable device based deep neural network system, comprising the steps of: (i) selecting a dataset in accordance with a predefined user criteria, (ii) selecting a HW configuration from a library and perform a training using a reconfigurable device, (iii) analyzing the training parameters using a training monitor.

29. The method of claim 28, wherein the system is dynamically reconfigured.

30. The method of claim 29, wherein the dynamically reconfiguration is driven by the model weight values.

31. The method of claim 28, wherein a training monitor sources HW configurations from the HW configuration selector in accordance with relation between performance and accuracy.

32. The method of claim 28, wherein the selected HW configuration is predesigned.

33. The method of claim 28, wherein the selected HW configuration is synthesized on-the-fly.

34. (canceled)

35. The method of claim 21, wherein the deep neural network is a convolutional neural network.

36. The method of claim 21, wherein the deep neural network is configured to process imaging data.

37. The method of claim 21, wherein the deep neural network is configured to process natural language data.

38. The method of claim 28, wherein training analysis results that indicates a convergence results in an accomplishment of the training session.

39. The method of claim 28, wherein training analysis results that indicates a lack of convergence triggers sending a request to a HW configuration selector to select HW configuration encoded in a greater or lesser detail.

40. The method in claim 39 wherein varying levels of detail refer to varying fixed point precision.

41. The method in claim 39 wherein varying levels of detail refer to varying sparsity threshold.

42-43. (canceled)

44. The system of claim 1, wherein the system is capable of synthesize new HW configurations in order to provide on-the-fly reconfiguration to the system, wherein said synthesized new HW configurations are used to modify the datapath of the reconfigurable device, and wherein said reconfiguration is adapted to a use-case to which said system is to be applied.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0044] Some embodiments of the invention are described herein with reference to the accompanying figures. The description, together with the figures, makes apparent to a person having ordinary skill in the art how some embodiments may be practiced. The figures are for the purpose of illustrative description and no attempt is made to show structural details of an embodiment in more detail than is necessary for a fundamental understanding of the invention.

[0045] In the Figures:

[0046] FIG. 1 constitutes a structure diagram illustrating an exemplary reconfigurable device based DNN system, according to some embodiments of the invention.

[0047] FIG. 2 constitutes a flowchart diagram illustrating a method of operation leading to two training modes, according to some embodiments of the invention.

[0048] FIG. 3 constitutes a flowchart diagram illustrating a normal training mode, according to some embodiment of the invention.

[0049] FIG. 4 constitutes a flow chart diagram illustrating the sub operations of operation 314, according to some embodiments of the invention.

[0050] FIG. 5 constitutes a flow chart diagram illustrating the sub operations of operation 304, according to some embodiments of the invention.

[0051] FIG. 6 constitutes a flow chart diagram illustrating the sub operations of operation 306, according to some embodiments of the invention.

[0052] FIG. 7 constitutes a flowchart diagram illustrating a sparse training mode, according to some embodiments of the invention.

DETAILED DESCRIPTION OF SOME EMBODIMENTS

[0053] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, and components, modules, units and/or circuits have not been described in detail so as not to obscure the invention. Some features or elements described with respect to one embodiment may be combined with features or elements described with respect to other embodiments. For the sake of clarity, discussion of same or similar features or elements may not be repeated.

[0054] Although embodiments of the invention are not limited in this regard, discussions utilizing terms such as, for example, “processing,” “computing,” “calculating,” “determining,” “establishing”, “analyzing”, “checking”, “setting”, “receiving”, or the like, may refer to operation(s) and/or process(es) of a controller, a computer, a computing platform, a computing system, or other electronic computing device, that manipulates and/or transforms data represented as physical (e.g., electronic) quantities within the computer's registers and/or memories into other data similarly represented as physical quantities within the computer's registers and/or memories or other information non-transitory storage medium that may store instructions to perform operations and/or processes.

[0055] Unless explicitly stated, the method embodiments described herein are not constrained to a particular order or sequence. Additionally, some of the described method embodiments or elements thereof can occur or be performed simultaneously, at the same point in time, or concurrently.

[0056] The term “Controller”, as used herein, refers to any type of computing platform or component that may be provisioned with a Central Processing Unit (CPU) or microprocessors, and may be provisioned with several input/output (I/O) ports, for example, a general-purpose computer such as a personal computer, laptop, tablet, mobile cellular phone, controller chip, SoC or a cloud computing system.

[0057] The term “Deep Neural Network” or DNN, as used herein, refers to a computer model that include connectionist systems that are inspired by, but not identical to, biological neural networks that constitute animal brains. A deep neural network can consist of multiple layers. The data elements which are the output of a given layer are typically the input of the following layer (though sometimes the output of given layer can also be used as an input of a deeper layer which is not the following one). A “Deep” neural network is a neural network which has at least one “hidden” layer. A hidden layer is a layer that has two properties: Its input is not the input of the system (but the output of other layer(s)); Its output is not the output of the system (but is used as an input to other layer(s)). The properties of a hidden layer typically mean the designer of the system does not know what the hidden layer represents in the calculation and “blindly trusts” the training process to “imbue something useful” into the layer.

[0058] The term “Convolutional Neural Network” or CNN, as used herein, refers to a DNN that has at least some convolutional layers. Each specific neuron in a convolutional layer does not use all the data elements in the input of the layer but only the data elements which are “closer” to it. All the neurons in the convolutional layer use an identical set of weights (cooperatively trained) while a given neuron multiplies a given data element by a weight which is a function of the “distance” between the data element and the neuron.

[0059] The term “Reconfigurable device” as used herein, refers to any semiconductor device designed to be reconfigured by a customer or a designer after manufacturing. In contrary to a typical ASIC (Application Specific Integrated Circuit), the reconfigurable device aims at providing the customer or the designer with significant flexibility of its configuration allowing wide diversity of possible logic functions performed in the device. For example, a semiconductor device that comprises some portion that behaves like a typical ASIC and another portion that aims at the above is a reconfigurable device according to the definition used herein.

[0060] The term “FPGA” as used herein, refers to a Field-Programmable Gate Array which is a semiconductor device having an integrated circuit and based around a matrix of configurable logic blocks (CLBs) connected via programmable interconnects. An FPGA is designed to be configured by a customer or a designer after manufacturing.

[0061] The term “CPLD” as used herein, refers to Complex Programmable Logic Device which is a semiconductor device designed to be configured by a customer or a designer after manufacturing. A CPLD typically offers lower flexibility of its configuration due to its lower amount of logic components compared to a FPGA, but has an advantage of having more deterministic timing and simpler synthesis process.

[0062] The term “Kernel” as used herein, refers to a parameterized representation of a surface in the space that can have many forms. Kernels may be used in deep neural network layers to extract features. For example, in a convolutional neural network used for image processing the kernels might represent filters applied on a small region of an image.

[0063] The term “Data elements” as used herein, refers to any kind of data or partial data that can be evaluated and processed through DNN. A data element may comprise of data pertaining to an image data element, a voice data element, etc.

[0064] The term “Hardware (HW) configuration” as used herein, refers to a series of hardware blocks comprising the network, that may be physically altered or modified in different ways and can be evaluated and processed through DNN. For example, a reconfigurable device such as a FPGA may have various HW configurations.

[0065] The term “On-the-fly” as used herein, refers to a single or continuous event along a timeline. For example, a reconfiguration that can be a single or continuous event performed on-the-fly, may be performed at any given time slot before or during a dataset running time, either as a separate event or as a part of a sequence of events, sporadic or continuous.

[0066] The term “Loss function” as used herein, refers to a function internally used by a deep learning machine in order to quantify how good its solution is. It is defined so that it has a gradient as a function of each of the learning parameters (Kernel elements). The gradient indicates the direction to which the parameters have to be tuned in order to improve the solution.

[0067] Training DNNs may be computationally intensive and time consuming which may prove costly to a network user. In an effort to overcome this problem, the present invention discloses a DNN system based on a reconfigurable device such as a field programmable gate arrays (FPGA), or complex programmable logic device (CPLD) or any other reconfigurable device that may reduce the length of training sessions as well as computational intensiveness while generating an error margin equal to or below an acceptable predetermined threshold.

[0068] The present invention further discloses a reconfigurable device such as, but not limited to, a FPGA that may be dynamically reprogrammed before or during training sessions. Alternatively, reconfigurable device may be programed “on-the-fly” before or during training sessions. According to some embodiments, these programming or reprograming procedures adjust the reconfigurable device's datapath in response to monitored operational parameters of the DNN and/or based on predefined user criteria which may include information associated with the network geometry, one or more user selected datasets, cost considerations etc.

[0069] Reference is now made to FIG. 1 which schematically illustrates an exemplary reconfigurable device based DNN system, that can be, according to some embodiments of the invention, a FPGA based DNN system 10. As shown, FPGA DNN system 10 may include a HW Configuration Selector (HCS) 100, an FPGA deep Neural Network chip (FPGA DNN) 102, a Controller (CTLR) 104, a Memory (MEM) 106, a Library (LIB) 108, and a Training Monitor (TM) 110. Optionally, FPGA DNN system 10 may further include a Sparse Module (SPAR) 112 and a Synthesizer (SYNTH) 114.

[0070] According to some embodiments, FPGA DNN system 10 may process input data and generate output data which, for example, may be associated with diverse applications. Such applications may include image processing comprising: object detection, object segmentation, motion detection, face recognition, image restoration, scene labelling, image classification, action recognition, human pose estimation, document analysis etc., Natural language processing comprising: speech recognition, natural language translation, question answering, named entity recognition, sentiment analysis, topic recognition, text classification etc., as well as systems and methods for recommendation, customer relationship management, fraud detection, drug discovery etc.

[0071] According to some embodiments, FPGA DNN system 10 may further include a dataset comprising data elements such as image data elements, speech data elements etc.

[0072] According to some embodiments, reconfiguring of the FPGA DNN system 10 may include automatically selecting predesigned HW configurations that are stored in the system. According to some embodiments, said selected predesigned HW configurations may then be used to modify the datapath of the FPGA DNN system 10.

[0073] According to some embodiments, the selected HW configurations may not be predesigned but rather be synthesized “on-the-fly”. In order to achieve this ability, SYNTH 114 that may be included in the FPGA DNN system 10, may be used to automatically synthesize HW configurations which are not predesigned and are not already found in the LIB 108. These synthesized HW configurations may then be optionally added to the LIB 108 to form a part of its regular collection. According to some embodiments, SYNTH 114 may use a similar method used to create the predesign HW configurations.

[0074] According to some embodiments, the LIB 108 may store the collection of predesigned HW configurations and/or the selected HW configurations synthesized “on-the-fly”. Optionally, the LIB 108 may include a sparse library which may store a collection of predesigned sparse HW configurations and/or sparse HW configurations synthesized “on-the-fly”, which may be used during sparse amplification (disclosed hereinafter). These sparse HW configurations may be used to modify (reprogram) the datapath of the FPGAs so that multiplications performed during convolution do not include data with under-threshold values, for example, a zero value, but rather only data with above-threshold value, for example, a non-zero value.

[0075] According to some embodiments, The HCS 100 may select predesigned or synthesized “on-the-fly” HW configurations from the LIB 108 which may be used to adjust the size and weights of the network kernels.

[0076] The HCS 100 may select the HW configurations upon a request from the TM 110 and based on the TM's 110 monitoring of the operational parameters of the FPGA DNN system 10. According to some embodiments, in the HW configuration selection procedure, the HCS 100 may take into consideration the predefined user criteria.

[0077] According to some embodiments, the TM 110 may monitor the operational parameters of the FPGA DNN system 10 and may take into account, in its request for an HW configuration from the HCS 100, tradeoffs between network speed and network accuracy, in other words, the TM 110 may take into account the relations between the performance and precision of FPGA DNN system 10's operation.

[0078] For example, if the TM 110 determines that the network is stable using 16 bit FP encoding but that the speed of the network may be increased without making the network unstable and/or where the error at the output of one or more layers, or at the output layer, exceeds a predetermined, maximum acceptable error threshold, the TM 110 may request from the HCS 100 to select a HW configuration with lower precision encoding (for example, fixed point precision encoding), for example, 8 bit FP encoding. If the 8 bit FP encoding causes instability or a large error, the TM 110 may request from the HCS 100 to select a HW configuration encoded using a precision (for example, fixed point precision encoding) between 8 bit FP and 16 bit FP, for example 12 bit FP.

[0079] According to some embodiments, The FPGA DNN system 10 may be an FPGA CNN (convolution neural network) system 10, and FPGA DNN 102 may be FPGA CNN 102 chip that may include a convolutional neural network architecture while its geometry may be defined based on the predefined user criteria and in accordance to changing needs and various conditions.

[0080] According to some embodiments, associated with the FPGA DNN system 10 is the MEM 106 which may be used to store the dataset information for each FPGA DNN chip 102. The MEM 106 may comprise a DDR memory, or any other types of a suitable memory components.

[0081] According to some embodiments, the operation of the FPGA DNN system 10 may be controlled by the CTRL 104 which may dynamically adjust the datapath of the FPGA DNN chip 102 during training sessions according to the coding parameters of the data cell selected by the HCS 100. According to some embodiments, the CTRL 104 may control the operation of the FPGA DNN system 10 in two different modes of training, “normal training mode” and “sparse training mode”.

[0082] Reference is now made to FIG. 2 which constitutes a flowchart diagram illustrating a method of operation leading to two training modes, according to some embodiments of the invention. As shown, operation 200 may include using the CTRL 104 to check the distribution of zero and non-zero values in the kernels and optionally in the data elements selected.

[0083] Operation 202 may include determining if the number of zero's values in the kernels and/or the selected data elements are equal to or exceeds a predetermined threshold, if the number of said zero's values exceeded said predetermined threshold, operation 204 may include using the CTRL 104 to select running the sparse mode of training. If the number of zero's values did not exceed said predetermined value, operation 206 may include using the CTRL 104 to select running the normal mode of training (said two modes of training are described in greater detail in FIGS. 3 and 7, respectively).

[0084] Reference is now made to FIG. 3 which is an exemplary flow chart of the normal training mode, according to some embodiments of the invention. For clarity purposes the normal training mode is described herein with reference to a FPGA CNN system which is often used to process imaging data, whereas the present invention may apply to any reconfigurable DNN system. The skilled person may appreciate that the exemplary flow chart shown is for illustrative purpose and that the normal training mode executed by said FPGA CNN system may be practiced using more or less operations and/or a different sequence of operations.

[0085] As shown, in operation 300, the dataset selected by the user that can be, for example, a part of a predefined user criteria, may be downloaded to the MEM 106 where it may be accessed by the FPGA CNN chip 102. According to some embodiments, only a portion of the dataset may be downloaded to the MEM 106 or alternatively, the whole dataset may be downloaded. Each FPGA CNN chip 102 in the FPGA CNN system 10 may access all the dataset stored in the MEM 106 or may, alternatively, be limited to accessing only specific predetermined areas of the dataset.

[0086] In operation 302, the HCS 100 may select a predesigned or synthesized “on-the-fly” HW configuration, (such as a HW configuration configured for image processing) from the LIB 108. According to some embodiments, in a first training run, the HCS 100 may select the HW configuration based on the predetermined user criteria.

[0087] In operation 304, the CTLR 104 may program the FPGA CNN 102 in the FPGA CNN system 10 based on the parameters of the selected HW configuration. A first training run may then be executed through the FPGA CNN system 10. The operational parameters of the network may be monitored by the TM 110 in real-time, or alternatively may be monitored following the training run as part of the next operation.

[0088] In operation 306 the TM 110 may evaluate the monitored operational parameters of the network and may determine whether or not another training run should be performed. The TM 110 may perform a tradeoff analysis to determine the relations between network speed and network accuracy taking into account, among other factors, the user requirements in order to attempt achieving an optimum balance between performance and accuracy.

[0089] In operation 308, the TM 110 may evaluate if the network has converged and if the optimum speed and accuracy have been achieved in accordance with the user requirements and possibly other factors. If yes, then the network has been optimally trained and the training session may be stopped. If not, the TM 110 may send a request to the HCS 100 to select a HW configuration which may be encoded with a greater or lesser precision depending on the results of the TM's 110 evaluation of the monitored operational parameters.

[0090] For example, and according to some embodiments, the TM 110 may send a request to the HCS 100 to select a 16 bit FP encoded HW configuration configured for image processing if the first training run was based on an 8 bit FP encoded HW configuration and the monitored operating parameters (i.e. the network performance) did not meet the network requirements. In another example, the TM 110 may send a request to the HCS 100 to select a 16 bit FP encoded HW configuration configured for image processing if the first training run was based on a 32 bit FP encoded HW configuration and the monitored operating parameters (i.e. the network performance) have exceeded network requirements.

[0091] According to some embodiments, if the network did not reach convergence, operation 308 of the normal training mode may use the HCS 100 to repeat operation 302, or alternatively, move forward to operation 310 that may use the HCS 100 to check the LIB 108 to see if there is a stored HW configuration which may conform to the TM's 110 request. If yes, the HCS 100 may select said HW configuration, taking into consideration, among other factors, the predefined user criteria, and may initiate an iterative process which may take the network a number of times through operation 302 to 306 until convergence is achieved. If there is no stored HW configuration in the LIB 108, the FPGA CNN system 10 may either do nothing or, alternately consider synthesizing an HW configuration as part of operation 312 further disclosed below.

[0092] In operation 312, the system may evaluate whether to synthesize a HW configuration. According to some embodiments, synthesizing an HW configuration may be done if an HW configuration which does not appear in the LIB 108 is frequently requested during training sessions. According to some embodiments, if an HW configuration is seldom requested, it may be preferable to not synthesize the HW configuration and to do nothing.

[0093] In operation 314, the HW configuration may be synthesized resulting in a new HW configuration which may be optionally stored in the LIB 108 for repeated use, such as, repeating operation 302 to select HW configuration from LIB 108 and so on until reaching convergence.

[0094] Reference is now made to FIG. 4 which constitutes a flow chart diagram illustrating the sub operations of operation 314, according to some embodiments of the invention. As shown, in operation 400a the requirements for a desired HW configuration are sent from the CTRL 104, in operation 400b the properties of a desired HW configuration are gathered. As said, a desired HW configuration may be an HW configuration that is frequently requested during training sessions. According to some embodiments, operations 400a and 400b may be executed simultaneously or at a different time frame from each other.

[0095] In operation 402 a synthesis of a new HW configuration is performed using the SYNTH 114, resulting in operation 404 that may optionally store the new HW configuration in the LIB 108 for repeated use.

[0096] Reference is now made to FIG. 5 which constitutes a flow chart diagram illustrating the sub operations of operation 304, according to some embodiments of the invention. As shown, in operation 500, FPGA CNN system 10 selects a subset of the dataset. in operation 502, the chosen subset is used as the input to the first layer of the FPGA CNN 102. in operation 504 the layer is applied over its input to calculate the output and so on until reaching the last layer. In operation 506, FPGA CNN system 10 checks if the last layer has undergone the aforementioned operations, if yes, a loss function is calculated as part of operation 508, if no, operation 510 is applied. In operation 510, FPGA CNN system 10 uses the output of the previous layer(s) as an input for the next layer and then repeats operation 504 and so on.

[0097] In operation 512 FPGA CNN system 10 calculates the gradient of the loss function. In operation 514, FPGA CNN 102 uses the gradient as the input to the last layer. In operation 516, FPGA CNN system 10 applies the gradient over the kernel of the layer. In operation 518, FPGA CNN system 10 checks if the first layer has undergone the aforementioned operations successively, if yes, the training iteration is complete as part of operation 520, if no, FPGA CNN system 10 back propagates the gradients through the layer to set an output as part of operation 522.

[0098] In operation 524, FPGA CNN system 10 uses the output of the following layer(s) as an input to yet to come following layers and in turn repeats operation 516 and so on.

[0099] Reference is now made to FIG. 6 which constitutes a flow chart diagram illustrating the sub operations of operation 306, according to some embodiments of the invention. As shown, in operation 600 FPGA CNN system 10 checks the number of iterations have reached target value. If the target value has not been achieved, FPGA CNN system 10 continues to perform iteration until reaching target value as part of operation 602, if target value is achieved, FPGA CNN system 10 checks the trend of loss function over a validation dataset as part of operation 604. FPGA CNN system 10 may also check the distribution of kernel elements in the layer(s) as part of operation 606. FPGA CNN system 10 may also check the distribution of data elements through the system as part of operation 608. According to some embodiments, operations 604, 606 and 608 may be executed simultaneously or at a different time frame from each other. In operation 610, FPGA CNN system 10 delivers metrics to the CTRL 104 to perform decisions.

[0100] Reference is now made to FIG. 7 which is an exemplary flow chart of the sparse training mode, according to some embodiments of the invention. For clarity purposes the sparse training mode is described herein with reference to a FPGA CNN system which is mainly used to process imaging data whereas the present invention may apply to any reconfigurable DNN system. The skilled person may appreciate that the exemplary flow chart shown is for illustrative purpose and that the sparse training mode executed by said FPGA CNN system may be practiced using more or less operations and/or a different sequence of operations.

[0101] According to some embodiments, sparse amplification may sometimes be used in training a FPGA CNN, in particular when there are many under-threshold values, for example, zero values in the selected data element and/or the kernel. According to some embodiments, as part of said sparse amplification, a tradeoff may be made between memory bandwidth and processing time by first generating multiple partial feature maps by convolving each filter with the selected data element on a same location on the data element, and successively repeating the process for each data element until all the feature maps have been completed.

[0102] According to some embodiments, when multiplying a kernel with a data element as part of conducting sparse amplification, data with a value under a certain threshold, for example, a zero, in either the kernel or the data element is not multiplied, that is, only data with value over a certain threshold, for example, non-zero, in both the data element and the kernel are multiplied, thereby reducing processing time and computing resources. Additional processing time may be gained by not accessing from MEM 106 to retrieve kernel data and/or data of a selected data element with a value under a certain threshold, for example, a zero.

[0103] According to some embodiments, using said method of sparse amplification, in exchange for gaining processing time, memory bandwidth is sacrificed as partial sums for each convolved location on the selected data element requires storing in MEM 106 (for each partial feature map).

[0104] According to some embodiments, addresses which contain data values under a certain threshold, for example, a zero, are not accessed to reduce processing time. This may be implemented, for example, by having the kernel decoder transmit to the CTRL 104 the location of values under a certain threshold, for example, a zero, so as to reduce the need to access the corresponding locations on the image (and inversely by having the image data element decoder transmit to the CTRL 104 the location of values under a certain threshold, for example, a zero).

[0105] As shown, in operation 700a, following determination that the sparsity ratio (number of multiplications of data with values under a certain threshold, for example, a zero, out of a total number of multiplications of data having zero and non-zero values between the kernel data and the image data) is equal to or greater than a predetermined threshold, the HCS 100 may select a predesigned sparse HW configuration that optimally fits the sparsity ratio encountered, from the sparse library in LIB 108. According to some embodiments, operation 700b may be executed by the CTRL 104 accessing and retrieving the kernel data from the MEM 106. According to some embodiments, operation 700c may be executed by the CTRL 104 accessing and retrieving the image data element the MEM 106.

[0106] According to some embodiments, operations 700a 700b and 700c may be executed simultaneously or at a different time frame from each other. According to some embodiments, HCS 100 may select an HW configuration that is synthesized “on-the-fly” such that it optimally fits the sparsity ratio encountered, from the sparse library in LIB 108.

[0107] In operation 702, a determination may be made if the data in the HW configuration and/or the kernel is encoded. In a case the data is encoded, it is decoded as part of operation 704, prior to proceeding to the next operation. In a case the data is not encoded, the process may proceed to the next operation.

[0108] In operation 706, a partial feature map may be generated for a given location on the image by multiplying (convolving) the kernels having values over a certain threshold, for example non-zero, with corresponding image data element having values over a certain threshold, for example, non-zero, at the same location. If a kernel value is under a certain threshold, for example, a zero, and/or an image data element value is under a certain threshold, for example, a zero, these are not multiplied together as their multiplication will yield an under a certain threshold value or a zero. According to some embodiments, not multiplying said kernel and/or image data element with one another may reduce processing time and save computing resources.

[0109] In operation 708, the data calculated in operation 706 for the partial feature map may be stored in MEM 106.

[0110] In operation 710, operations 706 and 708 may be repeated for each filter (kernel) to generate a plurality of partial feature maps for the same image location. The data calculated for each partial feature map may be stored in MEM 106.

[0111] In operation 712, operation 706, 708 and 710 may be repeated for another location on the image data element.

[0112] In operation 714, operation 712 may be repeated until all locations in the image data element have been convolved.

[0113] In operation 716, upon completion of a feature map, the data may be written into the MEM 106 for further processing by the FPGA CNN system 10.

[0114] According to some embodiments, during both normal and sparse training modes, the data in the data elements may be used to adjust the kernels in the FPGA CNN system 10 and may include a collection of samples of encoded data of varying sizes and precision. According to some embodiments, associated with each encoded data sample are compressed weight parameters which may then be used to adjust the kernels (kernel size and weights) during training.

[0115] For example, and according to some embodiments, HW configurations configured for image processing may include 32 bit floating point compressed weights for performing a 3×3 convolution on a 500 pixel size image data elements. A second HW configurations configured for image processing may include 32 bit floating point compressed weights for performing a 5×5 convolution on a 2000 pixel size image data elements. A third HW configurations configured for image processing may include 16 bit floating point compressed weights for performing a 3×3 convolution on a 5000 pixel size image data elements. A fourth HW configurations configured for image processing may include 16 bit floating point compressed weights for performing a 1×1 convolution on a 4000 pixel size image data elements. A fifth HW configurations configured for image processing may include 16 bit floating point compressed weights for performing a 1×1 convolution on a 400 pixel size image and may additionally include 32 bit floating point compressed weights for performing a 3×3 convolution on a 1000 pixel size image data elements, and so on.

[0116] According to some embodiments, the information associated with the geometry of the FPGA CNN 102 may include the number of layers, the types of layers, the number of filters, the depth of the filters, the number of feature maps, convoluting parameters such as padding and/or strides, among other various network geometry information.

[0117] According to some embodiments, the dataset information may be obtained from existing dataset sources. Examples of such dataset sources may include, for image classification, CIFAR10, CIFAR100, and ImageNet, among other datasets known in the art.

[0118] According to some embodiments, the monitored operational parameters of FPGA CNN 102 may include operational parameters such as, for example, error measured on each layer output in last/recent operations, distribution of parameters per layer, distribution of parameters derivative (over time) per layer, distribution of parameters variance (over some time) per layer, convergence rate in last/recent operations, as measured by various loss functions at the end of the neural network, amount of fixed-point overflow and underflow encountered per layer in last/recent operations, current epoch (i.e. how many sweeps of the entire dataset have passed through the system), amount of objects per class in dataset, error measurement per class, and error measurement on class-pairs that passed together through the neural network.

[0119] Although the present invention has been described with reference to specific embodiments, this description is not meant to be construed in a limited sense. Various modifications of the disclosed embodiments, as well as alternative embodiments of the invention will become apparent to persons skilled in the art upon reference to the description of the invention. It is, therefore, contemplated that the appended claims will cover such modifications that fall within the scope of the invention.