Power amplifier linearization circuit and related apparatus

Abstract

A power amplifier linearization circuit and related apparatus is provided. In examples disclosed herein, the power amplifier linearization circuit includes an analog pre-distortion (APD) circuit coupled to an input of a power amplifier. Notably, the power amplifier can exhibit linearity response deviation, namely linearity amplitude response deviation and linearity phase response deviation, when amplifying a radio frequency (RF) signal under a compression condition. As such, the APD circuit is configured to receive a control signal corresponding to the linearity response deviation and pre-process the RF signal based on the control signal before providing the RF signal to the power amplifier. As a result, it may be possible to reduce the linearity response deviation in the power amplifier, thus helping to improve linearity and RF performance of the power amplifier.

Claims

1. A power amplifier linearization circuit comprising: a signal input that receives a radio frequency (RF) signal; a signal output that outputs the RF signal to a power amplifier configured to amplify the RF signal to generate an amplified RF signal; and an analog pre-distortion (APD) circuit coupled between the signal input and the signal output, the APD circuit configured to: receive a control signal corresponding to a linearity response deviation that comprises an amplitude response deviation and a phase response deviation of the power amplifier; and process the RF signal based on the control signal to reduce the linearity response deviation.

2. The power amplifier linearization circuit of claim 1 wherein the APD circuit is further configured to process the RF signal to reduce the amplitude response deviation and the phase response deviation.

3. The power amplifier linearization circuit of claim 1 wherein: the amplitude response deviation comprises a positive amplitude response deviation and the phase response deviation comprises a positive phase response deviation; and the APD circuit is further configured to process the RF signal to reduce the positive amplitude response deviation and the positive phase response deviation.

4. The power amplifier linearization circuit of claim 1 further comprising: a control circuit coupled to the APD circuit and configured to generate the control signal comprising a control voltage in response to receiving a trigger voltage; and a detection circuit coupled between the control circuit and the power amplifier and configured to: detect the linearity response deviation of the power amplifier; and generate the trigger voltage in response to detecting the linearity response deviation.

5. The power amplifier linearization circuit of claim 4 wherein the detection circuit comprises a transistor-based diode coupled between the control circuit and the power amplifier, the transistor-based diode configured to become conductive in response to the linearity response deviation to generate the trigger voltage.

6. The power amplifier linearization circuit of claim 5 wherein the detection circuit further comprises a resistor-capacitor (RC) circuit coupled between the control circuit and the transistor-based diode, the RC circuit configured to output the trigger voltage within a defined triggering bandwidth.

7. The power amplifier linearization circuit of claim 5 wherein the detection circuit is further configured to adjust the trigger voltage prior to providing the trigger voltage to the control circuit.

8. The power amplifier linearization circuit of claim 4 wherein the control circuit comprises: a transistor network coupled to the detection circuit and configured to output an initial control voltage in response to receiving the trigger voltage; and a voltage divider coupled between the transistor network and the APD circuit, the voltage divider configured to divide the initial control voltage to generate the control voltage.

9. The power amplifier linearization circuit of claim 4 wherein the APD circuit comprises: a transistor coupled between the signal input and the signal output, the transistor comprising a base electrode coupled to the control circuit to receive the control voltage; and a capacitor coupled in parallel to the transistor between the signal input and the signal output.

10. A power amplifier apparatus comprising: a power amplifier configured to amplify a radio frequency (RF) signal to generate an amplified RF signal; and a power amplifier linearization circuit comprising: a signal input that receives the RF signal; a signal output that outputs the RF signal to the power amplifier; and an analog pre-distortion (APD) circuit coupled between the signal input and the signal output, the APD circuit configured to: receive a control signal corresponding to a linearity response deviation that comprises an amplitude response deviation and a phase response deviation of the power amplifier; and process the RF signal based on the control signal to reduce the linearity response deviation.

11. The power amplifier apparatus of claim 10 wherein the APD circuit is further configured to process the RF signal to reduce the amplitude response deviation and the phase response deviation.

12. The power amplifier apparatus of claim 10 wherein: the amplitude response deviation comprises a positive amplitude response deviation and the phase response deviation comprises a positive phase response deviation; and the APD circuit is further configured to process the RF signal to reduce the positive amplitude response deviation and the positive phase response deviation.

13. The power amplifier apparatus of claim 10 wherein the power amplifier linearization circuit further comprises: a control circuit coupled to the APD circuit and configured to generate the control signal comprising a control voltage in response to receiving a trigger voltage; and a detection circuit coupled between the control circuit and the power amplifier and configured to: detect the linearity response deviation of the power amplifier; and generate the trigger voltage in response to detecting the linearity response deviation.

14. The power amplifier apparatus of claim 13 wherein the detection circuit is coupled between the control circuit and an output stage of the power amplifier.

15. The power amplifier apparatus of claim 14 wherein the detection circuit comprises a transistor-based diode coupled between the control circuit and the output stage of the power amplifier, the transistor-based diode configured to become conductive in response to the linearity response deviation to generate the trigger voltage.

16. The power amplifier apparatus of claim 15 wherein the detection circuit further comprises a resistor-capacitor (RC) circuit coupled between the control circuit and the transistor-based diode, the RC circuit configured to output the trigger voltage within a defined triggering bandwidth.

17. The power amplifier apparatus of claim 13 wherein the detection circuit is further configured to adjust the trigger voltage prior to providing the trigger voltage to the control circuit.

18. The power amplifier apparatus of claim 13 wherein the control circuit comprises: a transistor network coupled to the detection circuit and configured to output an initial control voltage in response to receiving the trigger voltage; and a voltage divider coupled between the transistor network and the APD circuit, the voltage divider configured to divide the initial control voltage to generate the control voltage.

19. The power amplifier apparatus of claim 18 wherein the transistor network comprises at least two transistors coupled in parallel between the detection circuit and the voltage divider.

20. The power amplifier apparatus of claim 13 wherein the APD circuit comprises: a transistor coupled between the signal input and the signal output, the transistor comprising a base electrode coupled to the control circuit to receive the control voltage; and a capacitor coupled in parallel to the transistor between the signal input and the signal output.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

(2) FIG. 1A is a schematic diagram of an exemplary power amplifier;

(3) FIG. 1B is a schematic diagram providing an exemplary illustration of an output stage of the power amplifier of FIG. 1A;

(4) FIG. 1C is a graphic diagram providing an exemplary illustration of a load line corresponding to the power amplifier of FIG. 1A;

(5) FIG. 1D is a graphic diagram providing an exemplary illustration of characteristics of the power amplifier of FIG. 1A when operating as a class-A power amplifier;

(6) FIG. 1E is a graphic diagram providing an exemplary illustration of characteristics of the power amplifier of FIG. 1A when operating as a class-AB power amplifier under a compression condition;

(7) FIGS. 1F and 1G are graphic diagrams providing exemplary illustrations of linearity amplitude response deviation and linearity phase response deviation that may result from the power amplifier of FIG. 1A operating under the compression condition of FIG. 1E;

(8) FIG. 2A is a schematic diagram of an exemplary power amplifier apparatus including a power amplifier and a power amplifier linearization circuit configured to reduce linearity response deviation of the power amplifier;

(9) FIG. 2B is a schematic diagram providing an exemplary detailed illustration of the power amplifier apparatus of FIG. 2A;

(10) FIG. 3 is a graphic diagram providing an exemplary illustration of a quantitative relation between a control voltage generated by the power amplifier linearization and an output voltage at the output stage of the power amplifier in the power amplifier apparatus of FIGS. 2A and 2B;

(11) FIG. 4A is a schematic diagram of an exemplary power amplifier apparatus configured according to another embodiment of the present disclosure;

(12) FIG. 4B is a schematic diagram providing an exemplary detailed illustration of the power amplifier apparatus of FIG. 4A;

(13) FIG. 5 is a schematic diagram of an exemplary power amplifier linearization circuit configured according to another embodiment of the present disclosure; and

(14) FIGS. 6A-6D are graphic diagrams providing exemplary illustrations of linearity and error vector magnitude (EVM) improvements that may be achieved by the power amplifier linearization circuits of FIGS. 2A, 4A, and 5.

DETAILED DESCRIPTION

(15) The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

(16) It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

(17) It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

(18) Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

(19) The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

(20) Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

(21) Embodiments of the disclosure relate to a power amplifier linearization circuit and related apparatus. In examples disclosed herein, the power amplifier linearization circuit includes an analog pre-distortion (APD) circuit coupled to an input of a power amplifier. Notably, the power amplifier can exhibit linearity response deviation, namely linearity amplitude response deviation and linearity phase response deviation, when amplifying a radio frequency (RF) signal under a compression condition. As such, the APD circuit is configured to receive a control signal corresponding to the linearity response deviation and pre-process the RF signal based on the control signal before providing the RF signal to the power amplifier. As a result, it may be possible to reduce the linearity response deviation in the power amplifier, thus helping to improve linearity and RF performance of the power amplifier.

(22) Before discussing the power amplifier linearization circuit of the present disclosure, a brief overview of an exemplary power amplifier is first provided with reference to FIGS. 1A-1G to help explain certain key characteristics and operational principles of the power amplifier. The discussion of specific exemplary aspects of a power amplifier linearization circuit configured according to the present disclosure starts next with reference to FIG. 2A.

(23) FIG. 1A is a schematic diagram of an exemplary power amplifier 10. The power amplifier 10 is configured to amplify an RF signal 12 based on a bias voltage V.sub.BIAS and a supply voltage V.sub.CC to generate an amplified RF signal 14 having a higher power than the RF signal 12.

(24) The power amplifier 10 can include a single stage (e.g., an output stage) or multiple stages (e.g., a driver stage and an output stage). In this regard, FIG. 1B is a schematic diagram providing an exemplary illustration of an output stage 16 in the power amplifier 10 of FIG. 1A. Common elements between FIGS. 1A and 1B are shown therein with common element numbers and will not be re-described herein.

(25) In a non-limiting example, the output stage 16 includes a transistor 18, such as a bipolar junction transistor (BJT), having a base electrode B, a collector electrode C, and an emitter electrode E. Notably, the transistor 18 may also be a field-effect transistor (FET). Accordingly, the base electrode B, the collector electrode C, and the emitter electrode E may also be referred to as a gate electrode, a drain electrode, and a source electrode, respectively. The base electrode B may be coupled to a supply rail 20 via a bias resistor R.sub.B. The collector terminal C may be coupled to the supply rail 20 via a load resistor R.sub.L. The emitter terminal E may be coupled to a ground rail 22.

(26) The transistor 18 receives the bias voltage V.sub.BIAS between the base terminal B and the emitter terminal E. In this regard, the bias voltage V.sub.BIAS is equivalent to a base-emitter voltage V.sub.BE. The supply voltage V.sub.CC is applied between the supply rail 20 and the ground rail 22. As such, the supply voltage V.sub.CC is equivalent to a collector-emitter voltage V.sub.CE.

(27) The transistor 18 is in an active state when the base-emitter voltage V.sub.BE is greater than zero and less than the collector-emitter voltage V.sub.CE (V.sub.CE>V.sub.BE>0). When the transistor 18 is in the active state, a collector-emitter current I.sub.C is proportional to a base current I.sub.B. In this regard, the transistor 18 is in a linear state, thus causing the power amplifier 10 to operate as a linear device.

(28) The transistor 18 is in a saturation state when the base-emitter voltage V.sub.BE is greater than the collector-emitter voltage V.sub.CE (V.sub.BE>V.sub.CE). When the transistor 18 is in the saturation state, the transistor 18 acts like a short circuit, thus allowing the collector-emitter current I.sub.C to flow freely from the collector terminal C to the emitter terminal E. In this regard, the power amplifier 10 produces a maximum collector-emitter current I.sub.C.

(29) The transistor 18 is in a cut-off state when the collector-emitter voltage V.sub.CE is greater than the base-emitter voltage V.sub.BE (V.sub.BE<V.sub.CE). When the transistor 18 is in the cut-off state, the transistor 18 acts like an open circuit, thus preventing the collector-emitter current I.sub.C from flowing from the collector terminal C to the emitter terminal E. In this regard, the collector-emitter current I.sub.C is at a minimum level.

(30) The active state, the saturation state, and the cut-off state of the power amplifier 10 can be visualized using a load line plot. In this regard, FIG. 1C is a graphic diagram providing an exemplary illustration of a load line 24 corresponding to the power amplifier 10 of FIG. 1A. As discussed below, the power amplifier 10 can be configured to operate in different states by moving a bias point (also known as quiescent point or Q-point) of the power amplifier 10 along the load line 24. The power amplifier 10 operates in the saturation state when the Q-point of the power amplifier 10 is set at a saturation point 26.

(31) The power amplifier 10 operates in the linear state when the Q-point of the power amplifier 10 is set at a middle point 28 of the load line 24. Accordingly, the power amplifier 10 can be said to operate in a class-A mode or referred to as a class-A power amplifier.

(32) The power amplifier 10 operates in the cut-off state when the Q-point of the power amplifier 10 is set at a cut-off point 30. Accordingly, the power amplifier 10 can be said to operate in a class-B mode or referred to as a class-B power amplifier.

(33) Notably, when the Q-point of the power amplifier 10 is set between the middle point 28 and the cut-off point 30 on the load line 24, the power amplifier 10 can be said to operate in a class-AB mode or referred to as a class-AB power amplifier.

(34) FIG. 1D is a graphic diagram providing an exemplary illustration of characteristics of the power amplifier 10 of FIG. 1A when operating as a class-A power amplifier. Common elements between FIGS. 1C and 1D are shown therein with common element numbers and will not be re-described herein.

(35) When the power amplifier 10 is operating in the class-A mode, the Q-point of the power amplifier 10 is set at the middle point 28 along the load line 24. In this regard, the power amplifier 10 operates as a linear device and the amplified RF signal 14 in FIG. 1A is linearly proportional to the RF signal 12 in FIG. 1A. Given that the power amplifier 10 never drives the amplified RF signal 14 beyond the saturation point 26 and the cut-off point 30, the amplified RF signal 14 will not be compressed or clipped. As such, the power amplifier 10 can effectively suppress out-of-band spectral regrowth and/or in-band interference. As a result, the power amplifier 10 can operate with desirable adjacent channel power ratio (ACPR) and error vector magnitude (EVM). Notably, the improved linearity performance comes at the expense of reduced power amplifier efficiency (PAE). The PAE of the power amplifier 10 is typically below 25% in the class-A mode.

(36) In contrast, the power amplifier 10 can achieve an enhanced possible PAE when operating in the class-B mode. However, in the class-B mode, the power amplifier 10 will no longer operate as a linear device. As a result, the power amplifier 10 can suffer a significant degradation in ACPR and EVM. In this regard, the class-AB mode is often seen as a trade-off configuration between the class-A mode and the class-B mode.

(37) FIG. 1E is a graphic diagram providing an exemplary illustration of characteristics of the power amplifier 10 of FIG. 1A when operating as a class-AB power amplifier. Common elements between FIGS. 1C and 1E are shown therein with common element numbers and will not be re-described herein.

(38) In the class-AB mode, the Q-point of the power amplifier 10 is set between the middle point 28 and the cut-off point 30 along the load line 24. In this regard, the power amplifier 10 will neither offer the linearity performance of the class-A mode nor achieve the PAE of the class-B mode. As shown in FIG. 1E, the amplified RF signal 14 is no longer a replica of the RF signal 12 due to amplitude clipping. As such, the power amplifier 10 is said to be under a compression condition when operating in the class-AB mode.

(39) When operating under the compression condition, the power amplifier 10 can exhibit linearity amplitude response deviation and linearity phase response deviation. In this regard, FIGS. 1F and 1G are graphic diagrams providing exemplary illustrations of the linearity amplitude response deviation and the linearity phase response deviation that may result from the power amplifier 10 of FIG. 1A operating under the compression condition of FIG. 1E.

(40) FIG. 1F illustrates a linearity amplitude response curve 32. In a non-limiting example, the linearity amplitude response curve 32 exhibits a positive linearity response deviation from an ideal flat amplitude response curve 34 when the amplified RF signal 14 in FIG. 1A is above a certain output power threshold (e.g., 5 dBm). For example, when the output power is above 5 dBm, the linearity amplitude response curve 32 can have a 0.7 dB amplitude response deviation from the ideal flat amplitude response curve 34.

(41) FIG. 1G illustrates a linearity phase response curve 36. Similar to the linearity amplitude response curve 32 in FIG. 1F, the linearity phase response curve 36 exhibits a positive linearity phase deviation from an ideal flat phase response curve 38 when the amplified RF signal 14 in FIG. 1A is above a certain power threshold (e.g., 5 dBm). For example, when the output power is above 5 dBm, the linearity phase response curve 36 can have a 12° phase response deviation from the ideal flat phase response curve 38.

(42) As discussed above, the class-AB mode of operation represents a trade-off between linearity and RF performance of the power amplifier 10 of FIG. 1A. However, when the power amplifier 10 operates in the class-AB mode under the compression condition, the power amplifier 10 may experience the linearity amplitude response deviation and the linearity phase response deviation as shown in FIGS. 1F and 1G. Given that the linearity amplitude response deviation and the linearity phase response deviation can contribute to potential EVM degradation, it may be desirable to reduce the linearity amplitude response deviation and the linearity phase response deviation to help improve linearity and RF performance of the power amplifier 10.

(43) In this regard, FIG. 2A is a schematic diagram of an exemplary power amplifier apparatus 40 including a power amplifier 42 and a power amplifier linearization circuit 44 configured to reduce a linearity response deviation of the power amplifier 42. The power amplifier 42 is configured to amplify an RF signal 46 to generate an amplified RF signal 48. In a non-limiting example, the power amplifier 42 is a multi-stage power amplifier including a driver stage 50 configured to receive the RF signal 46 and an output stage 52 configured to output the amplified RF signal 48. It should be appreciated that the power amplifier linearization circuit 44 can also effectively reduce the linearity response deviation when the power amplifier 42 is a single-stage power amplifier.

(44) Notably, the power amplifier 42 may experience the linearity response deviation as previously discussed in FIGS. 1F and 1G. In this regard, the power amplifier linearization circuit 44 is configured to include an APD circuit 54 to help reduce the linearity response deviation of the power amplifier 42. More specifically, the APD circuit 54 is configured to reduce a positive amplitude response deviation between the linearity amplitude response curve 32 and the ideal flat phase response curve 38 in FIG. 1F as well as a positive phase response deviation between the linearity phase response curve 36 and the ideal flat phase response curve 38 in FIG. 1G.

(45) The power amplifier linearization circuit 44 can be configured to include a signal input 56 and a signal output 58. The signal input 56 may be coupled to a transceiver circuit (not shown) to receive the RF signal 46. The signal output 58 may be coupled to the driver stage 50 to output the RF signal 46 to the power amplifier 42. In a non-limiting example, the APD circuit 54 is provided in front of the driver stage 50 of the power amplifier 42 and between the signal input 56 and the signal output 58. As discussed in detail below, the APD circuit 54 is configured to receive a control signal 60, which can include a control voltage V.sub.CTRL that is quantitatively related to the linearity response deviation of the power amplifier 42. Accordingly, the APD circuit 54 is configured to process the RF signal 46 based on the control voltage V.sub.CTRL to cause the linearity response deviation to be reduced at the output stage 52 of the power amplifier 42.

(46) Moreover, studies have shown that the APD circuit 54 is able to respond to the linearity response deviation in a timely fashion (e.g., <1 μs) and can handle a wider modulation bandwidth (e.g., up to 1 GHz). By providing the APD circuit 54 in front of the power amplifier 42 to pre-process the RF signal 46 prior to amplification, it may be possible to respond to the linearity response deviation in a timely manner, thus helping to improve linearity and EVM of the power amplifier 42.

(47) The power amplifier linearization circuit 44 can be configured to include a detection circuit 62 and a control circuit 64. The detection circuit 62 is coupled to the output stage 52 of the power amplifier 42. The control circuit 64 is coupled between the detection circuit 62 and the APD circuit 54. The detection circuit 62 is configured to detect the linearity response deviation at the output stage 52 of the power amplifier 42 and generate a trigger voltage V.sub.TG in response to detecting the linearity response deviation. The control circuit 64 is configured to receive the trigger voltage V.sub.TG from the detection circuit 62. Accordingly, the control circuit 64 generates the control voltage V.sub.CTRL to cause the APD circuit 54 to respond to the linearity response deviation detected by the detection circuit 62.

(48) FIG. 2B is a schematic diagram providing an exemplary detailed illustration of the power amplifier apparatus 40 of FIG. 2A. Common elements between FIGS. 2A and 2B are shown therein with common element numbers and will not be re-described herein.

(49) In a non-limiting example, the detection circuit 62 includes a capacitor C.sub.A, a transistor-based diode Q.sub.1, and a resistor R.sub.A. The transistor-based diode Q.sub.1 and the resistor R.sub.A are coupled in series between the output stage 52 and a coupling node A. Specifically, the transistor-based diode Q.sub.1 includes a source electrode S.sub.1 coupled to the output stage 52 of the power amplifier 42, a drain electrode D.sub.1 coupled to the resistor R.sub.A, and a gate electrode G.sub.1 coupled to the drain electrode D.sub.1. The capacitor C.sub.A is coupled in parallel to the transistor-based diode Q.sub.1. The capacitor C.sub.A and the resistor R.sub.A collectively form a resistor-capacitor (RC) circuit 66.

(50) In the same non-limiting example, the control circuit 64 includes resistors R.sub.1, R.sub.2, R.sub.3, R.sub.4, R.sub.5, R.sub.6, and R.sub.7 as well as transistors Q.sub.2 and Q.sub.3. The resistor R.sub.1 is coupled between the coupling node A and a battery voltage V.sub.BAT. The transistor Q.sub.2 has a gate electrode G.sub.2 coupled to the coupling node A, a drain electrode D.sub.2 coupled to the battery voltage V.sub.BAT via the resistor R.sub.2, and a source electrode S.sub.2 coupled to a ground via the resistor R.sub.3. The transistor Q.sub.3 has a gate electrode G.sub.3 coupled to the source electrode S.sub.2 of the transistor Q.sub.2, a drain electrode D.sub.3 coupled to the battery voltage V.sub.BAT via the resistor R.sub.4, and a source electrode S.sub.3 coupled to the ground via the resistor R.sub.5. The transistors Q.sub.2 and Q.sub.3 collectively form a transistor network 68. The resistors R.sub.6 and R.sub.7 are coupled in series to form a voltage divider 70 between the drain D.sub.3 of the transistor Q.sub.3 and the ground.

(51) In the same non-limiting example, the APD circuit includes resistors R.sub.8, R.sub.9, transistor Q.sub.4, and capacitor C.sub.B. The transistor Q.sub.4 has a gate electrode G.sub.4 coupled to the voltage divider 70, a drain electrode D.sub.4 coupled to the signal input 56, and a source electrode S.sub.4 coupled to the signal output 58. The capacitor C.sub.B is coupled in parallel to the transistor Q.sub.4 between the signal input 56 and the signal output 58. The resistor R.sub.8 is coupled between the source electrode S.sub.4 and the ground. The resistor R.sub.9 is coupled between the drain electrode D.sub.4 and the ground.

(52) When the linearity response deviation occurs at the output stage 52 of the power amplifier 42, an output voltage V.sub.OUT at the output stage 52 moves progressively lower as an output power P.sub.OUT at the output stage 52 increases. The decreasing output voltage V.sub.OUT causes the transistor-based diode Q.sub.1 to become conductive to reduce the trigger voltage V.sub.TG at the coupling node A. The RC circuit 66 in the detection circuit 62 is configured to set a cut-off frequency (also known as corner frequency) well below a carrier frequency of the amplified RF signal 48. Accordingly, the RC circuit 66 can output the trigger voltage V.sub.TG to the transistor network 68 within a defined triggering bandwidth (e.g., up to 1 GHz) that corresponds to a modulation bandwidth of the power amplifier 42.

(53) The decreased trigger voltage V.sub.TG, in turn, causes the transistors Q.sub.2 and Q.sub.3 in the transistor network 68 to be turned on. Notably, the transistor Q.sub.2 is included in the transistor network 68 to prevent the transistor Q.sub.3 from being prematurely turned on. When the transistors Q.sub.2 and Q.sub.3 are turned on, the transistor network 68 generates an initial control voltage V′.sub.CTRL across the voltage divider 70. The voltage divider 70 may be configured to divide the initial control voltage V′.sub.CTRL to generate the control voltage V.sub.CTRL.

(54) The control circuit 64 can be configured to generate the control voltage V.sub.CTRL that is quantitively related to the output voltage V.sub.OUT at the output stage 52 of the power amplifier 42. In this regard, FIG. 3 is a graphic diagram providing an exemplary illustration of a quantitative relation between the control voltage V.sub.CTRL and the output voltage V.sub.OUT at the output stage 52 of the power amplifier 42 in the power amplifier apparatus 40 of FIGS. 2A and 2B.

(55) The quantitative relation between the control voltage V.sub.CTRL and the output voltage V.sub.OUT can be set based on a voltage correlation curve 72. For example, the control voltage V.sub.CTRL can be generated at approximately 0.7 V, 0.6 V, and 0.35 V, respectively, when the output voltage V.sub.OUT is approximately at 0.4 V, 0.8 V, and 1.5 V.

(56) With reference back to FIG. 2B, the transistor Q.sub.4 in the APD circuit 54 is controlled by the control voltage V.sub.CTRL that is quantitatively related to the output voltage V.sub.OUT. As a result, the transistor Q.sub.4 can effectively adjust the RF signal 46 to help reduce the linearity response deviation at the output stage 52 of the power amplifier 42. Notably, the transistor Q4 can have approximately 10Ω of on-resistance for 100 micrometer (μm) of gate periphery. The capacitor C.sub.B, on the other hand, can be configured to have approximately 40Ω of reactance. Due to the higher impedance of the capacitor C.sub.B, it may be possible to reduce the size of the transistor Q.sub.4, thus helping to reduce insertion loss of the APD circuit 54. Although the transistor-based diode Q.sub.1 and the transistors Q.sub.2, Q.sub.3, and Q.sub.4 are shown herein as FETs, it should be appreciated that the transistor-based diode Q.sub.1 and the transistors Q.sub.2, Q.sub.3, and Q.sub.4 can also be BJTs.

(57) The power amplifier 42 can also be configured to operate as a differential power amplifier to amplify the RF signal 46, as discussed next in FIGS. 4A and 4B. In this regard, FIG. 4A is a schematic diagram of an exemplary power amplifier apparatus 40A configured according to another embodiment of the present disclosure. Common elements between FIGS. 2A and 4A are shown therein with common element numbers and will not be re-described herein.

(58) The power amplifier apparatus 40A includes a power amplifier 42A and a power amplifier linearization circuit 44A. The power amplifier 42A is a differential power amplifier that includes an input stage 50A and an output stage 52A. It should be appreciated that the power amplifier linearization circuit 44A can also effectively reduce the linearity response deviation when the power amplifier 42A is a single-stage power amplifier. In this regard, the power amplifier apparatus 40A further includes an input balun 74 coupled between the APD circuit 54 and the input stage 50A. The input balun 74 is configured to convert the RF signal 46 into a plus RF signal 46P and a minus RF signal 46M. The power amplifier 42A amplifies the plus RF signal 46P and the minus RF signal 46M to generate an amplified plus RF signal 48P and an amplified minus RF signal 48M. The power amplifier apparatus 40A further includes an output balun 76 coupled to the output stage 52A. The output balun 76 is configured to convert the amplified plus RF signal 48P and the amplified minus RF signal 48M into the amplified RF signal 48.

(59) The power amplifier linearization circuit 44A includes a detection circuit 62A coupled to the output stage 52A. The detection circuit 62A is configured to detect the linearity response deviation at the output stage 52A based on the amplified plus RF signal 48P and the amplified minus RF signal 48M. Accordingly, the detection circuit 62A generates the trigger voltage V.sub.TG to cause the control circuit 64 to generate the control voltage V.sub.CTRL.

(60) FIG. 4B is a schematic diagram providing an exemplary detailed illustration of the power amplifier apparatus 40A of FIG. 4A. Common elements between FIGS. 2A, 2B, 4A, and 4B are shown therein with common element numbers and will not be re-described herein.

(61) In a non-limiting example, the detection circuit 62A includes a plus capacitor C.sub.AP, a minus capacitor C.sub.AM, a transistor-based plus diode Q.sub.1P, a transistor-based minus diode Q.sub.1M, a plus resistor R.sub.AP, and a minus resistor R.sub.AM. The transistor-based plus diode Q.sub.1P and the plus resistor R.sub.AP are coupled in series between the output stage 52A and a coupling node A. Specifically, the transistor-based plus diode Q.sub.1P includes a source electrode S.sub.1P coupled to the output stage 52A of the power amplifier 42A, a drain electrode D.sub.1P coupled to the plus resistor R.sub.AP, and a gate electrode G.sub.1P coupled to the drain electrode D.sub.1P. The plus capacitor C.sub.AP is coupled in parallel to the transistor-based plus diode Q.sub.1P. The plus capacitor C.sub.AP and the plus resistor R.sub.AP collectively form a plus RC circuit 66P.

(62) Similarly, the transistor-based minus diode Q.sub.1M and the minus resistor R.sub.AM are coupled in series between the output stage 52 and a coupling node A. Specifically, the transistor-based minus diode Q.sub.1M includes a source electrode S.sub.1M coupled to the output stage 52A of the power amplifier 42A, a drain electrode D.sub.1M coupled to the minus resistor R.sub.AM, and a gate electrode G.sub.1M coupled to the drain electrode D.sub.1M. The minus capacitor C.sub.AM is coupled in parallel to the transistor-based minus diode Q.sub.1M. The minus capacitor C.sub.AM and the minus resistor R.sub.AM collectively form a minus RC circuit 66M. Although the transistor-based plus diode Q.sub.1P and the transistor-based minus diode Q.sub.1M are shown herein as FETs, it should be appreciated that the transistor-based plus diode Q.sub.1P and the transistor-based minus diode Q.sub.1M can also be BJTs.

(63) The power amplifier linearization circuit 44 of FIG. 2B and the power amplifier linearization circuit 44A of FIG. 4B can be further configured to adjust the trigger voltage V.sub.TG in a controllable fashion. In this regard, FIG. 5 is a schematic diagram of an exemplary power amplifier linearization circuit 44B configured according to another embodiment of the present disclosure. Common elements between FIGS. 2B, 4B, and 5 are shown therein with common element numbers and will not be re-described herein.

(64) The power amplifier linearization circuit 44B includes a detection circuit 62B, which further includes resistors R.sub.CP, R.sub.CM and capacitors C.sub.CP, C.sub.CM configured as illustrated in FIG. 5. The detection circuit 62B may be configured to adjust the trigger voltage V.sub.TG prior to providing the trigger voltage V.sub.TG to the control circuit 64.

(65) The power amplifier linearization circuit 44 of FIG. 2A, the power amplifier linearization circuit 44A of FIG. 4A, and the power amplifier linearization circuit 44B of FIG. 5 can effectively reduce the linearity response deviation to improve linearity and EVM of the power amplifier 42 of FIG. 2A and the power amplifier 42A of FIG. 4A. In this regard, FIGS. 6A-6D are graphic diagrams providing exemplary illustrations of linearity and EVM improvements that may be achieved by the power amplifier linearization circuit 44 of FIG. 2A, the power amplifier linearization circuit 44A of FIG. 4A, and the power amplifier linearization circuit 44B of FIG. 5.

(66) FIG. 6A includes a number of dotted line curves 78D, 80D, and 82D indicative of the amplitude response deviations at different frequencies without analog pre-distortion, and a number of solid line curves 78S, 80S, and 82S indicative of respective amplitude response deviations with analog pre-distortion. For example, the solid line curve 78S indicates a substantial improvement in the amplitude response deviation compared to the respective dotted line curve 78D.

(67) FIG. 6B includes a number of dotted line curves 84D, 86D, and 88D indicative of the phase response deviations at different frequencies without analog pre-distortion, and a number of solid line curves 84S, 86S, and 88S indicative of respective phase response deviations with analog pre-distortion. For example, the solid line curve 84S indicates substantial improvement in the phase response deviation compare to the respective dotted line curve 84D.

(68) FIG. 6C includes a number of curves 90, 92, and 94 indicative of the EVMs at different frequencies without analog pre-distortion. FIG. 6D includes a number of curves 90A, 92A, and 94A indicative of respective EVMs without analog pre-distortion. For example, the curve 90A indicates substantial EVM reduction compare to the corresponding curve 90.

(69) Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.