ZERO-DELAY PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER BASED ON MULTI-STAGE SYNCHRONIZATION

Abstract

Disclosed is a zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization, which belongs to the technical field of integrated circuits. The zero-delay phase-locked loop frequency synthesizer comprises: a phase frequency detector, a charge pump, a loop pass filter, a voltage control oscillator and a multi-stage synchronization divider, wherein the phase frequency detector, the charge pump, the loop pass filter and the voltage control oscillator are connected in sequence; an output OUT of the voltage control oscillator is connected to an input IN of the multi-stage synchronization divider; and an output OUT of the multi-stage synchronization divider is connected to an input IN of the phase frequency detector, so as to form a feedback path.

Claims

1. A zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization, comprising a phase frequency detector, a charge pump, a loop pass filter, a voltage control oscillator and a multi-stage synchronization divider, wherein an output OP end of the phase frequency detector is connected with an input IP end of the charge pump, an output ON end of the phase frequency detector is connected with an input IN end of the charge pump, an output end of the charge pump is connected with an input end of the loop pass filter, an output end of the loop pass filter is connected with an input end of the voltage control oscillator, an output end of the voltage control oscillator is connected with an input end of the multi-stage synchronous divider, and an output end of the multi-stage synchronous divider is connected with an input IN end of the phase frequency detector to form a feedback path;

2. The zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization according to claim 1, wherein the multi-stage synchronization divider adopts a PS counter structure which specifically comprises a dual-modulus divider, a P counter, an S counter, a first clock synchronization module SYN1, a second clock synchronization module SYN2 and a third clock synchronization module SYN3; the output end of the voltage control oscillator is simultaneously connected with an input end a of the dual-modulus divider, an synchronization end c of the first clock synchronization module SYN1 and an synchronization end c of the third clock synchronization module SYN3; an output end b of the dual-modulus divider is connected with an input end a of the first clock synchronization module SYN1, and an output end b of the first clock synchronization module SYN1 is simultaneously connected with an input end a of the S counter, an input end a of the P counter and an synchronization end c of the second clock synchronization module SYN2; an output end b of the S counter is connected to a mode switch end c of the dual-modulus divider, and an output end b of the P counter is connected to an input end a of the second clock synchronization module SYN2, an output end b of the second clock synchronization module SYN2 is connected to an input end a of the third clock synchronization module SYN3, and an output end b of the third clock synchronization module SYN3 is connected to an input IN end of the phase frequency detector; an output signal CLK_VCO of the voltage control oscillator is further connected to the synchronization end c of the synchronization module SYN1 and the synchronization end c of the synchronization module SYN3.

3. The zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization according to claim 1, wherein the output clock signal CLK_VCO of the voltage control oscillator is input to the multi-stage synchronization divider, and a clock signal CLK1 obtained by frequency division by the dual-modulus divider is input to the first clock synchronization module SYN1; the first clock synchronization module SYN1 takes CLK_VCO as a trigger clock to obtain an output signal CLK2, which is input to the P counter and the S counter; the S counter outputs a MC signal, the P counter outputs a pulse signal CLK3; the pulse signal CLK3 is input to the second clock synchronization module SYN2 to obtain an output signal CLK4; the pulse signal CLK4 is input to the third clock synchronization module SYN3 to obtain CLK_DIV; the CLK_DIV is input into the phase frequency detector (PFD), and is compared with a reference clock CLK_REF in terms of phase.

4. The zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization according to claim 3, wherein a delay T.sub.syn1 of the first clock synchronization module SYN1, a delay T.sub.syn2 of the second clock synchronization module SYN2 and a delay T.sub.CLK_VCO of the voltage control oscillator satisfy:
T.sub.syn1+T.sub.syn2<T.sub.CLK_VCO.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0011] FIG. 1 is a schematic diagram of a traditional phase-locked loop circuit;

[0012] FIG. 2 is a schematic diagram of a traditional zero-delay phase-locked loop frequency synthesizer;

[0013] FIG. 3 is a schematic diagram of a signal of each point of the traditional zero-delay phase-locked loop frequency synthesizer;

[0014] FIG. 4 is a schematic diagram of an improved zero-delay phase-locked loop frequency synthesizer;

[0015] FIG. 5 is a schematic diagram of a signal of each point of the improved zero-delay phase-locked loop frequency synthesizer of the present disclosure;

[0016] FIG. 6 shows the application of the present disclosure to a multi-channel transceiver system.

DESCRIPTION OF EMBODIMENTS

[0017] For an ideal divider, its input and output clock signals are naturally consistent in phase. However, in the actual circuit, any module will have a certain delay. In the present disclosure, the influence of this delay is minimized. In order to make the purpose and effect of the present disclosure clearer, the present disclosure will be further explained in detail with reference to the drawings. It should be appreciated that what is described herein is only for explaining the present disclosure, rather than to limit the present disclosure.

[0018] FIGS. 1-3 show the traditional zero-delay phase-locked loop frequency synthesizer circuit, which realizes the phase consistency between the output clock signal and the input reference clock signal through the adjustable delay unit, so as to achieve the purpose of zero delay.

[0019] FIG. 4 is a schematic diagram of an improved zero-delay phase-locked loop frequency synthesizer. Different from the traditional PLL system, the first clock synchronization module SYN1, the second clock synchronization module SYN2 and the third clock synchronization module SYN3 are added to the PLL frequency synthesizer. The PLL frequency synthesizer specifically includes a phase frequency detector, a charge pump, a loop pass filter, a voltage control oscillator and a multi-stage synchronization divider, wherein an output OP end of the phase frequency detector is connected with an input IP end of the charge pump, an output ON end of the phase frequency detector is connected with an input IN end of the charge pump, an output end of the charge pump is connected with an input end of the loop pass filter, an output end of the loop pass filter is connected with an input end of the voltage control oscillator, an output end of the voltage control oscillator is connected with an input end of the multi-stage synchronous divider, and an output end of the multi-stage synchronous divider is connected with an input IN end of the phase frequency detector to form a feedback path.

[0020] In the synthesizer, the multi-stage synchronization divider adopts a PS counter structure, and specifically comprises a dual-modulus divider, a P counter, an S counter, a first clock synchronization module SYN1, a second clock synchronization module SYN2 and a third clock synchronization module SYN3; the output end of the voltage control oscillator is simultaneously connected with an input end a of the dual-modulus divider, an synchronization end c of the first clock synchronization module SYN1 and an synchronization end c of the third clock synchronization module SYN3; an output end b of the dual-modulus divider is connected with an input end a of the first clock synchronization module SYN1, and an output end b of the first clock synchronization module SYN1 is simultaneously connected with an input end a of the S counter, an input end a of the P counter and an synchronization end c of the second clock synchronization module SYN2; an output end b of the S counter is connected to a mode switch end c of the dual-modulus divider, and an output end b of the P counter is connected to an input end a of the second clock synchronization module SYN2, an output end b of the second clock synchronization module SYN2 is connected to an input end a of the third clock synchronization module SYN3, and an output end b of the third clock synchronization module SYN3 is connected to an input IN end of the phase frequency detector; an output signal CLK_VCO of the voltage control oscillator is further connected to the synchronization end c of the synchronization module SYN1 and the synchronization end c of the synchronization module SYN3.

[0021] Firstly, the output clock signal CLK_VCO of the voltage control oscillator is input into a multi-stage synchronization divider, and is divided by a dual-modulus divider, in which a large number of nonlinear delays are accumulated. The CLK_VCO input to the dual-modulus divider is divided to obtain a clock signal CLK1, which is then input to the first clock synchronization module SYN1; the first clock synchronization module SYN1 takes the CLK_VCO as a trigger clock to obtain an output signal CLK2, so that the output signal CLK2 and CLK_VCO are edge-aligned. The CLK2 is then input into a P counter and an S counter; when the S counter counts to a set value, it outputs a MC signal to the dual-modulus divider to change its frequency dividing ratio; the P counter continues counting until the P counter counts to the set value and outputs a pulse signal CLK3; the pulse signal CLK3 is input to the second clock synchronization module SYN2 to obtain an output signal CLK4. The second clock synchronization module SYN2 uses CLK1 as a trigger clock, so that its output signal CLK4 is edge-aligned with the output signal CLK1 of the first clock synchronization module SYN1. The pulse signal CLK4 is input to the third clock synchronization module SYN3 to obtain CLK_DIV, and the third clock synchronization module SYN3 uses the CLK_VCO as the trigger clock again, so that its output signal CLK_DIV and CLK_VCO are edge-aligned, that is, they are consistent in phase. The CLK_DIV is input into a phase frequency detector (PFD), and compared with a reference clock CLK_REF. After the loop is locked, the two are consistent in phase, and the CLK_VCO with the same phase as CLK_DIV is naturally consistent with CLK_REF in phase, thus realizing a zero-delay phase-locked loop frequency synthesizer.

[0022] FIG. 5 is a schematic signal diagram of the zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization according to the present disclosure. CLK_VCO will accumulate a certain delay T.sub.delay1 after passing through the dual-modulus divider, which makes CLK1 and CLK_VCO have a certain phase difference. In the first clock synchronization module SYN1, after the synchronization of CLK_VCO, CLK2 is aligned with CLK_VCO again. However, due to the non-ideality of the circuit, the first clock synchronization module SYN1 itself also has a time delay, namely T.sub.syn1, but it is obvious that T.sub.syn1<<Tdelay1. When CLK2 is input to the P counter again, a large amount of delay T.sub.delay2 will be accumulated there, so the delay between CLK3 and CLK_VCO is T.sub.syn1+T.sub.delay2. In the second clock synchronization module SYN2, the CLK4 is aligned with CLK2, so the delay between CLK4 and CLK_VCO is reduced to T.sub.syn1+T.sub.syn2. Similarly, since T.sub.syn2<<T.sub.delay2, then T.sub.syn1+T.sub.syn2<<T.sub.syn1+T.sub.delay2. CLK4 is synchronized with CLK_VCO in the third clock synchronization module SYN3, so that CLK4 and CLK_VCO are aligned, and there is only a delay of T.sub.syn3 between the finally obtained CLK_DIV and CLK_VCO, while CLK_DIV and CLK_REF are aligned through the loop, finally making the phases of the CLK_VCO and CLK_REF aligned.

[0023] At the same time, it should be noted that the delay T.sub.syn1 of the first clock synchronization module SYN1, the delay T.sub.syn2 of the second clock synchronization module SYN2 and the delay T.sub.CLK_VCO of the voltage control oscillator should satisfy: Tsyn1+Tsyn2<T.sub.CLK_VCO. That is, when the CLK_VCO samples CLK3, the delay between them should be less than T.sub.CLK_VCO. Otherwise, due to the non-ideal factors of the circuit, the sampling of CLK3 by the CLK_VCO may occur at its rising edge, which leads to sampling failure, and then leads to logic confusion of the divider.

[0024] FIG. 6 is a diagram showing the application of the zero-delay phase-locked loop frequency synthesizer based on multi-level synchronization in a multi-channel transceiver system. The reference clock signal CLK_REF is provided from the same signal source to TXPLL and RXPLL. Due to the characteristics of the zero-delay phase-locked loop, its output clocks CLK_TX and CLK_RX are phase-aligned with the reference clock signal CLK_REF, while the consistency between the phases of the clock signals reaching each module is realized by adjusting signal paths from TXPLL and RXPLL to respective TX and RX modules, thereby finally realizing the synchronization of all TX and RX paths.