ANALOG FIR FILTER

Abstract

A FIR filter (15), comprising an input terminal for receiving an input signal, a first filtering circuit comprising: a first transconductance device (30a) configured to generate a first current signal (i1) proportional to the input signal; a first analog switch (41a) commuted in n by a first digital gate signal (ϕ1) and configured to block the current signal when the first digital gate signal has a first value and to transmit the current signal to a first integrating capacitor (45a) when the first digital gate signal has a second value; characterized in that the first digital gate signal (ϕ1) comprises a periodic series of pulses, wherein the pulses have widths proportional to the filter coefficients.

Claims

1. A FIR filter, comprising an input terminal for receiving an input signal, a first filtering circuit comprising: a first integrating capacitor, a first transconductance device configured to generate a first current signal proportional to the input signal; a first analog switch commuted by a first digital gate signal and configured to block the current signal when the first digital gate signal has a first value and to transmit the first current signal to the first integrating capacitor when the first digital gate signal has a second value; wherein the first digital gate signal comprises a periodic series of pulses, wherein the pulses have widths proportional to a set of coefficients of the FIR filter.

2. The FIR filter of claim 1, having a gate generator comprising a memory storing the filter coefficients and a digital-to-time converter, wherein the filter coefficients are read from the memory and provided to the digital-to-time converter sequentially and synchronously with a clock signal, and the digital-to-time converter generates for each received filter coefficient a pulse having a width proportional thereto.

3. The FIR filter claim 1, wherein the first integrating capacitor is periodically reset.

4. The FIR filter of claim 1, wherein the charge stored in the first integrating capacitor is periodically transferred to an output unit.

5. The FIR filter of claim 1, comprising a second filtering circuit comprising: a second transconductance device configured to generate a second current signal proportional to an inverted-phase replica of the input signal; a second analog switch controlled by a second digital gate signal and configured to block the second current signal when the second digital gate signal has the first value and to transmit the second current signal to the first integrating capacitor when the second digital gate signal has the second value; wherein the second gate signal consists in a series of pulses of constant width.

6. The FIR filter of claim 4 wherein the second digital gate signal is generated by a second digital-to-time converter whose input is static.

7. The FIR filter of claim 4, having a second integrating capacitor, a third analog switch and a fourth analog switch controlled by digital signals and configured to transfer the first current signal and the second current signal to the first and second integrating capacitor in an interleaved fashion.

8. The FIR filter of claim 4 having a plurality of integrating capacitors and a plurality of analog switches controlled by digital signals and configured to select cyclically an integrating capacitor from the plurality of integrating capacitors, block the current signal when the first digital gate signal has a first value and to transmit the first current signal to the selected integrating capacitor when the first digital gate signal has a second value, block the second current signal when the second digital gate signal has the first value and to transmit the second current signal to the selected integrating capacitor when the second digital gate signal has the second value.

9. The FIR filter of claim 8, having two integrating capacitors charged alternately.

10. The FIR filter of claim 8, wherein the charges stored in the integrating capacitors are cyclically transferred to an output circuit and determine a sampled output signal.

11. The FIR circuit of claim 10, having a gate generator comprising a memory storing the filter coefficients and a digital-to-time converter, wherein the filter coefficients are read from the memory and provided to the digital-to-time converter sequentially and synchronously with a clock signal, and the digital-to-time converter generates for each received filter coefficient a pulse having a width proportional thereto, wherein the sampled output signal is decimated relative to the clock signal.

Description

SHORT DESCRIPTION OF THE DRAWINGS

[0013] Exemplar embodiments of the invention are disclosed in the description and illustrated by the drawings in which:

[0014] FIG. 1 illustrates schematically a filter according to the invention.

[0015] FIG. 1a shows a variant of the invention with two filtering chains, one receiving a positive signal and another receiving the complementary negative signal.

[0016] FIGS. 2a and 2b show a variant of the invention with two multiplexed filters.

[0017] FIG. 3 is a chronogram plotting signals in the of the filter of FIGS. 2a and 2b, including the timing signals ϕ.sub.11, ϕ.sub.21, ϕ.sub.12, ϕ.sub.22, ϕ.sub.2r, ϕ.sub.2s, ϕ.sub.1r, ϕ.sub.1s, driving the switches of corresponding names of FIG. 2a.

[0018] FIG. 4 plots the transfer function of two filters according to the invention, comparing them to those of similar digital filters.

EXAMPLES OF EMBODIMENTS OF THE PRESENT INVENTION

[0019] With reference to FIG. 1, the filter 15 of the invention comprises an input terminal 12a that receives a signal V.sub.in to be filtered and provides it to the input of a transconductance node 30a to generate a current I.sub.1 that is sensibly proportional to the input signal level (I.sub.1=G.sub.m.Math.V.sub.in). The transconductance node 30a can be realized with any one of the many circuits used in the art to provide a transconductance with fixed gain G.sub.m.

[0020] An N-tap FIR filter is defined by N real coefficients α.sub.1, . . . , α.sub.n and can be represented mathematically in the z domain by

[00001]$H_{\mathrm{dig}}\left(z\right)=\underset{n=0}{\overset{N-1}{.Math.}}{\alpha }_n.Math.z^{-n}.$

[0021] The FIR coefficients α.sub.0, . . . , α.sub.n-1 are stored in the memory 23 from which they are read cyclically at each period of a clock signal clk. In the presented example, the clock signal has a frequency of 50 MHz, but this value could change according to the application. The digital values of the coefficients α.sub.n are presented to the input of a digital-to-time converter 25a that generates a gate signal ϕ.sub.1 consisting in a train of pulses, one per each period of the clock clk, whose width is proportional to the value of one of the coefficients α.sub.n. Since the memory 23 is read cyclically, the gate signal ϕ.sub.1 is periodic and repeats itself after a period T.sub.s,out=N.Math.T.sub.s, where T.sub.s is the period of the clock signal and N the number of taps.

[0022] In the shown example, the data fed from the memory to the DTC have a depth of 10 bit, but the invention could be applied to coefficients represented by digital words of any size.

[0023] The switch 41a switches the current I.sub.1 with the gate signal ϕ.sub.1 that encodes the coefficients α.sub.n as pulse widths, such that the integrating capacitor C.sub.int receives at each pulse a charge proportional to V.sub.in.Math.G.sub.m.Math.α.sub.n.Math.T.sub.s. At the end of a period T.sub.s,out, the charge accumulated in C.sub.int will a be proportional to the desired filtered output, and can be transferred to the output terminal V.sub.out by closing momentarily the switch 43a, after which the integrating capacitor 45a is reset to zero with the switch 47a and the cycle is repeated.

[0024] The signal present V.sub.out is therefore a sampled output at a frequency f.sub.s/N, where f.sub.s denotes the clock frequency, and N the number of taps of the filter. In other words, the output signal is decimated by a factor N relative to the clock frequency f.sub.s. To make an example, to realize a channel filter in a digital receiver the circuit of the invention may be used to synthesize a low-pass filter with a corner frequency of few MHz or lower. This can be obtained by a 25-taps FIR filter whereby, if f.sub.s=50 MHz, the output will be sampled at 2 MHz.

[0025] The digital-to-time converter 25a can be implemented in many ways by using a counter, a variable slope integrator, a constant slope integrator, or other suitable means. Owing to the non-zero rise and fall times of the DTC output, the DTC output may not be precise enough for low values of an (for short pulses, the duty cycle becomes comparable to the rise and fall time of the DTC). This may result in deviation from the desired transfer function and reduce the attenuation in the stop band.

[0026] To mitigate this problem, it is advantageous to use two filtering chains, as shown in FIG. 1a, one receiving a positive signal +V.sub.in/2, and another receiving the complementary negative signal −V.sub.in/2. The first and second filtering chains have two transconductance nodes 30a respectively 30b, ideally identical, whose outputs are chopped by switches S.sub.11 and S.sub.22 and integrated in capacitor 45a.

[0027] One of the switches—In the drawing, S.sub.11 in the upper chain connected to the positive input—is driven by a gate signal ϕ.sub.11 encoding the coefficients of the filter, as in FIG. 1, but with a deliberately inserted offset D.sub.min1, as visible in FIG. 2b. The other switch—S.sub.12 in this case—is driven by a gate signal ϕ.sub.12 consisting in identical pulses of width D.sub.min2. The second gate signal may be produced by a second DTC 25b or in any other way. This disposition avoids very short pulses entirely and avoid the errors arising from finite rise and fall times. Any further ill effect that might arise because of mismatch between the paths can be avoided by tuning the values of D.sub.min1 and D.sub.min2.

[0028] FIGS. 2a and 2b show a variant of the invention where the outputs of the transconductance amplifiers 30a and 30b are presented to two integrators arranged in parallel. In a first filter, the currents I.sub.1 and I.sub.2 generated by the transconductance amplifiers are integrated in capacitor 45a after having been chopped by switches 14a (S11) and 42a (S12). In a second filter, the same currents I.sub.1 and I.sub.2 are integrated in capacitor 45b through switches 41b (S.sub.22) and 42b (S.sub.21). Each filter has an independent reset switch 47a (S.sub.1s) respectively 47b (S.sub.2s) as well as transfer switches 43a (S.sub.1r) respectively 43b (S.sub.2r). It will be appreciated that both filters are electrically identical to the filter of FIG. 1a.

[0029] The two filters are operated in time-interleaved mode, the roles exchanging after each period T.sub.s,out. In a first period if length T.sub.s,out, the voltage is integrated, for example, in capacitor 45a, In the successive period of the same length, the voltage will be integrated in capacitor 45b, while capacitor 45a is reset by switch 47a each integration, the integrated voltage on the capacitors Cint1(2). The capacitors need to be reset to avoid peaking in the filter response due to IIR (infinite impulse response) effect. The corresponding signals in a possible implementation are presented in the chronogram of FIG. 3.

[0030] The transfer function of the proposed filter with Gm1=Gm2, Dmin1=Dmin2, and Cint1=Cint2, can be shown to be given by,

[00002]$H_{\mathrm{ana}}\left(f\right)=\frac{G_{m1}}{C_{int1}}.Math.\underset{n=0}{\overset{N-1}{.Math.}}\left(\frac{\sin \frac{{f\alpha }_n}{f_s}}{f}.Math.e^{-j\frac{2f}{f_s}}\right)$

[0031] The bandwidth is inversely proportional to the number of taps N and directly proportional to the clock rate f.sub.s. Time interleaving has the further advantage of decoupling the relationship between the output sample rate and the bandwidth. By increasing the number of parallel filters to four, for example, the output signal may have a decimation factor N/2 rather than N. Other decimation ratios can be obtained by increasing the number of interleaved parallel filters. N interleaved filters can be used to suppress the decimation and have an output signal sampled at the same frequency as the clock rate f.sub.s.

[0032] To improve the aliasing performance, a low pass filter in either continuous time domain like an RC filter or a discrete time filter like a windowed integration (integrating time of Ts) sampler can be placed before the proposed filter.

[0033] FIG. 4 shows the simulated transfer functions of the filter of the invention in a 25-taps and in a 50 taps realization (solid lines) The dashed lines plot the ideal transfer function obtained by the equations above, and the dotted line show, for comparison, the ideal output of digital FIR filters of the same coefficients.