Integrator And Analog-To-Digital Converter

Abstract

An integrator and an analog-to-digital converter are provided. The analog-to-digital converter includes the integrator, a comparison circuit and a control logic circuit. The integrator includes an operational amplifier, offset capacitors, input capacitors, integral capacitors and controllable switches. The input capacitors and the integral capacitors are connected to the operational amplifier via controllable switches, so that the integrator operates in various operation modes. Operation states of the offset capacitors in a first phase and a second phase of an operation cycle are controlled by switching on or off the controllable switches. Therefore, an offset voltage of the integrator is eliminated, and conversion efficiency and conversion accuracy of the analog-to-digital converter is improved.

Claims

1. An integrator, comprising: an operational amplifier, wherein the operational amplifier comprises a first input terminal, a second input terminal, a first output terminal and a second output terminal; a first offset capacitor and a second offset capacitor, wherein the first offset capacitor is coupled to the first input terminal, and the second offset capacitor is coupled to the second input terminal; a plurality of controllable switches, a plurality of input capacitors and a plurality of integral capacitors, wherein the input capacitors and the integral capacitors are connected to the operational amplifier via the controllable switches, to control an operation mode of the integrator, wherein the controllable switches are configured to control operation states of the first offset capacitor and the second offset capacitor in a first phase and a second phase of an operation cycle to eliminate an offset voltage of the operational amplifier.

2. The integrator according to claim 1, wherein: the first offset capacitor and the second offset capacitor are configured to store the offset voltage in the first phase; and the offset voltage of the operational amplifier is eliminated by counteracting the offset voltage with a voltage across the first offset capacitor and a voltage across the second offset capacitor in the second phase.

3. The integrator according to claim 1, wherein the operation mode of the integrator comprises a return-to-zero mode, a first integral mode and a second integral mode.

4. The integrator according to claim 3, wherein the integrator is reset in a first phase of the return-to-zero mode; and the integrator is configured to, in a second phase of the return-to-zero mode, sample an input voltage signal and output the sampled input voltage signal.

5. The integrator according to claim 3, wherein the integrator is configured to, in the first integral mode: sample a reference voltage signal and output an integral signal in a last operation cycle; and sample an input voltage signal and a reference voltage signal and output an integral signal in an operation cycle other than the last operation cycle.

6. The integrator according to claim 3, wherein in the first integral mode, an integral signal outputted by the integrator in a last operation cycle is equal to a sum of an integral signal outputted by the integrator in an operation cycle immediately before the last operation cycle and a first signal; and an integral signal outputted by the integrator in an operation cycle other than the last operation cycle is equal to a sum of an integral signal outputted by the integrator in a previous operation cycle, the first signal and an input voltage signal, wherein the first signal is a product of a reference voltage signal and a first coefficient.

7. The integrator according to claim 3, wherein the integrator is configured to, in the second integral mode, amplify an output voltage of the integrator in a previous operation cycle.

8. The integrator according to claim 3, wherein the integrator is configured to, in a first phase of the second integral mode, sample a reference voltage signal and output an integral signal, wherein in a second phase of the second integral mode, an integral signal outputted by the integrator in a current operation cycle is equal to a multiple of a sum of an integral signal outputted by the integrator in an operation cycle immediately before the current operation cycle and a first signal, wherein the first signal is a product of a reference voltage signal and a first coefficient.

9. The integrator according to claim 6, wherein in a case that the integrator is configured to receive a positive reference voltage signal in the first phase and receive a negative reference voltage signal in the second phase, the first coefficient is equal to 1; in a case that the integrator is configured to receive a negative reference voltage signal in the first phase and receive a positive reference voltage signal in the second phase, the first coefficient is equal to −1; and in a case that the integrator is configured to receive a zero reference signal in the first phase and the second phase, the first coefficient is equal to 0.

10. The integrator according to claim 8, wherein in a case that the integrator is configured to receive a positive reference voltage signal in the first phase and receive a negative reference voltage signal in the second phase, the first coefficient is equal to 1; in a case that the integrator is configured to receive a negative reference voltage signal in the first phase and receive a positive reference voltage signal in the second phase, the first coefficient is equal to −1; and in a case that the integrator is configured to receive a zero reference signal in the first phase and the second phase, the first coefficient is equal to 0.

11. The integrator according to claim 3, wherein the input capacitors comprise a first input capacitor and a second input capacitor, and the integral capacitors comprise a first integral capacitor, a second integral capacitor, a third integral capacitor and a fourth integral capacitor, wherein the first input capacitor, the first integral capacitor and the second integral capacitor each are configured to be coupled to at least one of the first input terminal and the first output terminal of the operational amplifier, and the second input capacitor, the third integral capacitor and the fourth integral capacitor each are configured to be coupled to at least one of the second input terminal and the second output terminal of the operational amplifier; and in the second integral mode, the second integral capacitor is configured to charge the first integral capacitor in a current operation cycle, and the first input capacitor is configured to charge the first integral capacitor in an operation cycle immediately after the current operation cycle, and the fourth integral capacitor is configured to charge the third integral capacitor in the current operation cycle and the second input capacitor is configured to charge the third integral capacitor in the operation cycle immediately after the current operation cycle, to amplify an output voltage of the integrator in the current operation cycle.

12. The integrator according to claim 1, wherein the input capacitors comprise a first input capacitor, a second input capacitor, a third input capacitor and a fourth input capacitor, wherein the first input capacitor and the third input capacitor each are configured to be coupled to the first input terminal of the operational amplifier, and the second input capacitor and the fourth input capacitor each are configured to be coupled to the second input terminal of the operational amplifier, and wherein the first input capacitor and the second input capacitor are configured to receive an input voltage signal or a common mode voltage signal, and the third input capacitor and the fourth input capacitor are configured to receive a reference voltage signal or a common mode voltage signal.

13. An analog-to-digital converter, comprising: an integrator comprising an operational amplifier, a plurality of controllable switches and a plurality of capacitors, wherein the operational amplifier comprises a first input terminal, a second input terminal, a first output terminal and a second output terminal, and the capacitors are connected to the operational amplifier via the controllable switches; a comparison circuit configured to receive an output signal of the integrator; and a control logic circuit configured to generate a digital signal corresponding to an input voltage signal based on an output signal of the comparison circuit, and wherein: the controllable switches are configured to be switched on or switched off to control the analog-to-digital converter to operate in one of a reset mode, a sigma-delta analog-to-digital conversion mode and a cyclic conversion mode.

14. The analog-to-digital converter according to claim 13, wherein the capacitors comprise a first offset capacitor and a second offset capacitor, wherein the first offset capacitor is coupled to the first input terminal of the operational amplifier, and the second offset capacitor is coupled to the second input terminal of the operational amplifier; the first offset capacitor and the second offset capacitor are configured to store an offset voltage of the operational amplifier in a first phase; and the offset voltage of the operational amplifier is eliminated by counteracting the offset voltage with a voltage across the first offset capacitor and a voltage across the second offset capacitor in a second phase.

15. The analog-to-digital converter according to claim 13, wherein the analog-to-digital converter is reset in a first phase of the reset mode; and the integrator is configured to, in a second phase of the reset mode of the analog-to-digital converter, sample an input voltage signal and output the sampled input voltage signal.

16. The analog-to-digital converter according to claim 13, wherein the integrator is configured to, in the sigma-delta analog-to-digital conversion mode of the analog-to-digital converter: sample a reference voltage signal and output an integral signal in a last operation cycle; and sample an input voltage signal and a reference voltage signal and output an integral signal in an operation cycle other than the last operation cycle.

17. The analog-to-digital converter according to claim 13, wherein in the sigma-delta analog-to-digital conversion mode of the analog-to-digital converter, an integral signal outputted by the integrator in a last operation cycle is equal to a sum of an integral signal outputted by the integrator in an operation cycle immediately before the last operation cycle and a first signal; and an integral signal outputted by the integrator in an operation cycle other than the last operation cycle is equal to a sum of an integral signal outputted by the integrator in a previous operation cycle, the first signal and an input voltage signal, wherein the first signal is a product of a reference voltage signal and a first coefficient.

18. The analog-to-digital converter according to claim 13, wherein the integrator is configured to, in the cyclic conversion mode of the analog-to-digital converter, amplify an output voltage of the integrator in a previous operation cycle.

19. The analog-to-digital converter according to claim 13, wherein the integrator is configured to, in a first phase of the cyclic conversion mode of the analog-to-digital converter, sample a reference voltage signal and output an integral signal, wherein in a second phase of the cyclic conversion mode of the analog-to-digital converter, an integral signal outputted by the integrator in a current operation cycle is equal to a multiple of a sum of an integral signal outputted by the integrator in an operation cycle immediately before the current operation cycle and a first signal, wherein the first signal is a product of a reference voltage signal and a first coefficient.

20. The analog-to-digital converter according to claim 17, wherein in a case that the integrator is configured to receive a positive reference voltage signal in a first phase and receive a negative reference voltage signal in a second phase, the first coefficient is equal to 1; in a case that the integrator is configured to receive a negative reference voltage signal in a first phase and receive a positive reference voltage signal in a second phase, the first coefficient is equal to −1; and in a case that the integrator is configured to receive a zero reference signal in a first phase and a second phase, the first coefficient is equal to 0.

21. The analog-to-digital converter according to claim 19, wherein in a case that the integrator is configured to receive a positive reference voltage signal in a first phase and receive a negative reference voltage signal in a second phase, the first coefficient is equal to 1; in a case that the integrator is configured to receive a negative reference voltage signal in a first phase and receive a positive reference voltage signal in a second phase, the first coefficient is equal to −1; and in a case that the integrator is configured to receive a zero reference signal in a first phase and a second phase, the first coefficient is equal to 0.

22. The analog-to-digital converter according to claim 20, wherein it is determined whether the integrator receives a positive reference voltage signal, a negative reference voltage signal or a zero reference signal in the first phase and the second phase of the current operation cycle based on an output signal of the comparison circuit at an output end of the second phase of the operation cycle immediately before the current operation cycle.

23. The analog-to-digital converter according to claim 13, wherein the capacitors comprise a plurality of input capacitors and a plurality of integral capacitors, wherein the input capacitors comprise a first input capacitor and a second input capacitor, the integral capacitors comprise a first integral capacitor, a second integral capacitor, a third integral capacitor and a fourth integral capacitor, and wherein the first input capacitor, the first integral capacitor and the second integral capacitor are configured to be coupled to at least one of the first input terminal and the first output terminal of the operational amplifier, and the second input capacitor, the third integral capacitor and the fourth integral capacitor are configured to be coupled to at least one of the second input terminal and the second output terminal of the operational amplifier; and in the cyclic conversion mode of the analog-to-digital converter, the second integral capacitor is configured to charge the first integral capacitor in a current operation cycle, and the first input capacitor is configured to charge the first integral capacitor in an operation cycle immediately after the current operation cycle, and the fourth integral capacitor is configured to charge the third integral capacitor in the current operation cycle and the second input capacitor is configured to charge the third integral capacitor in the operation cycle immediately after the current operation cycle, to amplify an output voltage of the integrator in the current operation cycle.

24. The analog-to-digital converter according to claim 23, wherein in the cyclic conversion mode of the analog-to-digital converter, in the first phase, each of the first integral capacitor, the second integral capacitor, the third integral capacitor and the fourth integral capacitor is configured to store charges that are stored in the capacitor in an operation cycle immediately before the current operation cycle, and the first input capacitor and the second input capacitor each are configured to discharge; and in the second phase, the first integral capacitor is connected between the first input terminal and the first output terminal of the operational amplifier, the third integral capacitor is connected between the second input terminal and the second output terminal of the operational amplifier, the second integral capacitor is configured to charge the first integral capacitor, and the fourth integral capacitor is configured to charge the third integral capacitor, to amplify an output voltage of the operational amplifier, wherein the first input capacitor and the second input capacitor are configured to sample the output voltage of the integrator.

25. The analog-to-digital converter according to claim 23, wherein in the cyclic conversion mode of the analog-to-digital converter, in the first phase, each of the first input capacitor, the second input capacitor, the first integral capacitor and the third integral capacitor is configured to store charges that are stored in the capacitor in the operation cycle immediately before the current operation cycle, and the second integral capacitor and the fourth integral capacitor each are configured to discharge; and in the second phase, the first integral capacitor is connected between the first input terminal and the first output terminal of the operational amplifier, the third integral capacitor is connected between the second input terminal and the second output terminal of the operational amplifier, the first input capacitor is configured to charge the first integral capacitor and the second input capacitor is configured to charge the third integral capacitor to amplify an output voltage of the operational amplifier, wherein the second integral capacitor and the fourth integral capacitor are configured to sample the output voltage of the integrator.

26. The analog-to-digital converter according to claim 13, wherein the analog-to-digital converter is configured to sequentially operate in the reset mode, the sigma-delta analog-to-digital conversion mode and the cyclic conversion mode, to perform analog-to-digital conversion.

27. The analog-to-digital converter according to claim 13, wherein the comparison circuit is configured to compare the output signal of the integrator with a first threshold to obtain a first comparison signal and compare the output signal of the integrator with a second threshold to obtain a second comparison signal, wherein the first threshold is greater than the second threshold.

28. The analog-to-digital converter according to claim 27, wherein in the sigma-delta analog-to-digital conversion mode, the first comparison signal is a first high-bit comparison signal, and the second comparison signal is a second high-bit comparison signal; and in the cyclic conversion mode, the first comparison signal is a first low-bit comparison signal, and the second comparison signal is a second low-bit comparison signal.

29. The analog-to-digital converter according to claim 28, wherein the control logic circuit is configured to: acquire a first digital signal based on the first high-bit comparison signal and the first low-bit comparison signal; acquire a second digital signal based on the second high-bit comparison signal and the second low-bit comparison signal; and output the digital signal corresponding to the input voltage based on the first digital signal and the second digital signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and other objects, features and advantages of the present disclosure are clearer by describing the embodiments of the present disclosure with reference to the drawings. In the drawings:

[0044] FIG. 1 is a circuit diagram of a Σ-Δ analog-to-digital converter according to the conventional technology;

[0045] FIG. 2 is a circuit diagram of a successive approximation register (SAR) analog-to-digital converter according to the conventional technology;

[0046] FIG. 3 is a schematic structural diagram of an analog-to-digital converter combining an SAR analog-to-digital converter and a Σ-Δ analog-to-digital converter according to the conventional technology;

[0047] FIG. 4 is a circuit diagram of an analog-to-digital converter according to an embodiment of the present disclosure;

[0048] FIG. 5 is a circuit diagram of the integrator operating in a first phase of a return-to-zero mode according to an embodiment of the present disclosure;

[0049] FIG. 6 is a circuit diagram of the integrator operating in a second phase of the return-to-zero mode according to an embodiment of the present disclosure;

[0050] FIG. 7 is a circuit diagram of the integrator operating in a first phase of a first integral mode according to an embodiment of the present disclosure;

[0051] FIG. 8 is a circuit diagram of the integrator operating in a second phase of the first integral mode according to an embodiment of the present disclosure;

[0052] FIG. 9 is a circuit diagram of the integrator operating in the first phase of the first integral mode according to an embodiment of the present disclosure;

[0053] FIG. 10 is a circuit diagram of the integrator operating in the second phase of the first integral mode according to an embodiment of the present disclosure;

[0054] FIG. 11 is a circuit diagram of the integrator operating in a first phase of a second integral mode according to an embodiment of the present disclosure;

[0055] FIG. 12 is a circuit diagram of the integrator operating in a second phase of the second integral mode according to an embodiment of the present disclosure;

[0056] FIG. 13 is a circuit diagram of the integrator operating in the first phase of the second integral mode according to an embodiment of the present disclosure; and

[0057] FIG. 14 is a circuit diagram of the integrator operating in the second phase of the second integral mode according to an embodiment of the present disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS

[0058] The present disclosure is described on the basis of the embodiments hereinafter, but is not limited to these embodiments. In the detailed description of the present disclosure hereinafter, numerous specific details are set forth. Those skilled in the art can understand the present disclosure without these specific details. To avoid obscuring the substance of the present disclosure, well-known methods, procedures, processes, elements and circuits are not described in detail herein.

[0059] In addition, those skilled in the art should understand that the drawings are provided herein for illustration, and are not necessarily drawn to scale.

[0060] In addition, it should be understood that in the following description, the term “circuit” indicates a conductive loop formed by at least one element or sub-circuit through electrical connections or electromagnetic connections. When an element or a circuit is described as being “connected to” another element or an element or a circuit is described as being “connected between” two nodes, the element or the circuit is coupled or connected to another element directly or via other element. The elements may be connected physically, logically, or a combination thereof. In addition, when an element is described as being “directly coupled” or “directly connected” to another element, it indicates that there is no element between the two elements.

[0061] Unless otherwise stated, the terms “include”, “comprise” or any other variations in the specification are intended to be inclusive, rather than exclusive or exhaustive. That is, the terms indicate “including but not limited to”.

[0062] In the description of the present disclosure, it should be understood that terms “first”, “second” and the like are used only for description and cannot be understood as indicating or implying relative importance. In addition, in the description of the present disclosure, “multiple” means two or more unless otherwise stated.

[0063] FIG. 1 is a circuit diagram of a Σ-Δ analog-to-digital converter according to the conventional technology. As shown in FIG. 1, the analog-to-digital converter includes an operational amplifier OTA, a comparator CMP, and a counter. A non-inverting input terminal of the operational amplifier OTA is grounded, and an inverting input terminal of the operational amplifier OTA is connected to capacitors C.sub.3 and C.sub.1. One terminal of capacitor C.sub.3 receives a negative signal −V.sub.REF of a reference voltage via a switch S.sub.5 and is grounded via a switch S.sub.4. One terminal of capacitor C.sub.1 receives an input voltage V.sub.IN via a switch S.sub.1 and is grounded via a switch S.sub.2. One terminal of the capacitor C.sub.2 is connected to an output terminal of the operational amplifier OTA, and the other terminal of the capacitor C.sub.2 is connected to the inverting input terminal of the operational amplifier OTA via a switch S.sub.3. The switch S.sub.6 short-circuits the output terminal of the operational amplifier OTA and the inverting input terminal of the operational amplifier OTA.

[0064] The input voltage V.sub.IN is sampled by controlling the switch S.sub.1 and the switch S.sub.6 to be switched on, so that the capacitor C.sub.1 is charged until a voltage of the capacitor C.sub.1 is equal to the input voltage V.sub.IN. Then, charges on the capacitor C.sub.1 are transferred to the capacitor C.sub.2 by controlling the switches S.sub.2 and S.sub.3 to be switched on, so that an output signal of the operational amplifier OTA is inputted to an non-inverting input terminal of the comparator CMP. In a case that a gain of the integrator is equal to 1 and a gain of the operational amplifier OTA is infinite, the output signal of the operational amplifier OTA is approximately equal to the input voltage V.sub.IN. The comparator CMP compares the output signal of the operational amplifier OTA with the reference voltage signal V.sub.REF. If the comparator outputs a signal at a low level, the number of times stored in the counter remains unchanged. In a next cycle, the input voltage V.sub.IN is resampled by controlling the switches S.sub.1 and S.sub.6 to be switched on. When a voltage of the capacitor C.sub.1 is equal to the input voltage V.sub.IN, charges are transferred from the capacitor C.sub.1 to the capacitor C.sub.2 by controlling the switches S.sub.3 and S.sub.2 to be switched on, so that a voltage of the capacitor C.sub.2 is approximately equal to twice the input voltage V.sub.IN. Similarly, in a case that the comparator CMP outputs a signal at a low level, the number of times stored in the counter remains unchanged. The above process is repeated until the comparator CMP outputs a signal at a high level.

[0065] Alternatively, in a case that the comparator CMP outputs a signal at a high level, the number of times stored in the counter is increased. In addition, in the case that the comparator CMP outputs a signal at a high level, the switches S.sub.5, S.sub.1 and S.sub.6 are controlled to be switched on to sample the negative signal −V.sub.REF of the reference voltage and the input voltage V.sub.IN, so as to accumulate charges representing the negative signal −V.sub.REF of the reference voltage on the capacitor C.sub.3 and accumulate charges representing the input voltage V.sub.IN on the capacitor C.sub.1. The charges on the capacitors C.sub.3 and C.sub.1 are transferred to the capacitor C.sub.2 by controlling the switches S.sub.3, S.sub.4 and S.sub.2 to be switched on. The input voltage V.sub.IN is continuously and repeatedly sampled and the negative signal −V.sub.REF of the reference voltage is sampled in a case that the comparator CMP outputs a signal at a high level. After N cycles, a voltage caused by residual charges on the capacitor C.sub.2 is expressed as: V=N*V.sub.IN−X*V.sub.REF, where X represents the number of times outputted by the counter.

[0066] The above process may repeated for a large number of cycles, so that conversion accuracy is improved. However, in a case that a high accuracy is required, conversion efficiency is low. For example, 1024 cycles are required for 10-bit resolution and more than a million cycles are required for 20-bit resolution. Therefore, although the analog-to-digital converter in FIG. 1 can achieve an accurate result, a long period of time spent on conversion is required.

[0067] FIG. 2 is a circuit diagram of a successive approximation register SAR analog-to-digital converter in the conventional technology. As shown in FIG. 2, the successive approximation register analog-to-digital converter includes a comparator CMP and a shift register. An input voltage V.sub.IN is compared with half of a reference voltage V.sub.REF. In a case that the input voltage V.sub.IN is greater than half of the reference voltage V.sub.REF, the comparator CMP outputs a signal at a high level and logic “1” is shifted to the shift register.

[0068] Further, in the case that the previous comparison indicates that the input voltage V.sub.IN is less than half of the reference voltage V.sub.REF, half of the reference voltage V.sub.REF is added to a quarter of the reference voltage V.sub.REF by an adder to obtain a sum, and the sum is compared with the input voltage V.sub.IN by the comparator CMP (that is, the input voltage V.sub.IN is compared with three quarters of the voltage reference V.sub.REF). Similarly, in a case that comparator CMP outputs a signal at a high level, the logic “1” is shifted to the shift register. In a case that comparator CMP outputs a signal at a low level, logic “0” is shifted to the shift register.

[0069] Alternatively, in a case that the previous comparison indicates that the input voltage V.sub.IN is less than half of the reference voltage V.sub.REF, a quarter of the reference voltage V.sub.REF is subtracted from half of the reference voltage V.sub.REF to obtain a difference, and the difference is compared with the input voltage V.sub.IN (that is, the input voltage V.sub.IN is compared with a quarter of the voltage reference V.sub.REF). Similarly, in a case that comparator CMP outputs a signal at a high level, the logic “1” is shifted to the shift register. In a case that comparator CMP outputs a signal at a low level, logic “0” is shifted to the shift register.

[0070] Therefore, a conversion result with high-resolution is obtained in a short period of time through the above process. Moreover, only one cycle is required for each bit of resolution. For example, ten cycles are required for a ten-bit resolution, and twenty cycles are required for a twenty-bit resolution. However, the reference voltage is susceptible to white noise and bounce noise, resulting in an inaccurate conversion result.

[0071] FIG. 3 is a schematic structural diagram of an analog-to-digital converter combining an SAR analog-to-digital converter and a Σ-Δ analog-to-digital converter in the conventional technology. As shown in FIG. 3, the analog-to-digital converter includes a Σ-Δ analog-to-digital converter 1, an SAR analog-to-digital converter 2 and a logic circuit 3. The Σ-Δ analog-to-digital converter 1 operates based on the principle of a delta-sigma analog-to-digital converter and is configured to generate a first output result and a residual signal based on an input voltage V.sub.IN. The SAR analog-to-digital converter 2 operates based on the principle of an SAR analog-to-digital converter and is configured to generate a second output result based on the residual signal. The logic circuit 3 is configured to generate a digital signal corresponding to the input voltage V.sub.IN based on the first output result and the second output result.

[0072] Further, the logic circuit 3 acquires a high-order conversion result based on the first output result, acquires a low-order conversion result based on the second output result, and combines the high-order conversion result with the low-order conversion result to obtain a digital signal D.sub.out corresponding to the input voltage V.sub.IN.

[0073] However, an offset voltage of an operational amplifier is directly superimposed on an output voltage of the operational amplifier in each cycle. In addition, the offset voltage of the operational amplifier varies with a voltage of a power supply and a temperature, so that a temperature feature and a power supply suppression feature of the analog-to-digital converter deteriorates due to the offset voltage of the operational amplifier even if the system calibrates an offset error of the analog-to-digital converter at the room temperature and a typical operation voltage. Moreover, the analog-to-digital converter combining an SAR analog-to-digital converter and a Σ-Δ analog-to-digital converter has high requirements on a direct current gain of the operational amplifier since an error is proportional to a reciprocal of the direct current gain when the operational amplifier operates as a closed loop.

[0074] FIG. 4 is a circuit diagram of an analog-to-digital converter according to an embodiment of the present disclosure. As shown in FIG. 4, the analog-to-digital converter according to the embodiment of the present disclosure includes an integrator 1, a comparison circuit 2 and a control logic circuit 3. The integrator 1 is capable of operating in various operation modes. The comparison circuit 2 is configured to receive an output signal of the integrator 1. The control logic circuit 3 is configured to generate a digital signal corresponding to an input voltage based on an output signal of the comparison circuit 2.

[0075] In the embodiment, the integrator 1 includes an operational amplifier OTA, multiple offset capacitors, multiple input capacitors, multiple integral capacitors and multiple controllable switches.

[0076] In the embodiment, the operational amplifier OTA includes a first input terminal a.sub.1, a second input terminal a.sub.2, a first output terminal b.sub.1 and a second output terminal b.sub.2.

[0077] In the embodiment, the offset capacitors include a first offset capacitor C.sub.H1 and a second offset capacitor C.sub.H2. The first offset capacitor C.sub.H1 is coupled to the first input terminal a.sub.1. The second offset capacitor C.sub.H2 is coupled to the second input terminal az.

[0078] The first offset capacitor and the second offset capacitor store an offset voltage in a first phase. In a second phase, a voltage across the first offset capacitor and a voltage across the second offset capacitor counteract the offset voltage to eliminate the offset voltage of the operational amplifier.

[0079] In the embodiment, the input capacitors include a first input capacitor C.sub.I1, a second input capacitor C.sub.I2, a third input capacitor C.sub.I3 and a fourth input capacitor C.sub.I4. The first input capacitor C.sub.I1 and the third input capacitor C.sub.I3 are configured to be coupled to the first input terminal a.sub.1 of the operational amplifier OTA. The second input capacitor C.sub.I2 and the fourth input capacitor C.sub.I4 are configured to be coupled to the second input terminal a.sub.2 of the operational amplifier OTA.

[0080] In the embodiment, the integral capacitors include a first integral capacitor C.sub.F1, a second integral capacitor C.sub.F2, a third integral capacitor C.sub.F3 and a fourth integral capacitor C.sub.F4. The first integral capacitor C.sub.F1 and the second integral capacitor C.sub.F2 are configured to be coupled to at least one of the first input terminal a.sub.1 and the first output terminal b.sub.1 of the operational amplifier OTA. The third integral capacitor C.sub.F3 and the fourth integral capacitor C.sub.F4 are configured to be coupled to at least of the first input terminal a.sub.2 and the second output terminal b.sub.2 of the operational amplifier OTA.

[0081] In the embodiment, the controllable switches include switches S.sub.11 to S.sub.46.

[0082] The switch S ii is connected between a first input terminal V.sub.RP of the reference voltage signal and a first terminal of the third input capacitor C.sub.I3.

[0083] The switch S.sub.12 is connected between a second input terminal V.sub.RN of the reference voltage signal and the first terminal of the third input capacitor C.sub.I3.

[0084] The switch S.sub.13 is connected between an input terminal of a common mode voltage signal V.sub.CM and the first terminal of the third input capacitor C.sub.I3.

[0085] The switch S.sub.14 is connected between the input terminal of the common mode voltage signal V.sub.CM and a first terminal of the first input capacitor C.sub.I1.

[0086] The switch S.sub.15 is connected between a first input terminal V.sub.INP of an input voltage signal and the first terminal of the first input capacitor C.sub.I1.

[0087] The switch S.sub.16 is connected between the first input terminal V.sub.INP of the input voltage signal and a first terminal of the second input capacitor C.sub.I2.

[0088] The switch S.sub.17 is connected between a second input terminal V.sub.INN of the input voltage signal and the first terminal of the first input capacitor C.sub.I1.

[0089] The switch S.sub.18 is connected between the second input terminal V.sub.INN of the input voltage signal and the first terminal of the second input capacitor C.sub.I2.

[0090] The switch S.sub.19 is connected between the input terminal V.sub.CM of the common mode voltage signal and the first terminal of the second input capacitor C.sub.I2.

[0091] The switch S.sub.20 is connected between the input terminal of the common mode voltage signal V.sub.CM and a first terminal of the fourth input capacitor C.sub.I4.

[0092] The switch S.sub.21 is connected between the second input terminal V.sub.RN of the reference voltage signal and the first terminal of the fourth input capacitor C.sub.I4.

[0093] The switch S.sub.22 is connected between the first input terminal V.sub.RP of the reference voltage signal and the first terminal of the fourth input capacitor C.sub.I4.

[0094] The switch S.sub.23 is connected between the input terminal of the common mode voltage signal V.sub.CM and a second terminal of the first input capacitor C.sub.I1.

[0095] The switch S.sub.24 is connected between the input terminal of the common mode voltage signal V.sub.CM and a second terminal of the second input capacitor C.sub.I2.

[0096] The switch S.sub.25 is connected between a first terminal of the first offset capacitor C.sub.H1 and the second terminal of the first input capacitor C.sub.I1.

[0097] The switch S.sub.26 is connected between a first terminal of the second offset capacitor C.sub.H2 and the second terminal of the second input capacitor C.sub.I2.

[0098] The switch S.sub.27 is connected between the input terminal of the common mode voltage signal V.sub.CM and the first terminal of the first offset capacitor C.sub.H1.

[0099] The switch S.sub.28 is connected between the input terminal of the common mode voltage signal V.sub.CM and the first terminal of the second offset capacitor C.sub.H2.

[0100] The switch S.sub.29 is connected between a first terminal of the second integral capacitor C.sub.F2 and the second terminal of the third input capacitor C.sub.I3.

[0101] The switch S.sub.30 is connected between a first terminal of the first integral capacitor C.sub.F1 and the second terminal of the third input capacitor C.sub.I3.

[0102] The switch S.sub.31 is connected between a first terminal of the third integral capacitor C.sub.F3 and the second terminal of the fourth input capacitor C.sub.I4.

[0103] The switch S.sub.32 is connected between a first terminal of the fourth integral capacitor C.sub.F4 and the second terminal of the fourth input capacitor C.sub.I4.

[0104] The switch S.sub.33 is connected between the first output terminal b.sub.1 of the operational amplifier and the first terminal of the first input capacitor C.sub.I1.

[0105] The switch S.sub.34 is connected between the second output terminal b.sub.2 of the operational amplifier and the first terminal of the second input capacitor C.sub.I2.

[0106] The switch S.sub.35 is connected between the input terminal of the common mode voltage signal V.sub.CM and the first terminal of the second integral capacitor C.sub.F2.

[0107] The switch S.sub.36 is connected between the input terminal of the common mode voltage signal V.sub.CM and a second terminal of the second integral capacitor C.sub.F2.

[0108] The switch S.sub.37 is connected between the first output terminal b.sub.1 of the operational amplifier and the second terminal of the second integral capacitor C.sub.F2.

[0109] The switch S.sub.38 is connected between the input terminal of the common mode voltage signal V.sub.CM and the second terminal of the first integral capacitor C.sub.F1.

[0110] The switch S.sub.39 is connected between the first output terminal b.sub.1 of the operational amplifier and the second terminal of the first integral capacitor C.sub.F1.

[0111] The switch S.sub.40 is connected between the first output terminal b.sub.1 of the operational amplifier and a second terminal of the first offset capacitor C.sub.H1.

[0112] The switch S.sub.41 is connected between the second output terminal b.sub.2 of the operational amplifier and a second terminal of the second offset capacitor C.sub.H2.

[0113] The switch S.sub.42 is connected between the second output terminal b.sub.2 of the operational amplifier and a second terminal of the third integral capacitor C.sub.F3.

[0114] The switch S.sub.43 is connected between the input terminal of the common mode voltage signal V.sub.CM and the second terminal of the third integral capacitor C.sub.F3.

[0115] The switch S.sub.44 is connected between the second output terminal b.sub.2 of the operational amplifier and a second terminal of the fourth integral capacitor C.sub.F4.

[0116] The switch S.sub.45 is connected between the input terminal of the common mode voltage signal V.sub.CM and the second terminal of the fourth integral capacitor C.sub.F4.

[0117] A switch S.sub.46 is connected between the input terminal of the common mode voltage signal V.sub.CM and a first terminal of the fourth integral capacitor C.sub.F4.

[0118] In the embodiment, the common mode voltage signal V.sub.CM has a value from zero to a voltage of a power supply of the analog-to-digital converter.

[0119] In the embodiment, the controllable switches are controlled to be switched on or switched off to connect the input capacitors and the integral capacitors to the operational amplifier or to disconnect the input capacitors and the integral capacitors from the operational amplifier, so as to control operation modes of the integrator and the analog-to-digital converter.

[0120] In the embodiment, the controllable switches are controlled to be switched on or switched off to control the integrator 1 to operate in one of a return-to-zero mode, a first integral mode and a second integral mode. Further, in a case that the integrator 1 operates in the return-to-zero mode, the analog-to-digital converter operates in a reset mode. In a case that the integrator 1 operates in the first integral mode, the analog-to-digital converter operates in a sigma-delta analog-to-digital conversion mode. In a case that the integrator 1 operates in the second integral mode, the analog-to-digital converter operates in a cyclic conversion mode.

[0121] In the embodiment, in a case that the integrator operates in the return-to-zero mode, the integrator is reset.

[0122] Further, in a case that the integrator operates in the return-to-zero mode, the integrator is configured to sample an input voltage signal and output the sampled input voltage signal. Further, in the return-to-zero mode, the integrator serves as a sampling holder.

[0123] In the embodiment, in a case that the integrator operates in the first integral mode, in a last operation cycle, the integrator samples the reference voltage signal and outputs an integral signal. In an operation cycle other than the last operation cycle, the integrator samples the input voltage signal and the reference voltage signal and outputs an integral signal.

[0124] Further, in a case that the integrator operates in the first integral mode, the integral signal outputted by the integrator in the last operation cycle is equal to a sum of an integral signal outputted by the integrator in an operation cycle immediately before the last operation cycle and a first signal. An integral signal outputted by the integrator in the operation cycle other than the last operation cycle is equal to a sum of an integral signal outputted by the integrator in a previous operation cycle, the first signal and the input voltage signal. The first signal is a product of the reference voltage signal and a first coefficient.

[0125] In the embodiment, in a case that the integrator operates in the second integral mode, an output voltage of the integrator in an operation cycle immediately before the current operation cycle is amplified.

[0126] Further, in a case that the integrator operates in the second integral mode, the integrator is configured to sample the reference voltage signal and output an integral signal.

[0127] Further, in a case that the integrator operates in the second integral mode, the integral signal outputted by the integrator is equal to a multiple of a sum of the first signal and an integral signal outputted by the integrator in an operation cycle immediately before the current operation cycle. The first signal is a product of the reference voltage signal and the first coefficient.

[0128] Further, in a case that the integrator receives a positive reference voltage signal in the first phase and receives a negative reference voltage signal in the second phase, the first coefficient is equal to 1.

[0129] In a case that the integrator receives a negative reference voltage signal in the first phase and receives a positive reference voltage signal in the second phase, the first coefficient is equal to −1.

[0130] In a case that the integrator receives a zero reference signal in the first phase and the second phase, the first coefficient is equal to 0.

[0131] In the embodiment, the reference voltage may be positive, negative or zero, so that the analog-to-digital converter serves as a bidirectional converter. That is, an input signal of the analog-to-digital converter may be positive or negative. In other embodiments, the reference signal is positive and the first coefficient is equal to 1. In this case, the analog-to-digital converter serves as a unidirectional converter. That is, the analog-to-digital converter converts only a positive input signal. In other embodiments, the reference signal is negative and the first coefficient is equal to −1. In this case, the analog-to-digital converter serves as a unidirectional converter. That is, the analog-to-digital converter converts only a negative input signal. The reference signal and the first coefficient are not limited in the present disclosure.

[0132] Further, whether the integrator receives a positive reference voltage signal, a negative reference voltage signal or a zero reference signal in the first phase and the second phase of a current operation cycle is determined based on an output signal of the comparison circuit at an output end of the second phase of the operation cycle immediately before the current operation cycle.

[0133] In analog-to-digital conversion, the analog-to-digital converter sequentially operates in the reset mode, the sigma-delta analog-to-digital conversion mode and the cyclic conversion mode, to perform analog-to-digital conversion. Correspondingly, the integrator 1 sequentially operates in the return-to-zero mode, the first integral mode and the second integral mode. It should be noted that the integrator 1 is further applicable to a scenario other than the analog-to-digital converter. Therefore, in other embodiments, the integrator 1 operates in these modes separately or operate in these modes in any order, and unnecessarily operates in the above three modes sequentially, which is not limited in the present disclosure. For example, in a case that the integrator serves as a sampling holder, the integrator operates in only the zero-return mode. In a case that the integrator is configured to integrate a current, the integrator operates in only the first integral mode or sequentially operates in the first integral mode and the second integral mode.

[0134] In the analog-to-digital conversion, the integrator 1 operates in the return-to-zero mode in a first cycle, and operates in the first integral mode for n cycles, and finally operates in the second integral mode for m cycles, where n and m are greater than or equal to 1.

[0135] Further, in the first integral mode, the analog-to-digital converter generates a first result and residual charges. The residual charges are stored in the four integral capacitors. In the second integral mode, the analog-to-digital converter receives the residual charges and generates a second result, and outputs a digital signal corresponding to the input voltage based on the first result and the second result.

[0136] Further, in a case that an accuracy of the analog-to-digital conversion is determined, conversion accuracy of the first integral mode and conversion accuracy of the second integral mode are determined based on balance between accuracy and efficiency, so as to determine the number of operation cycles of the integrator 1 in each mode.

[0137] For example, in a case that the accuracy of the analog-to-digital conversion is 2N, if the conversion accuracy of the analog-to-digital converter in the first integral mode and the conversion accuracy of the analog-to-digital converter in the second integral mode are respectively set to be N, the number of operation cycles of the analog-to-digital converter operating in the first integral mode is equal to 2.sup.N and the number of operation cycles of the analog-to-digital converter operating in the second integral mode is equal to N.

[0138] Further, in any operation mode of the integrator, each cycle includes two phases. The integrator includes an offset capacitor, which is configured to store the offset voltage of the operational amplifier in the first phase. The voltage of the offset capacitor counteracts the offset voltage of the operational amplifier in the second phase, so that the integrator can eliminate the offset voltage of the operational amplifier in any operation mode.

[0139] In the embodiment, the comparison circuit 2 is configured to generate a high-bit comparison signal in the first integral mode and generate a low-bit comparison signal in the second integral mode.

[0140] Further, the comparison circuit 2 is configured to compare the output signal of the integrator with a first threshold to obtain a first comparison signal, and compare the output signal of the integrator with a second threshold to obtain a second comparison signal. The first threshold is greater than the second threshold.

[0141] In a case that the integrator operates in the first integral mode, the first comparison signal and the second comparison signal are a first high-bit comparison signal and a second high-bit comparison signal respectively. In a case that the integrator operates in the second integral mode, the first comparison signal and the second comparison signal are a first low-bit comparison signal and a second low-bit comparison signal respectively.

[0142] In the embodiment, the comparison circuit 2 includes a first comparator CMP1 and a second comparator CMP2. An output signal of the first comparator CMP1 is referred to as a first comparison signal, and an output signal of the second comparator CMP2 is referred to as a second comparison signal. In other embodiments, the first comparison signal and the second comparison signal are outputted by a comparator with two thresholds (for example, a hysteresis comparator), which is not limited in the present disclosure.

[0143] In the embodiment, the control logic circuit 3 includes a first storage logic circuit 31, a second storage logic circuit 32, a third storage logic circuit 33, a fourth storage logic circuit 34, a first state logic circuit 35, a second state logic circuit 36 and a combination logic circuit 37.

[0144] Input terminals of the first comparator CMP1 receive a first threshold +V.sub.TH, an output voltage V.sub.OP of the first output terminal b.sub.1 of the operational amplifier OTA, and an output voltage V.sub.ON of the second output terminal b.sub.2 of the operational amplifier OTA. In the first integral mode, the first comparator CMP1 outputs a first high-bit comparison signal, and the first high-bit comparison signal is stored in the first storage logic circuit 31. In the second integral mode, the first comparator CMP1 outputs a first low-bit comparison signal, and the first low-bit comparison signal is stored in the third storage logic circuit 33.

[0145] Input terminals of the second comparator CMP2 receive a second threshold −V.sub.TH, the output voltage V.sub.OP of the first output terminal b.sub.1 of the operational amplifier OTA, and the output voltage V.sub.ON of the second output terminal b.sub.2 of the operational amplifier OTA. In the first integral mode, the second comparator CMP2 outputs a second high-bit comparison signal, and the second high-bit comparison signal is stored in the second storage logic circuit 32. In the second integral mode, the second comparator CMP2 outputs a second low-bit comparison signal, and the second low-bit comparison signal is stored in the fourth storage logic circuit 34.

[0146] Further, the first comparator compares (V.sub.OP−V.sub.ON) with the first threshold +V.sub.TH to output the first comparison signal. The second comparator compares (V.sub.OP−V.sub.ON) with the second threshold −V.sub.TH to output the second comparison signal.

[0147] In an embodiment, an inverting input terminal of the first comparator CMP1 receives the first threshold +V.sub.TH, and a non-inverting input terminal of the second comparator CMP2 receives the second threshold −V.sub.TH.

[0148] In a case that (V.sub.OP−V.sub.ON) is greater than +V.sub.TH, the first comparison signal is at a high level and the second comparison signal is at a low level.

[0149] In a case that (V.sub.OP−V.sub.ON) is greater than or equal to −V.sub.TH and is less than or equal to +V.sub.TH, the first comparison signal is at a low level and the second comparison signal is at a low level.

[0150] In a case that (V.sub.OP−V.sub.ON) is less than −V.sub.TH, the first comparison signal is at a low level and the second comparison signal is at a high level.

[0151] Further, the first state logic circuit 35 acquires a first digital signal V.sub.OUTP based on all first high-bit comparison signals stored in the first storage logic circuit 31 and all first low-bit comparison signals stored in the third storage logic circuit 33.

[0152] Further, the second state logic circuit 36 acquires a second digital signal V.sub.OUTN based on all second high-bit comparison signals stored in the second storage logic circuit 32 and all second low-bit comparison signals stored in the fourth storage logic circuit 34.

[0153] In the embodiment, the combination logic circuit 37 outputs a digital signal V.sub.OUT corresponding to the input voltage based on the first digital signal V.sub.OUTP and the second digital signal V.sub.OUTN.

[0154] Further, the control logic circuit 3 further includes a control logic circuit 38. The control logic circuit 38 is configured to generate a control signal, for controlling the multiple switches to be switched on or switched off, to control the multiple capacitors to be charged or discharge, so as to control the integrator 1 to operate in the return-to-zero mode, the first integral mode or the second integral mode.

[0155] FIG. 5 and FIG. 6 are circuit diagrams of the integrator operating in the return-to-zero mode according to an embodiment of the present disclosure. Each operation cycle of the integrator 1 includes a first phase and a second phase. FIG. 5 is a circuit diagram of the integrator operating in the first phase of the return-to-zero mode. As shown in FIG. 5, the switches S.sub.13, S.sub.15, S.sub.18, S.sub.20, S.sub.23, S.sub.24, S.sub.27, S.sub.28, S.sub.29, S.sub.30, S.sub.31, S.sub.32, S.sub.36, S.sub.38, S.sub.40, S.sub.41, S.sub.43, and S.sub.45 are controlled to be switched on, to control the integrator to operate in the first phase of the return-to-zero mode.

[0156] FIG. 6 is a circuit diagram of the integrator operating in the second phase of the return-to-zero mode. As shown in FIG. 6, the switches S.sub.13, S.sub.16, S.sub.17, S.sub.20, S.sub.25, S.sub.26, S.sub.29, S.sub.30, S.sub.31, S.sub.32, S.sub.37, S.sub.39, S.sub.42 and S.sub.44 are controlled to be switched on, to control the integrator to operate in the second phase of the return-to-zero mode.

[0157] Further, as can be seen from FIG. 5 and FIG. 6, in the return-to-zero mode, in a case of C.sub.IN=C.sub.I1=C.sub.I2, C.sub.R=C.sub.I3=C.sub.I4, C.sub.H=C.sub.H1=C.sub.H2 and C.sub.F=C.sub.F1=C.sub.F2=C.sub.F3=C.sub.F4, the output signal of the operational amplifier OTA in the second phase is expressed as:

[00001]$\begin{array}{cc}{V^{\prime }}_{OP}\left(i\right)-{V^{\prime }}_{ON}\left(i\right)=\frac{C_{\mathrm{IN}}}{C_F}\left[V_{\mathrm{INP}}\left(i\right)-V_{\mathrm{INN}}\left(i\right)\right]+\frac{C_{\mathrm{IN}}+2C_F+C_R}{2C_F}\left({V^{\prime }}_{OS}-V_{\mathrm{OS}}\right)& \end{array}$

[0158] In the above equation, V′.sub.OP(i) and V′.sub.ON(i) respectively represent a voltage of the first output terminal of the operational amplifier and a voltage of the second output terminal of the operational amplifier in the second phase. V.sub.INP(i) and V.sub.INN(i) respectively represent a positive signal of the input voltage and a negative signal of the input voltage in an (i)th period. V.sub.OS and V′.sub.OS respectively represent an offset voltage of the analog-to-digital converter in the first phase and an offset voltage of the analog-to-digital converter in the second phase.

[0159] Further, in a case of C.sub.IN=C.sub.R=C.sub.F and V.sub.OS=V′.sub.OS, the above equation is transformed into:

V′.sub.OP(i)−V′.sub.ON(i)=[V.sub.INP(i)−V.sub.INN(i)]

[0160] It can be seen from the above equation that the offset voltage of the operational amplifier is eliminated by switching between two phases, and the input signal is sampled and is stored in the integral capacitors.

[0161] In the return-to-zero mode, the integrator is configured as an auto-zeroed sampling hold circuit. The integral capacitors C.sub.F1, C.sub.F2, C.sub.F3 and C.sub.F4 are cleared in the first phase, and samples the input voltage signal and stores the sampled input voltage signal in the second phase. The offset capacitors store the offset voltage of the operational amplifier in the first phase. The voltages of the offset capacitors counteract the offset voltage of the operational amplifier in the second phase, so that the integrator can eliminate the offset voltage of the operational amplifier in the return-to-zero mode.

[0162] Therefore, the offset voltage and low frequency noise of the operational amplifier can be eliminated, thereby improving the accuracy of the analog-to-digital converter.

[0163] FIG. 7 is a circuit diagram of the integrator operating in a first phase of the first integral mode according to an embodiment of the present disclosure. FIG. 8 is a circuit diagram of the integrator operating in a second phase of the first integral mode according to an embodiment of the present disclosure. As shown in FIG. 7 and FIG. 8, it is assumed that the predetermined number of cycles for the first integral mode is equal to N, the integrator in controlled, in any of the following three manners, to operate in first (N−1) cycles of the first integral mode. Each cycle includes a first phase and a second phase.

[0164] In a first manner, the switches S.sub.11, S.sub.15, S.sub.18, S.sub.21, S.sub.23, S.sub.24, S.sub.27, S.sub.28, S.sub.36, S.sub.38, S.sub.40, S.sub.41, S.sub.43, and S.sub.45 are controlled to be switched on, to control the integrator to operate in the first phase of the first (N−1) cycles of the first integral mode.

[0165] In addition, the switches S.sub.12, S.sub.16, S.sub.17, S.sub.22, S.sub.23, S.sub.24, S.sub.29, S.sub.30, S.sub.31, S.sub.32, S.sub.37, S.sub.39, S.sub.42, and S.sub.44 are controlled to be switched on, to control the integrator to operate in the second phase the first (N−1) cycles of the first integral mode.

[0166] In a second manner, the switches S.sub.13, S.sub.15, S.sub.18, S.sub.20, S.sub.23, S.sub.24, S.sub.27, S.sub.28, S.sub.36, S.sub.38, S.sub.40, S.sub.41, S.sub.43, and S.sub.45 are controlled to be switched on, to control the integrator to operate in the first phase of the first (N−1) cycles of the first integral mode.

[0167] In addition, the switches S.sub.13, S.sub.16, S.sub.17, S.sub.20, S.sub.23, S.sub.24, S.sub.29, S.sub.30, S.sub.31, S.sub.32, S.sub.37, S.sub.39, S.sub.42 and S.sub.44 are controlled to be switched on, to control the integrator to operate in the second phase of the first (N−1) cycles of the first integral mode.

[0168] In a third manner, the switches S.sub.12, S.sub.15, S.sub.18, S.sub.22, S.sub.23, S.sub.24, S.sub.27, S.sub.28, S.sub.36, S.sub.38, S.sub.40, S.sub.41, S.sub.43, and S.sub.45 are controlled to be switched on, to control the integrator to operate in the first phase of the first (N−1) cycles of the first integral mode.

[0169] In addition, the switches S.sub.11, S.sub.16, S.sub.17, S.sub.21, S.sub.23, S.sub.24, S.sub.29, S.sub.30, S.sub.31, S.sub.32, S.sub.37, S.sub.39, S.sub.42, and S.sub.44 are controlled to be switched on, to control the integrator to operate in the second phase of the first (N−1) cycles of the first integral mode.

[0170] Further, as can be seen from FIG. 7 and FIG. 8, in the first integral mode, in a case of C.sub.IN=C.sub.I1=C.sub.I2, C.sub.R=C.sub.I3=C.sub.I4, C.sub.H=C.sub.H1=C.sub.H2, and C.sub.F=C.sub.F1=C.sub.F2=C.sub.F3=C.sub.F4, the output signal of the operational amplifier OTA in the second phase is expressed as:

[00002]$\begin{array}{cc}{V^{\prime }}_{\mathrm{OP}}\left(i\right)-{V^{\prime }}_{\mathrm{ON}}\left(i\right)=\frac{C_{IN}}{C_F}\left[V_{INP}\left(i\right)-V_{INN}\left(i\right)\right]+D\left(i\right)\frac{C_R}{C_F}\left[V_{RP}\left(i\right)-V_{RN}\left(i\right)\right]+\frac{C_{IN}+2C_F+C_R}{2C_F}\left({V^{\prime }}_{\mathrm{OS}}-V_{\mathrm{OS}}\right)+\left[{V^{\prime }}_{\mathrm{OP}}\left(i-1\right)-{V^{\prime }}_{\mathrm{ON}}\left(i-1\right)\right]& \end{array}$

[0171] In the above equation, i is greater than or equal to 1 and is less than or equal to (N−1). V′.sub.OP(i) and V′.sub.ON(i) respectively represent a voltage of the first output terminal of the operational amplifier and a voltage of the second output terminal of the operational amplifier in the second phase of the (i)th cycle. V.sub.INP(i) and V.sub.INN(i) respectively represent a positive signal and a negative signal of the input voltage in the (i)th cycle. D(i) is determined based on an output result of the comparator at an output end of the second phase of the (i−1)th cycle. V.sub.RN(i) and V.sub.RN(i) respectively represent a positive signal and a negative signal of the reference voltage in the (i)th cycle. V.sub.OS and V′.sub.OS respectively represent an offset voltage of the analog-to-digital converter in the first phase and an offset voltage of the analog-to-digital converter in the second phase. V′.sub.OP(i−1) and V′.sub.ON(i−1) respectively represent a voltage of the first output terminal of the operational amplifier and a voltage of the second output terminal of the operational amplifier in the second phase of the (i−1)th cycle.

[0172] Further, in a case of C.sub.IN=C.sub.R=C.sub.F and V.sub.OS=V′.sub.OS, the above equation is transformed into:

V′.sub.OP(i)−V′.sub.ON(i)=[V.sub.INP(i)−V.sub.INN(i)]+D(i)[V.sub.RP(i)−V.sub.RN(i)]+[V′.sub.OP(i−1)−V′.sub.ON(i−1)]

[0173] It can be seen from the above equation that in the first (N−1) cycles of the first integral mode, the integrator samples the input voltage signal and the reference voltage signal and outputs the integral signal. The integral signal is a differential output signal of the operational amplifier OTA. That is, in the first integral mode, in the second phase of each cycle other than the last cycle, the output signal of the operational amplifier OTA is equal to a sum of the differential output signal of the operational amplifier OTA in an operation cycle immediately before the cycle, the input voltage signal and the first signal. The first signal is a product of the reference voltage signal and the first coefficient. The first coefficient is expressed as D(i).

[0174] Further, in a case that i is equal to 1, V′.sub.OP(i−1) and V′.sub.ON(i−1) are equal to zero.

[0175] Further, in a case that the integrator receives a positive reference voltage signal (V.sub.RP−V.sub.RN) in the first phase (in this case, the third input capacitor C.sub.I3 receives a positive signal V.sub.RP of the reference voltage and the fourth input capacitor C.sub.I4 receives the negative signal V.sub.RN of the reference voltage) and receives a negative reference voltage signal (V.sub.RN−V.sub.RP) in the second phase (in this case, the third input capacitor C.sub.I3 receives the negative signal V.sub.RN of the reference voltage and the fourth input capacitor C.sub.I4 receives the positive signal V.sub.RP of the reference voltage), the first coefficient D(i) is equal to 1.

[0176] In a case that the integrator receives the negative reference voltage signal (V.sub.RN−V.sub.RP) in the first phase (in this case, the third input capacitor C.sub.I3 receives the negative signal V.sub.RN of the reference voltage and the fourth input capacitor C.sub.I4 receives the positive signal V.sub.RP of the reference voltage) and receives the positive reference voltage signal (V.sub.RP−V.sub.RN) in the second phase (in this case, the third input capacitor C.sub.I3 receives the positive signal V.sub.RP of the reference voltage and the fourth input capacitor C.sub.I4 receives the negative signal V.sub.RN of the reference voltage), the first coefficient D(i) is equal to −1.

[0177] In a case that the integrator receives a zero reference signal in both the first phase and the second phase (in this case, the third input capacitor C.sub.I3 receives a common mode voltage signal V.sub.CM and the fourth input capacitor C.sub.I4 receives the common mode voltage signal V.sub.CM), the first coefficient D(i) is equal to 0.

[0178] Further, whether the integrator receives a positive reference voltage signal, a negative reference voltage signal or a zero reference signal in the first phase and the second phase of a current operation cycle is determined based on an output signal of the comparison circuit at an output end of the second phase of the operation cycle immediately before the current operation cycle, so as to determine the first coefficient D(i) based on the output signal of the comparison circuit at the output end of the second phase of the operation cycle immediately before the current operation cycle.

[0179] Further, D(i) is determined based on the output signal of the comparison circuit at the output end of the second phase of the (i−1)th cycle by: determining D(i) to be 1 in a case that the output signal of the first comparator is at a low level and the output signal of the second comparator is at a high level; determining D(i) to be 0 in a case that the output signal of the first comparator is at a low level and the output signal of the second comparator is at a low level; and determining D(i) to be −1 in a case that the output signal of the first comparator is at a high level and the output signal of the second comparator is at a high level.

[0180] Further, the first comparator compares (V.sub.OP−V.sub.ON) with the first threshold +V.sub.TH to output a first comparison signal. The second comparator compares (V.sub.OP−V.sub.ON) with the second threshold −V.sub.TH to output a second comparison signal.

[0181] In a case that (V.sub.OP−V.sub.ON) is greater than +V.sub.TH, the first comparison signal is at a high level and the second comparison signal is at a low level.

[0182] In a case that (V.sub.OP−V.sub.ON) is greater than or equal to −V.sub.TH and is less than or equal to +V.sub.TH, the first comparison signal is at a low level and the second comparison signal is at a low level.

[0183] In a case that (V.sub.OP−V.sub.ON) is less than −V.sub.TH, the first comparison signal is at a low level and the second comparison signal is at a high level.

[0184] FIG. 9 is a circuit diagram of an integrator operating in the first phase of the first integral mode according to an embodiment of the present disclosure. FIG. 10 is a circuit diagram of an integrator operating in the second phase of the first integral mode according to an embodiment of the present disclosure. As shown in FIG. 9 and FIG. 10, the analog-to-digital converter is controlled, in the following three manners, to operate in the (N)th cycle of the first integral mode.

[0185] In a first manner, the switches S.sub.11, S.sub.14, S.sub.19, S.sub.21, S.sub.23, S.sub.24, S.sub.27, S.sub.28, S.sub.36, S.sub.38, S.sub.40, S.sub.41, S.sub.43, and S.sub.45 are controlled to be switched on, to control the integrator to operate in the first phase of the last cycle of the first integral mode.

[0186] In addition, the switches S.sub.12, S.sub.14, S.sub.19, S.sub.22, S.sub.23, S.sub.24, S.sub.29, S.sub.30, S.sub.31, S.sub.32, S.sub.37, S.sub.39, S.sub.42, and S.sub.44 are controlled to be switched on, to control the integrator to operate in the second phase of the last cycle of the first integral mode.

[0187] In a second manner, the switches S.sub.13, S.sub.14, S.sub.19, S.sub.20, S.sub.23, S.sub.24, S.sub.27, S.sub.28, S.sub.36, S.sub.38, S.sub.40, S.sub.41, S.sub.43, and S.sub.45 are controlled to be switched on, to control the integrator to operate in the first phase of the last cycle of the first integral mode.

[0188] In addition, the switches S.sub.13, S.sub.14, S.sub.19, S.sub.20, S.sub.23, S.sub.24, S.sub.29, S.sub.30, S.sub.31, S.sub.32, S.sub.37, S.sub.39, S.sub.42, and S.sub.44 are controlled to be switched on, to control the integrator to operate in the second phase of the last cycle of the first integral mode.

[0189] In the third manner, the switches S.sub.12, S.sub.14, S.sub.19, S.sub.22, S.sub.23, S.sub.24, S.sub.27, S.sub.28, S.sub.36, S.sub.38, S.sub.40, S.sub.41, S.sub.43, and S.sub.45 are controlled to be switched on, to control the integrator to operate in the first phase of the last cycle of the first integral mode.

[0190] In addition, the switches S.sub.11, S.sub.14, S.sub.19, S.sub.21, S.sub.23, S.sub.24, S.sub.29, S.sub.30, S.sub.31, S.sub.32, S.sub.37, S.sub.39, S.sub.42, and S.sub.44 are controlled to be switched on, to control the integrator to operate in the second phase of the last cycle of the first integral mode.

[0191] Further, it can be seen from FIG. 9 and FIG. 10 that in the (N)th cycle of the first integral mode, in a case of C.sub.IN=C.sub.I1=C.sub.I2, C.sub.R=C.sub.I3=C.sub.I4, C.sub.H=C.sub.H1=C.sub.H2, and C.sub.F=C.sub.F1=C.sub.F2=C.sub.F3=C.sub.F4, the output signal of the operational amplifier OTA in the second phase is expressed as:

[00003]${V^{\prime }}_{\mathrm{OP}}\left(N\right)-{V^{\prime }}_{\mathrm{ON}}\left(N\right)=D\left(N\right)\frac{C_R}{C_F}\left[V_{RP}\left(N\right)-V_{RN}\left(N\right)\right]+\frac{C_{IN}+2C_F+C_R}{2C_F}\left({V^{\prime }}_{\mathrm{OS}}-V_{\mathrm{OS}}\right)+\left[{V^{\prime }}_{\mathrm{OP}}\left(N-1\right)-{V^{\prime }}_{\mathrm{ON}}\left(N­1\right)\right]$

[0192] In the above equation, V′.sub.OP(N) and V′.sub.ON(N) respectively represent a voltage of the first output terminal of the operational amplifier and a voltage of the second output terminal of the operational amplifier in the second phase of the (N)th cycle. D(N) is determined based on the output result of the comparator at the output end of the second phase of the (N−1)th cycle. V.sub.RP(N) and V.sub.RN(N) respectively represent a positive signal and a negative signal of the reference voltage in the (N)th cycle. V.sub.OS and V′.sub.OS respectively represent the offset voltage of the analog-to-digital converter in the first phase and the offset voltage of the analog-to-digital converter in the second phase. V′.sub.OP(N−1) and V′.sub.ON(N−1) respectively represent a voltage of the first output terminal of the operational amplifier and a voltage of the second output terminal of the operational amplifier in the second phase of the (N−1)th cycle.

[0193] Further, in a case of C.sub.IN=C.sub.R=C.sub.F and V.sub.OS=V′.sub.OS, the above equation is transformed into:

V′.sub.OP(N)−V′.sub.ON(N)=D(N)[V.sub.RP(N)−V.sub.RN(N)]+[V′.sub.OP(N−1)−V′.sub.ON(N−1)]

[0194] It can be seen from the above equation that in the (N)th cycle of the first integral mode, the integrator does not sample the input voltage signal and superimposes the first signal on the output signal of the operation cycle immediately before the current operation cycle. The first signal is a product of the reference voltage signal and the first coefficient. The first coefficient is expressed as D(N).

[0195] Further, in a case that the integrator receives the positive reference voltage signal (V.sub.RP−V.sub.RN) in the first phase (in this case, the third input capacitor C.sub.I3 receives a positive signal V.sub.RP of the reference voltage and the fourth input capacitor C.sub.I4 receives the negative signal V.sub.RN of the reference voltage) and receives the negative reference voltage signal (V.sub.RN−V.sub.RP) in the second phase (in this case, the third input capacitor C.sub.I3 receives the negative signal V.sub.RN of the reference voltage and the fourth input capacitor C.sub.I4 receives the positive signal V.sub.RP of the reference voltage), the first coefficient D(N) is equal to 1.

[0196] In a case that the integrator receives the negative reference voltage signal (V.sub.RN−V.sub.RP) in the first phase (in this case, the third input capacitor C.sub.I3 receives the negative signal V.sub.RN of the reference voltage, and the fourth input capacitor C.sub.I4 receives the positive signal V.sub.RP of the reference voltage) and receives the positive reference voltage signal (V.sub.RP−V.sub.RN) in the second phase (in this case, the third input capacitor C.sub.I3 receives the positive signal V.sub.RP of the reference voltage and the fourth input capacitor C.sub.I4 receives the negative signal V.sub.RN of the reference voltage), the first coefficient D(N) is equal to −1.

[0197] In a case that the integrator receives a zero reference signal in both the first phase and the second phase (in this case, the third input capacitor C.sub.I3 receives a common mode voltage signal V.sub.CM and the fourth input capacitor C.sub.I4 receives the common mode voltage signal V.sub.CM), the first coefficient D(N) is equal to 0.

[0198] Further, whether the integrator receives a positive reference voltage signal, a negative reference voltage signal or a zero reference signal in the first phase and the second phase of a current operation cycle is determined based on an output signal of the comparison circuit at an output end of the second phase of the operation cycle immediately before the current operation cycle, so as to determine the first coefficient D(N) based on the output signal of the comparison circuit at the output end of the second phase of the operation cycle immediately before the current operation cycle.

[0199] Further, D(N) is determined based on the output signal of the comparator at the output end of the second phase of the (N−1)th cycle by: determining D(N) to be 1 in a case that the output signal of the first comparator is at a low level and the output signal of the second comparator is at a high level; determining D(N) to be 0 in a case that the output signal of the first comparator is at a low level and the output signal of the second comparator is at a low level; and determining D(N) to be −1 in a case that the output signal of the first comparator is at a high level and the output signal of the second comparator is at a low level.

[0200] Further, the first comparator compares (V.sub.OP−V.sub.ON) with the first threshold +V.sub.TH to output a first comparison signal. The second comparator compares (V.sub.OP−V.sub.ON) with the second threshold −V.sub.TH to output a second comparison signal.

[0201] In a case that (V.sub.OP−V.sub.ON) is greater than +V.sub.TH, the first comparison signal is at a high level and the second comparison signal is at a low level.

[0202] In a case that (V.sub.OP−V.sub.ON) is greater than or equal to −V.sub.TH and is less than or equal to +V.sub.TH, the first comparison signal is at a low level and the second comparison signal is at a low level.

[0203] In a case that (V.sub.OP−V.sub.ON) is less than −V.sub.TH, the first comparison signal is at a low level and the second comparison signal is at a high level.

[0204] In FIGS. 7 to 10, in the first integral mode, the analog-to-digital converter generates a first result and residual charges. The residual charges are stored in the four integral capacitors. In the second integral mode shown in FIGS. 11 to 14, the analog-to-digital converter receives the residual charges and generates a second result, and performs analog-to-digital conversion based on the first result and the second result.

[0205] In the case that the integrator operates in the first integral mode, the capacitor C.sub.F1 and the capacitor C.sub.F2 operate in the same way and are connected in the same manner at any time. That is, the capacitor C.sub.F1 and the capacitor C.sub.F2 are simultaneously charged or simultaneously discharge. Therefore, the capacitor C.sub.F1 and the capacitor C.sub.F2 may be replaced by one integral capacitor C.sub.F. Similarly, the capacitor C.sub.F3 and the capacitor C.sub.F4 operate in the same way and are connected in the same manner at any time. That is, the capacitor C.sub.F3 and the capacitor C.sub.F4 are simultaneously charged or simultaneously discharge. Therefore, the capacitor C.sub.F3 and the capacitor C.sub.F4 may be replaced by one integral capacitor C.sub.F. In order to describe the operation process in the second integral mode, four integral capacitors are used to store the integral signal, which is not limited in the present disclosure.

[0206] FIG. 11 is a circuit diagram of the integrator operating in a first phase of the second integral mode according to an embodiment of the present disclosure. FIG. 12 is a circuit diagram of the integrator operating in a second phase of the second integral mode according to an embodiment of the present disclosure. As shown in FIG. 11 and FIG. 12, the analog-to-digital converter is controlled, in the following three manners, to operate in the second integral mode.

[0207] In a first manner, the switches S.sub.11, S.sub.14, S.sub.19, S.sub.21, S.sub.23, S.sub.24, S.sub.27, S.sub.28, S.sub.36, S.sub.39, S.sub.40, S.sub.41, S.sub.42, and S.sub.45 are controlled to be switched on, to control the integrator to operate in the first phase of the second integral mode.

[0208] In addition, the switches S.sub.12, S.sub.22, S.sub.23, S.sub.24, S.sub.29, S.sub.30, S.sub.31, S.sub.32, S.sub.33, S.sub.34, S.sub.36, S.sub.39, S.sub.42, and S.sub.45 are controlled to be switched on, to control the integrator to operate in the second phase of the second integral mode.

[0209] In a second manner, the switches S.sub.13, S.sub.14, S.sub.19, S.sub.20, S.sub.23, S.sub.24, S.sub.27, S.sub.28, S.sub.36, S.sub.39, S.sub.40, S.sub.41, S.sub.42, and S.sub.45 are controlled to be switched on, to control the integrator to operate in the first phase of the second integral mode.

[0210] In addition, the switches S.sub.13, S.sub.20, S.sub.23, S.sub.24, S.sub.29, S.sub.30, S.sub.31, S.sub.32, S.sub.33, S.sub.34, S.sub.36, S.sub.39, S.sub.42, and S.sub.45 are controlled to be switched on, to control the integrator to operate in the second phase of the second integral mode.

[0211] In a third manner, the switches S.sub.12, S.sub.14, S.sub.19, S.sub.22, S.sub.23, S.sub.24, S.sub.27, S.sub.28, S.sub.36, S.sub.39, S.sub.40, S.sub.41, S.sub.42, and S.sub.45 are controlled to be switched on, to control the integrator to operate in the first phase of the second integral mode.

[0212] In addition, the switches S.sub.11, S.sub.21, S.sub.23, S.sub.24, S.sub.29, S.sub.30, S.sub.31, S.sub.32, S.sub.33, S.sub.34, S.sub.36, S.sub.39, S.sub.42 and S.sub.45 are controlled to be switched on, to control the integrator to operate in the second phase of the second integral mode.

[0213] In the embodiment, in the second integral mode, the integral capacitor is split into two capacitors. At the positive terminal, the integral capacitor is split into capacitors C.sub.F1 and C.sub.F2. At the negative terminal, the integral capacitor is split into capacitors C.sub.F3 and C.sub.F4. Capacitors C.sub.F1 and C.sub.F3 store the integral charges in the first phase, and are connected between the input terminal of the operational amplifier and the output terminal of the operational amplifier in the second phase to convert a charge signal into a voltage signal. At the same time, the capacitors C.sub.F2 and C.sub.F4 redistribute the charges. In the second phase, negative plates of capacitors C.sub.F2 and C.sub.F4 are connected to the common mode voltage V.sub.CM, and voltages of the positive plates of C.sub.F2 and C.sub.F4 are close to V.sub.CM, so that all charges on the capacitor C.sub.F2 are transferred to the capacitor C.sub.F1 and all charges on the capacitor C.sub.F4 are transferred to the capacitor C.sub.F3 in the second phase. Because of C.sub.F1=C.sub.F2 and C.sub.F3=C.sub.F4, the charges on C.sub.F1 and the charges on C.sub.F3 are doubled. Because of Q=V*C and V=Q/C, the voltage of C.sub.F1 and the voltage of C.sub.F3 are doubled, so that the output voltage of operational amplifier is doubled. In addition, the input capacitors C.sub.I1 and C.sub.I2 discharge in the first phase and sample the output signal in the second phase to prepare for amplification in the next cycle.

[0214] Further, as can be seen from FIG. 11 and FIG. 12, in the (j)th cycle of the second integral mode, in a case of C.sub.IN=C.sub.I1=C.sub.I2, C.sub.R=C.sub.I3=C.sub.I4, C.sub.H=C.sub.H1=C.sub.H2, and C.sub.F=C.sub.F1=C.sub.F2=C.sub.F3=C.sub.F4, the output signal of the operational amplifier OTA in the second phase is expressed as:

[00004]${V^{\prime }}_{\mathrm{OP}}\left(j\right)-{V^{\prime }}_{\mathrm{ON}}\left(j\right)=\frac{2C_F}{C_F}\left[{V^{\prime }}_{\mathrm{OP}}\left(j-1\right)-{V^{\prime }}_{\mathrm{ON}}\left(j-1\right)\right]+D\left(j\right)\frac{2C_R}{C_F}\left[V_{RP}-V_{RN}\right]+\frac{C_{IN}+C_R}{C_F}\left({V^{\prime }}_{\mathrm{OS}}-V_{\mathrm{OS}}\right)$

[0215] In the above equation, V′.sub.OP(j) and V′.sub.ON(j) respectively represent a voltage of the first output terminal of the operational amplifier and a voltage of the second output terminal of the operational amplifier in the second phase of the (j)th cycle. D (j) is determined based on the output result of the comparator at the output end of the second phase of the (j−1)th cycle. V.sub.RP and V.sub.RN respectively present a positive signal and a negative signal of the reference voltage. V.sub.OS and V′.sub.OS respectively present an offset voltage of the analog-to-digital converter in the first phase and an offset voltage of the analog-to-digital converter in the second phase. V′.sub.OP(j−1) and V.sub.ON (j−1) respectively represent a voltage of the first output terminal of the operational amplifier and a voltage of the second output terminal of the operational amplifier in the second phase of the (j−1)th cycle. Further, in a case of C.sub.IN=C.sub.R=C.sub.F and V.sub.OS=V′.sub.OS, the above equation is transformed into:

V′.sub.OP(j)−V′.sub.ON(j)=2[V′.sub.OP(j−1)−V′.sub.ON(j−1)]+2*D(j)[V.sub.RP−V.sub.RN]

[0216] It can be seen from the above equation that in the second integral mode, the integrator amplifies the output voltage of the integrator in an operation cycle immediately before the current operation cycle. The integrator is configured to sample the reference voltage signal and output an integral signal. The integral signal outputted by the integrator is equal to a multiple of the sum of the first signal and the integral signal outputted by the integrator in the operation cycle immediately before the current operation cycle. The first signal is a product of the reference voltage signal and the first coefficient. The first coefficient is expressed as D(j).

[0217] Further, in a case that the integrator receives a positive reference voltage signal (V.sub.RP−V.sub.RN) in the first phase (in this case, the third input capacitor C.sub.I3 receives a positive signal V.sub.RP of the reference voltage and the fourth input capacitor C.sub.I4 receives the negative signal V.sub.RN of the reference voltage) and receives a negative reference voltage signal (V.sub.RN−V.sub.RP) in the second phase (in this case, the third input capacitor C.sub.I3 receives the negative signal V.sub.RN of the reference voltage and the fourth input capacitor C.sub.I4 receives the positive signal V.sub.RP of the reference voltage), the first coefficient D(j) is equal to 1.

[0218] In a case that the integrator receives the negative reference voltage signal (V.sub.RN−V.sub.RP) in the first phase (in this case, the third input capacitor C.sub.I3 receives the negative signal V.sub.RN of the reference voltage and the fourth input capacitor C.sub.I4 receives the positive signal V.sub.RP of the reference voltage) and receives the positive reference voltage signal (V.sub.RP−V.sub.RN) in the second phase (in this case, the third input capacitor C.sub.I3 receives the positive signal V.sub.RP of the reference voltage and the fourth input capacitor C.sub.I4 receives the negative signal V.sub.RN of the reference voltage), the first coefficient D(j) is equal to −1.

[0219] In a case that the integrator receives a zero reference signal in both the first phase and the second phase (in this case, the third input capacitor C.sub.I3 receives a common mode voltage signal V.sub.CM and the fourth input capacitor C.sub.I4 receives the common mode voltage signal V.sub.CM), the first coefficient D(j) is equal to 0.

[0220] Further, whether the integrator receives a positive reference voltage signal, a negative reference voltage signal or a zero reference signal in the first phase and the second phase of a current operation cycle is determined based on an output signal of the comparison circuit at an output end of the second phase of the operation cycle immediately before the current operation cycle, so as to determine the first coefficient D(j) based on the output signal of the comparison circuit at the output end of the second phase of the operation cycle immediately before the current operation cycle.

[0221] D(j) is determined based on the output signal of the comparison circuit at the output end of the second phase of the (j−1)th cycle by: determining D(j) to be 1 in a case that the output signal of the first comparator is at a low level and the output signal of the second comparator is at a high level; determining D(j) to be 0 in a case that the output signal of the first comparator is at a low level and the output signal of the second comparator is at a low level; and determining D(j) to be −1 in a case that the output signal of the first comparator is at a high level and the output signal of the second comparator is at a low level.

[0222] Further, the first comparator compares (V.sub.OP−V.sub.ON) with the first threshold +V.sub.TH and outputs a first comparison signal. The second comparator compares (V.sub.OP−V.sub.ON) with the second threshold −V.sub.TH and outputs a second comparison signal.

[0223] In a case that (V.sub.OP−V.sub.ON) is greater than +V.sub.TH, the first comparison signal is at a high level and the second comparison signal is at a low level.

[0224] In a case that (V.sub.OP−V.sub.ON) is greater than or equal to −V.sub.TH and is less than or equal to +V.sub.TH, the first comparison signal at is a low level and the second comparison signal is at a low level.

[0225] In a case that (V.sub.OP−V.sub.ON) is less than −V.sub.TH, the first comparison signal is at a low level and the second comparison signal is at a high level.

[0226] FIG. 13 is a circuit diagram of the integrator operating in the first phase of the second integral mode according to an embodiment of the present disclosure. FIG. 14 is a circuit diagram of the integrator operating in the second phase of the second integral mode according to the embodiment of the present disclosure. As shown in FIG. 13 and FIG. 14, the analog-to-digital converter is controlled, in the following three manners, to operate in the second integral mode.

[0227] In a first manner, the switches S.sub.11, S.sub.14, S.sub.19, S.sub.21, S.sub.27, S.sub.28, S.sub.35, S.sub.36, S.sub.39, S.sub.40, S.sub.41, S.sub.42, S.sub.45 and S.sub.46 are controlled to be switched on, to control the integrator to operate in the first phase of the second integral mode.

[0228] In addition, the switches S.sub.12, S.sub.14, S.sub.19, S.sub.22, S.sub.25, S.sub.26, S.sub.30, S.sub.31, S.sub.35, S.sub.37, S.sub.39, S.sub.42, S.sub.44 and S.sub.46 are controlled to be switched on, to control the integrator to operate in the second phase of the second integral mode.

[0229] In a second manner, the switches S.sub.13, S.sub.14, S.sub.19, S.sub.20, S.sub.27, S.sub.28, S.sub.35, S.sub.36, S.sub.39, S.sub.40, S.sub.41, S.sub.42, S.sub.45, and S.sub.46 are controlled to be switched on, to control the integrator to operate in the first phase of the second integral mode.

[0230] In addition, the switches S.sub.13, S.sub.14, S.sub.19, S.sub.20, S.sub.25, S.sub.26, S.sub.30, S.sub.31, S.sub.35, S.sub.37, S.sub.39, S.sub.42, S.sub.44 and S.sub.46 are controlled to be switched on, to control the integrator to operate in the second phase of the second integral mode.

[0231] In a third manner, the switches S.sub.12, S.sub.14, S.sub.19, S.sub.22, S.sub.27, S.sub.28, S.sub.35, S.sub.36, S.sub.39, S.sub.40, S.sub.41, S.sub.42, S.sub.45 and S.sub.46 are controlled to be switched on, to control the integrator to operate in the first phase of the second integral mode.

[0232] In addition, the switches S.sub.11, S.sub.14, S.sub.19, S.sub.21, S.sub.25, S.sub.26, S.sub.30, S.sub.31, S.sub.35, S.sub.37, S.sub.39, S.sub.42, S.sub.44 and S.sub.46 are controlled to be switched on, to control the integrator to operate in the second phase of the second integral mode.

[0233] In the embodiment, in the second integral mode, the integral capacitor C.sub.F is split into two capacitors. At the positive terminal, the integral capacitor is split into capacitors C.sub.F1 and C.sub.F2. At the negative terminal, the integral capacitor is split into capacitors C.sub.F3 and C.sub.F4. The capacitors C.sub.F1 and C.sub.F3 store the integral charges in the first phase, and are connected between the input terminal of the operational amplifier and the output terminal of the operational amplifier in the second phase to convert a charge signal into a voltage signal. At the same time, the capacitors C.sub.I1 and C.sub.I2 redistribute the charges. The capacitors C.sub.I1 and C.sub.I2 sample the output voltage and storage the sampled output voltage in the operation cycle immediately before the current operation cycle. In the second phase, negative plates of the capacitors C.sub.I1 and C.sub.I2 are connected to the common mode voltage V.sub.CM, and voltages of the positive plates of C.sub.I1 and C.sub.I2 are close to V.sub.CM, so that all charges on the capacitor C.sub.I1 are transferred to the capacitor C.sub.F1 and all charges on C.sub.I2 are transferred to the capacitor C.sub.F3 in the second phase. Because of C.sub.F1=C.sub.I1 and C.sub.F3=C.sub.I2, the charges on C.sub.F1 and the charges on C.sub.F3 are doubled. Because of Q=V*C and V=Q/C, the voltage of C.sub.F1 and the voltage of C.sub.F3 are doubled, so that the output voltage of operational amplifier is doubled. In addition, the integral capacitors C.sub.F2 and C.sub.F4 discharge in the first phase and sample the output signal in the second phase to prepare for amplification in the next period.

[0234] Further, as can be seen from FIG. 13 and FIG. 14, in the (j)th cycle of the second integral mode, in a case of C.sub.IN=C.sub.I1=C.sub.I2, C.sub.R=C.sub.I3=C.sub.I4, C.sub.H=C.sub.H1=C.sub.H2, and C.sub.F=C.sub.F1=C.sub.F2=C.sub.F3=C.sub.F4, the output signal of the operational amplifier OTA in the second phase is expressed as:

[00005]${V^{\prime }}_{\mathrm{OP}}\left(j\right)-{V^{\prime }}_{\mathrm{ON}}\left(j\right)=\frac{C_F+C_{IN}}{C_F}\left[{V^{\prime }}_{\mathrm{OP}}\left(j-1\right)-{V^{\prime }}_{\mathrm{ON}}\left(j-1\right)\right]+D\left(j\right)\frac{2C_R}{C_F}\left[V_{RP}-V_{RN}\right]+\frac{C_{IN}+C_R}{C_F}\left({V^{\prime }}_{\mathrm{OS}}{V}_{\mathrm{OS}}\right)$

[0235] In the above equation, V′.sub.OP(j) and V′.sub.ON(j) respectively represent a voltage of the first output terminal of the operational amplifier and a voltage of the second output terminal of the operational amplifier in the second phase of the (j)th cycle. D(j) is determined based on the output result of the comparator at the output end of the second phase of the (j−1)th cycle. V.sub.RP and V.sub.RN respectively present a positive signal and a negative signal of the reference voltage. V.sub.OS and V′.sub.OS respectively present an offset voltage of the analog-to-digital converter in the first phase and an offset voltage of the analog-to-digital converter in the second phase. V′.sub.OP(j−1) and V.sub.ON (j−1) respectively present a voltage of the first output terminal of the operational amplifier and a voltage of the second output terminal of the operational amplifier in the second phase of the (j−1)th cycle. Further, in a case of C.sub.I1=C.sub.I2=C.sub.I3=C.sub.I4=C.sub.F and V.sub.OS=V′.sub.OS, the above equation is transformed into:

V′.sub.OP(j)−V′.sub.ON(j)=2[V′.sub.OP(j−1)−V′.sub.ON(j−1)]+2*D(j)[V.sub.RP−V.sub.RN]

[0236] It can be seen from the above equation that in the second integral mode, the integrator amplifies the output voltage of the integrator in the operation cycle immediately before the current operation cycle. The integrator is configured to sample the reference voltage signal and output an integral signal. The integral signal outputted by the integrator is equal to a multiple of the sum of the integral signal outputted by the integrator in the operation cycle immediately before the current operation cycle and the first signal. The first signal is a product of the reference voltage signal and the first coefficient. The first coefficient is expressed as D(j).

[0237] Further, in a case that the integrator receives a positive reference voltage signal (V.sub.RP−V.sub.RN) in the first phase (in this case, the third input capacitor C.sub.I3 receives a positive signal V.sub.RP of the reference voltage and the fourth input capacitor C.sub.I4 receives the negative signal V.sub.RN of the reference voltage) and receives a negative reference voltage signal (V.sub.RN−V.sub.RP) in the second phase (in this case, the third input capacitor C.sub.I3 receives the negative signal V.sub.RN of the reference voltage and the fourth input capacitor C.sub.I4 receives the positive signal V.sub.RP of the reference voltage), the first coefficient D(j) is equal to 1.

[0238] In a case that the integrator receives the negative reference voltage signal (V.sub.RN−V.sub.RP) in the first phase (in this case, the third input capacitor C.sub.I3 receives the negative signal V.sub.RN of the reference voltage and the fourth input capacitor C.sub.I4 receives the positive signal V.sub.RP of the reference voltage) and receives the positive reference voltage signal (V.sub.RP−V.sub.RN) in the second phase (in this case, the third input capacitor C.sub.I3 receives the positive signal V.sub.RP of the reference voltage and the fourth input capacitor C.sub.I4 receives the negative signal V.sub.RN of the reference voltage), the first coefficient D(j) is equal to −1.

[0239] In a case that the integrator receives a zero reference signal in both the first phase and the second phase (in this case, the third input capacitor C.sub.I3 receives a common mode voltage signal V.sub.CM and the fourth input capacitor C.sub.I4 receives the common mode voltage signal V.sub.CM), the first coefficient D(j) is equal to 0.

[0240] Further, whether the integrator receives a positive reference voltage signal, a negative reference voltage signal or a zero reference signal in the first phase and the second phase of a current operation cycle is determined based on an output signal of the comparison circuit at an output end of the second phase of the operation cycle immediately before the current operation cycle, so as to determine the first coefficient D(j) based on the output signal of the comparison circuit at the output end of the second phase of the operation cycle immediately before the current operation cycle.

[0241] D(j) is determined based on the output signal of the comparison circuit at the output end of the second phase of the (j−1)th cycle by: determining D(j) to be 1 in a case that the output signal of the first comparator is at a low level and the output signal of the second comparator is at a high level; determining D(j) to be 0 in a case that the output signal of the first comparator is at a low level and the output signal of the second comparator is at a low level; and determining D(j) to be −1 in a case that the output signal of the first comparator is at a high level and the output signal of the second comparator is at a low level.

[0242] Further, the first comparator compares (V.sub.OP−V.sub.ON) with the first threshold +V.sub.TH to output a first comparison signal. The second comparator compares (V.sub.OP−V.sub.ON) with the second threshold −V.sub.TH to output a second comparison signal.

[0243] In a case that (V.sub.OP−V.sub.ON) is greater than +V.sub.TH, the first comparison signal is at a high level and the second comparison signal is at a low level.

[0244] In a case that (V.sub.OP−V.sub.ON) is greater than or equal to −V.sub.TH and is less than or equal to +V.sub.TH, the first comparison signal is at a low level and the second comparison signal is at a low level.

[0245] In a case that (V.sub.OP−V.sub.ON) is less than −V.sub.TH, the first comparison signal is at a low level and the second comparison signal is at a high level.

[0246] In an embodiment, in a case that the integrator 1 operates in the second integral mode, the integrator 1 alternately operates in two cases of the second integral mode, and the two cases are described in the above two embodiments. That is, in the operation cycle immediately before the current operation cycle, the integrator 1 operates as shown in FIG. 11 and FIG. 12. In the current cycle, the integrator 1 operates as shown in FIG. 13 and FIG. 14. In a cycle immediately after the current cycle, the integrator 1 operates as shown in FIG. 11 and FIG. 12, and so on. As described above, in the second integral mode shown in FIG. 11 to FIG. 14, the charges are redistributed by the integral capacitors and the input capacitors alternately.

[0247] Further, it can be seen from FIG. 5 to FIG. 14 that in the first phase and the second phase of each operation mode, the first offset capacitor C.sub.H1 and the second offset capacitor C.sub.H2 are connected in the same manner. For ease of illustration, the offset voltage is applied to the first input terminal of the operational amplifier, which is not limited in the present disclosure.

[0248] In the first phase:

V.sub.CM+V.sub.H1=V.sub.IP_OTA+V.sub.OS  (1)

V.sub.CM+V.sub.H2=V.sub.IN_OTA  (2)

[0249] In the above equations (1) and (2), V.sub.CN represents the common mode voltage signal. V.sub.H1 represents the voltage across the first offset capacitor C.sub.H1. V.sub.IP_OTA represents the voltage of the first input terminal of the operational amplifier in the first phase. V.sub.OS represents the offset voltage of the operational amplifier in the first phase. V.sub.H2 represents the voltage across the second offset capacitor C.sub.H2. V.sub.IN_OTA represents the voltage of the second input terminal of the operational amplifier in the first phase.

[0250] According to the virtual short feature of the operational amplifier, the following equation (3) is obtained:

V.sub.IP_OTA=V.sub.IN_OTA  (3)

[0251] According to the above equations (1) and (2), in the first phase, V.sub.H1−V.sub.H2=V.sub.OS (4).

[0252] Similarly, in the second phase:

V′.sub.AP+V.sub.H1=V′.sub.IP_OTA+V′.sub.OS  (5)

V′.sub.AN+V.sub.H2=V′.sub.IN_OTA  (6)

[0253] In the above equations (5) and (6), V.sub.H1 represents the voltage across the first offset capacitor C.sub.H1. V.sub.IP_OTA represents the voltage of the first input terminal of the operational amplifier in the second phase. V′.sub.OS represents the offset voltage of the operational amplifier in the second phase. V.sub.H2 represents the voltage across the second offset capacitor C.sub.H2. V.sub.IN_OTA represents the voltage of the second input terminal of the operational amplifier in the second phase. V′.sub.AP represents the voltage of the first terminal of the first offset capacitor V.sub.H1 in the second phase. V′.sub.AN represents the voltage of the first terminal of the second offset capacitor V.sub.H2 in the second phase. The second terminal of the first offset capacitor V.sub.H1 is coupled to the first input terminal of the operational amplifier. The second terminal of the second offset capacitor V.sub.H2 is coupled to the second input terminal of the operational amplifier.

[0254] According to the virtual short feature of the operational amplifier, the following equation (7) is obtained:

V′.sub.IP_OTA=V′.sub.IN_OTA  (7)

[0255] According to the above equations (5) and (6), in the second phase:

V′.sub.AP−V′.sub.AN+V.sub.H1−V.sub.H2=V′.sub.OS  (8)

[0256] The following equation is obtained by subtracting equation (4) from equation (8):

V′.sub.AP−V′.sub.AN=V′.sub.OS−V.sub.OS

[0257] Since V′.sub.OS is equal to V.sub.OS, V′.sub.AP is equal to V′.sub.AN. Therefore, a circuit formed by the operational amplifier OTA, the first offset capacitor V.sub.H1, the second offset capacitor V.sub.H2 and the offset voltage V.sub.OS is equivalent to an ideal operational amplifier. In the second phase, V′.sub.AP and V′.sub.AN are equivalent to the first input terminal and the second input terminal of the ideal operational amplifier.

[0258] That is, the first offset capacitor and the second offset capacitor store the offset voltage in the first phase, and the voltages of the first offset capacitor and the second offset capacitor counteract the offset voltage in the second phase to eliminate the offset voltage of the operational amplifier.

[0259] In the embodiment, the input capacitors and the integral capacitors are controlled to be connected to the operational amplifier by controlling the controllable switches to be switched on or switched off, so as to control the integrator to operate in different operation modes and control operation states of the first offset capacitor and the second offset capacitor in the first phase and the second phase of an operation cycle. Therefore, the offset voltage of the integrator can be eliminated, and the conversion efficiency and conversion accuracy of the analog-to-digital converter can be improved.

[0260] The above descriptions are merely preferred embodiments of the present disclosure and are not intended to limit the present disclosure, and those skilled in the art can make various modifications and variations to the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and the principle of the present disclosure are within the protection scope of the present disclosure.