Gain-control stage for a variable gain amplifier

Abstract

The invention relates to a gain-control stage (100) for generating gain-control signals (V.sub.c+, V.sub.c−) for controlling an external variable-gain amplifying unit (101). The gain-control stage comprises a first (102) and a second differential amplifier unit (112) that receive, at a respective input interface (104,114) a reference voltage signal (V.sub.Ref) and a variable gain-control voltage signal (V.sub.GC). The second differential amplifier unit is configured to provide, via a second output interface (120), a control voltage signal (V.sub.1) to a controllable first current source (106) of the first differential amplifier unit (102). The first differential amplifier unit (102) is configured to provide, via a first output interface (110), the first and the second gain-control signal (V.sub.C+, V.sub.C−) in dependence on the variable gain-control voltage signal (V.sub.GC), the reference voltage signal (V.sub.Ref) and a first biasing current (I.sub.B1) that depends on the control voltage signal.

Claims

1. A gain-control stage for generating a first gain-control signal (V.sub.c+) and a second gain-control signal (V.sub.c−) for controlling a gain value of an external variable-gain amplifying unit, the gain-control stage comprising: a first differential amplifier unit, comprising: a first input interface configured to receive a reference voltage signal (V.sub.Ref) and a variable gain-control voltage signal (V.sub.GC); a first amplifying stage comprising a controllable first current source, configured to provide a first biasing current (I.sub.B1) having a first biasing current amount that depends on a current voltage value of a control voltage signal (V.sub.1), the first amplifying stage being connected to a first polarization voltage supply line for providing a first polarization voltage (V.sub.cc) to a second polarization voltage supply line (GND) for providing, via the first current source, a second polarization voltage as a reference polarization voltage, and to the first input interface, the first amplifying stage being configured to provide, via a first output interface, the first and the second gain-control signals (V.sub.c+, V.sub.c−) in dependence on the variable gain-control voltage signal, the reference voltage signal and the first biasing current (I.sub.B1); and a second differential amplifier unit for providing the current voltage value of the control voltage signal, comprising: a second input interface configured to receive the reference voltage signal (V.sub.Ref) and the variable gain-control voltage signal (V.sub.GC); a second amplifying stage comprising a second current source, configured to provide a second biasing current (I.sub.B2) having a second biasing current amount, the second amplifying stage connected to the first polarization voltage supply line via an active load unit, to the second polarization voltage supply line via the second current source, and to the second input interface, the second amplifying stage being configured to provide, via a second output interface, the current voltage value of the control voltage signal (V.sub.1) to the controllable first current source of the first differential amplifier unit, wherein the second amplifying stage of the second differential amplifier unit comprises a second long-tailed pair circuit with a current mirror load as the active load unit.

2. The gain-control stage of claim 1, wherein the controllable first current source, or the second current source or both the first and the second current source comprises a respective first and second current unit configured to receive a respective reference current (I.sub.Ref1, I.sub.Ref2) and to provide the respective first biasing current (I.sub.B1) or second biasing current (I.sub.B2) in dependence on the respective reference current.

3. The gain-control stage of claim 2, wherein the first current unit and/or the second current unit is current mirror source or a Wilson current source.

4. The gain-control stage of claim 3, wherein the first amplifying stage of the first differential amplifier unit comprises a first long-tailed pair circuit.

5. The gain-control stage of claim 4, further comprising a bandgap-voltage reference unit connected to the first and the second polarization voltage supply lines and configured to generate and provide the reference voltage signal (V.sub.Ref) to the first input interface and to the second input interface.

6. A variable gain amplifier, comprising: a gain-control stage in accordance with claim 1 for providing the first and the second gain-control signals; a gain-control signal input for receiving the first gain-control signal (V.sub.c+) and the second gain-control signal (V.sub.c−); a variable-gain-amplifier signal input for receiving a first input signal (In+) and a second input signal (In−); a variable-gain amplifying unit configured: to receive the first and the second gain-control signals from the gain-control signal input; to receive the first and the second input signals from the variable-gain-amplifier signal input; to amplify a difference of the first and the second input signals in accordance with a current value of the first and the second gain-control signals, thus generating a first output signal (Out+) and a second output signal (Out−) with an amplified output signal difference; and a variable-gain-amplifier signal output for providing the first and the second output signals.

7. The variable gain amplifier of claim 6, wherein the variable-gain amplifying unit comprises: two cascode stages connected to the first and the second polarization voltage supply lines, each cascode stage comprising: a first transistor (Q3) connected to the variable-gain-amplifier signal output, and to the gain control signal input for receiving the first gain-control signal (V.sub.c+); a second transistor (Q1) connected to the first transistor (Q3) and to the variable-gain-amplifier signal input for receiving a respective one of the first input signal (In+) and the second input signal; a third transistor (Q5) and a fourth transistor (Q6), both connected to the variable-gain-amplifier signal input for receiving the second gain-control signal (V.sub.c−), to the first polarization voltage supply line, and to the first transistor (Q3) and the second transistor (Q1) of each of the two cascode stages.

8. The variable gain amplifier of claim 7, wherein the first transistors (Q3, Q4), the second transistors (Q1, Q2), the third transistor (Q5) and the fourth transistor (Q6) are bipolar transistors.

9. The gain-control stage of claim 1, wherein the first amplifying stage of the first differential amplifier unit comprises a first long-tailed pair circuit.

10. The gain-control stage of claim 2, wherein the first amplifying stage of the first differential amplifier unit comprises a first long-tailed pair circuit.

11. The gain-control stage of the claim 4, wherein the first long-tailed pair circuit or the first long-tailed pair circuit and the second long-tailed pair circuit with the current mirror load comprise field effect transistors (P1, P2).

12. The gain-control stage of claim 1, further comprising a bandgap-voltage reference unit connected to the first and the second polarization voltage supply lines and configured to generate and provide the reference voltage signal (V.sub.Ref) to the first input interface and to the second input interface.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

(2) FIG. 1 shows a schematic block diagram of an embodiment of a variable gain amplifier having a gain control-stage.

(3) FIG. 2 shows an electrical circuit representing an embodiment of a gain-control stage.

(4) FIG. 3 shows an electrical circuit representing an embodiment of a variable-gain amplifying unit with a gain-control signal input, a variable-gain-amplifier signal input and a variable-gain-amplifier signal output.

DETAILED DESCRIPTION

(5) FIG. 1 shows a schematic block diagram of an embodiment of a variable gain amplifier 105 having a gain-control stage 100 that is configured to control a gain value of a variable-gain amplifying unit 101. The gain-control stage comprises a first and a second differential amplifier unit, 102 and 112 respectively. The first differential amplifier unit 102 includes a first input interface 104, which is configured to receive a reference voltage signal V.sub.Ref and a variable gain-control voltage signal V.sub.GC. The first differential amplifier unit 102 also includes a first amplifying stage 108 that comprises a controllable first current source 106. The first current source 106 is configured to provide a first biasing current I.sub.B1 having a first biasing current amount that depends on a current voltage value of a control voltage signal V.sub.1, which is generated and provided by the second differential amplifier unit 112. The first amplifying stage 108 is connected to a first polarisation voltage supply line that provides a first polarisation voltage V.sub.CC. The first amplifying stage is also connected to a second polarisation voltage supply line GND for providing, via the first current source 116, a second polarisation voltage as a reference polarisation voltage. The first amplifying stage 108 is configured to receive, from the first input interface, the reference voltage signal V.sub.ref and the variable gain-control voltage signal V.sub.GC and to provide, via a first output interface 110, a first and a second gain-control signal, V.sub.C+, V.sub.C−, in dependence on the current values of the variable gain-control voltage signal V.sub.GC and the reference voltage signal V.sub.ref.

(6) The gain-control stage 100 also comprises the second differential amplifier unit 112, which is configured to provide the current voltage value of the control voltage signal V.sub.1, to the first differential amplifier unit 102 for controlling the first biasing current amount I.sub.B1. The second differential amplifier unit 112 comprises a second input interface 114 that is configured to receive the reference voltage signal V.sub.Ref and the control gain voltage signal V.sub.GC. It also comprises a second amplifying stage 118 that includes a second current source 116, configured to provide a second biasing current I.sub.B2 having a second biasing current amount. The second amplifying stage 118, as in the case of the first amplifying stage is connected to the first polarisation voltage supply line V.sub.CC, to the second polarisation voltage supply line GND via the second current source 116, and to the second input interface, 114. The second amplifying stage 118 is configured to provide, via a second output interface 120, the current voltage value of the control voltage signal V.sub.1 to the controllable first current source 106 of the first differential amplifier unit 102.

(7) The second amplifying stage is connected to the first polarisation voltage supply line via an active-load unit. The active-load unit is an electrical unit acting as a circuit component that comprise active devices, and that acts as a current-stable non-linear resistor. The gain-control stage 100 may optionally comprise a bandgap-voltage reference unit 160 that is connected to the first and the second polarisation voltage supply lines and configured to generate and provide the reference voltage signal V.sub.Ref to the first input interface 104 and to the second input interface 114. The reference voltage signal provided by the bandgap-voltage reference unit has a constant value regardless of power supply variations (up to a predetermined maximum allowable deviation), temperature changes and circuit loading.

(8) FIG. 2 shows an electrical circuit representing an exemplary gain-control stage 200 for generating and providing the first and the second gain-control signals, V.sub.C+ and V.sub.C−, for controlling the gain value of a variable-gain amplifying unit (not shown). The gain-control stage includes the first differential amplifier unit 202 and the second differential amplifier unit 212 that is configured to provide the current voltage value of the control voltage signal V.sub.1 to the first differential amplifier unit 202. The first and the second differential amplifier unit 202 and 212 comprise a respective input interface for receiving the reference voltage signal Vef and the variable gain-control voltage signal V.sub.GC.

(9) The first current source of the first amplifier unit 202 comprises a first current unit 222 that is configured to receive a reference current IRef1 and to provide the first biasing current I.sub.B1 in dependence thereof. Respectively, the second current source of the second amplifier unit 212 comprises a second current unit 224 that is also configured to receive a reference current IRef2 and to provide the second biasing current I.sub.B2 in dependence thereof. Exemplarily, the first and the second current units 222, 224 of the gain-control stage 200 are implemented as a current mirror source. Other gain-control stages comprise other types of suitable current unit such as, but not limited to, Wilson current sources. In another gain-control stage, the first and the second differential amplifier unit comprise different types of suitable current units. In the case of having perfectly matched transistors, the value of I.sub.B1 and I.sub.B2 mirror, i.e. matches, the value of the respective reference currents I.sub.Ref1 and I.sub.Ref2.

(10) The first amplifying stage of the first differential amplifier unit 202 comprises a first long-tailed pair circuit 226. In general, a long tailed pair, also referred to as LTP or differential pair, operates as a differential amplifier configured to amplify a difference in voltage value of a pair of input signals V.sub.Ref and V.sub.GC. A ratio of the resistance value of resistors R4 and R3 defines a gain value of the first differential amplifier unit 202. Additionally, the second amplifying stage of the second differential amplifier unit 212 comprises a second long-tailed pair circuit 228 with a current mirror load 230. As in the case of the first long tailed pair, the second long-tailed pair is also configured to amplify a difference in voltage value of a pair of input signals V.sub.Ref and V.sub.GC. A ratio of the resistance value of resistors R6 and R5 defines a gain value of the second differential amplifier unit 212. The transistors P1 and P2 form the current mirror load. In the gain-control stage 200, the PMOS transistors P1, P2 are P3 are ideally matched and have the same dimensions. When the input signals V.sub.Ref and V.sub.GC are equal, the value of the current flowing through P3, i.e., I.sub.Ref1, is equal to the current flowing through the diode-connected PMOS transistor P1. Thus, transistor P1 acts as a reference for P3. In another gain-control stage, the PMOS transistor P3 has scaled dimensions compared to those of P1 and P2, which are still matched. In this case, the value of the current I.sub.Ref1 is proportional to that of the current flowing through P1, with a proportionality factor depending on a width and length extension value of the respective transistors P1 and P3.

(11) When the input signals V.sub.Ref and V.sub.GC differ, the value of the current I.sub.Ref1 will decrease or increase accordingly, which in turn changes the value of the first biasing current I.sub.B1 of the first differential amplifier unit. In this way, when the value of V.sub.GC changes, the amount of current flowing through load resistors R4 also changes thus changing the value of the first and the second gain control signals, V.sub.C+ and V.sub.C−.

(12) As V.sub.CC is the same supply voltage used for the first and the second differential amplifier units 102, 112, any fluctuation in the supply is directly affecting both the PMOS FETs in the first and second differential stages. This means that PMOS P1, P2 and P3 have their respective sources coupled to the same potential V.sub.CC and the reference V.sub.1 is therefore usable even when V.sub.CC fluctuates. Preferably, the PMOS transistors have identical dimensions and are properly matched. Alternatively, NMOS transistors N1, N2 and N3 are used instead of the PMOS transistors P1, P2 and P3, in an exemplary gain-control stage (not shown). In this particular gain-control stage with NMOS transistors, they are all configured as current sources coupled to the ground. In general, the sources of the FETs P1, P2 and P3 must be referred to the same potential and have the same topology. In the case including NMOS transistors N1, N2 and N3, all other transistors are of the opposite topology as in FIG. 2, so for instance the transistors amplifying the signals V.sub.Ref and V.sub.GC in the differential pairs are PMOS transistors.

(13) FIG. 3 shows an electrical circuit representing a variable-gain amplifying unit 336 with a gain-control signal input 332, a variable-gain-amplifier signal input 334 and a variable-gain-amplifier signal output 338. The variable-gain amplifying unit 336 is configured to receive the first and the second gain control signals V.sub.C+ and V.sub.C− from a gain-control stage (not shown) via the gain-control signal input 332. It is also configured to receive a first input signal In+ and a second input signal In− via the variable-gain-amplifier signal input 334. The variable-gain amplifying unit 336 is configured to amplify a difference of the input signals in accordance with a current value of the first and the second gain-control signal, thus generating a first output signal Out+ and a second output signal Out− with an amplified output signal difference. The variable-gain-amplifying unit also comprises a variable-gain-amplifier signal output 338 for providing the first and the second output signal.

(14) In particular, the exemplary variable-gain amplifying unit 336 comprises two cascode stages, such as cascode stage 340, connected to the first and the second polarisation voltage supply lines, V.sub.CC and GND. For the sake of clarity, the following explanation will refer to one of the two cascode stages. The second cascode stage includes the same number and type of active and passive devices. References to those devices and input or output signals of the second cascode stage that correspond to the devices referred to in the description of the first cascode stage 340 will be included in brackets.

(15) The first cascode stage 340 comprises a first transistor Q3 (Q4) connected to the variable-gain-amplifier signal output 338 and to the gain control signal input 332 for receiving the first gain-control signal V.sub.c+. It also comprises a second transistor Q1 (Q2) that is connected to the first transistor Q3 (Q4) and to the variable-gain-amplifier signal input 334 for receiving the first input signal In+(In−). The first transistor Q3 (Q4) is connected to the first polarisation voltage supply line via a resistor R2. The second transistor is connected to the second polarisation voltage supply line GND via a resistor R1 and a current source.

(16) The variable-gain amplifying unit 336 also comprises a third transistor Q5 and a fourth transistor Q6, both connected to the variable-gain-amplifier signal input 332 for receiving the second gain-control signal Vc−, to the first polarisation voltage supply line, and to the first transistor Q3, Q4 and the second transistor Q1, Q2 of each of the two cascode stages.

(17) The variable-gain amplifying unit 336 follows a topology commonly referred to as current-steering-based variable gain amplifier (VGA), which is based on a two-quadrant multiplier. It is based on cascode stages comprising a common-emitter amplifier that includes transistors Q1, Q2 and a common-base amplifier that includes transistors Q3, Q4. Resistors R.sub.1 are so-called degeneration resistors and are connected to the emitter of Q1 and Q2. The resistors R.sub.2 are collector resistors. In a cascode amplifier, the gain is approximated by the ratio R.sub.2/R.sub.1. Further, the product R.sub.2×I.sub.C determines the potential difference that falls in the resistor R.sub.2 and which defines the output common mode voltage V.sub.CC−(R.sub.2×I.sub.C). In addition to the standard cascode amplifier, transistors Q5 and Q6 are added, which turns the stage into a variable gain amplifier. Controlling the first and the second gain-control signals causes a variable amount of current through the transistors Q5 and Q6. This causes a change in the collector currents I.sub.C, which modifies the gain of the VGA. In particular, when I.sub.C decreases, the gain decreases with minimal impact in other characteristics of the VGA such as for instance its bandwidth.

(18) Based on the exemplary electrical circuits shown in FIGS. 2 and 3, the first and the second gain-control signals V.sub.C+ and V.sub.C− affect the gain of the variable-gain amplifying unit in the following ways:

(19) When V.sub.GC is lower than V.sub.Ref, i.e. when the variable gain amplifier is in a low gain mode, the voltage value of the control voltage signal V.sub.1 is higher than when V.sub.GC is equal to V.sub.Ref. This is based on the fact that the transistor P3 is a PMOS transistor, so a lower gate-to-source voltage V.sub.GS causes a lower drain-source current I.sub.DS, which is referred to as I.sub.Ref1 in FIG. 2. Thus, the current amount I.sub.Ref1 decreases. Also, a common mode of the first and second gain-control signals increases. The increase in this common mode compensates how much the collector-emitter voltage V.sub.CE of the transistors Q3 and Q4 increases thus ensuring that a breakdown voltage value is not exceeded.

(20) In turn, when V.sub.GC is higher than V.sub.Ref, i.e. when the variable gain amplifier is in a high gain mode, the voltage value of the control voltage signal is lower than when V.sub.GC is equal to V.sub.Ref. Thus, the current amount I.sub.Ref1 increases. Also, the common mode of the first and second gain-control signals decreases. The decrease of in this common mode compensates how much the saturation collector-emitter voltage V.sub.CE of the transistors Q3 and Q4 decreases thus ensuring that a saturation collector-emitter voltage value V.sub.CE,sat is not reached.

(21) The gain-control Signals provided by the claimed gain-control stage are differential Signals (Vc+ and Ve−). As known in the literature, differentials Signals are more immune to ground noise and supply fluctuations, as the information is carried by the difference between the Signals without any dependency to the supply or ground. Therefore, the conversion of the control signal VGC to a differential signal is inherent in the invention from the very beginning in all the stages presented. Moreover, the first differential pair as it is based on an NMOS amplifier, the common mode of the Output differential Signals Vc+ and Ve− is dependent on the supply Vcc. This means, if there are Vcc fluctuations, they tend to influence equally the Output common-mode voltages of the VGA and the first differential pair, so in the VGA the controlled difference between collector and base voltages of the transistors Q3 to Q6 remain the same. This means, any fluctuation in the supply will not affect the purpose of this invention, which is to provide a control Signal to the VGA that will not force the bipolar transistors to be out of the proper operating range.

(22) Thus, the variable gain amplifier 150 comprising the gain-control stage 100 or 200 and the variable-gain amplifying unit 336 is suitable for solving an essential drawback of steering-current-based variable gain amplifiers. The first and the second gain-control signals keep the bipolar transistors of the variable-gain amplifying unit 336 in a linear region, avoiding that VCE exceeds the breakdown voltage amount or reaches saturation collector-emitter voltage value V.sub.CE,sat. Additionally, the variable gain amplifier 150 provides compensation against supply voltage fluctuations. The feedforward architecture further opens the possibility to be used in any multi-stage transimpedance amplifier with input overload-current compensation or DC-offset cancellation loop or both.

(23) In summary, the invention relates to a gain-control stage for generating gain-control signals for controlling an external variable-gain amplifying unit. The gain-control stage comprises a first and a second differential amplifier unit, that receive, at a respective input interface, a reference voltage signal and a variable gain-control voltage signal. The second differential amplifier unit is configured to provide, via a second output interface, a control voltage signal to a controllable first current source of the first differential amplifier unit. The first differential amplifier unit is configured to provide, via a first output interface, the first and the second gain-control signal in dependence on the variable gain-control voltage signal, the reference voltage signal and a first biasing current that depends on the control voltage signal.

(24) Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.

(25) In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality.

(26) A single unit or device may fulfil the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

(27) Any reference signs in the claims should not be construed as limiting the scope.