POWER CONVERTER
20230299692 · 2023-09-21
Assignee
Inventors
Cpc classification
H02M7/4835
ELECTRICITY
Y02B70/10
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
International classification
H02M1/12
ELECTRICITY
Abstract
A power converter includes an inverter circuit connected to positive and negative terminals of a direct current power supply, three H-bridge circuits, and a power conversion controller. The conversion controller calculates a first three-phase common voltage common to three phases; generates second phase voltage commands obtained by superimposing the calculated first three-phase common voltage on first phase voltage commands; calculates a second three-phase common voltage; generates third phase voltage commands obtained by superimposing the calculated second three-phase common voltage on the second phase voltage commands; and generates gate signals to first legs based on polarity of the third phase voltage commands and generates gate signals to second legs according to the third phase voltage commands. When a three-phase sum of the three-phase pulse voltage commands is non-zero, the conversion controller calculates the second three-phase common voltage so that the polarity of the third phase voltage commands is not switched.
Claims
1. A power converter that converts direct current power outputted from a direct current power supply into alternating current power to a load, and supplies the alternating current power to the load, the power converter comprising: a three-phase inverter circuit connected to positive and negative terminals of the direct current power supply; three single-phase bridge circuits each including: a first leg in which two semiconductor switching elements are connected in series, and a midpoint that is a connecting end of the two semiconductor switching elements is connected to an alternating current end of a corresponding phase among different alternating current ends of the three-phase inverter circuit; a second leg connected in parallel to the first leg, in which two semiconductor switching elements are connected in series, and a midpoint that is a connecting end of the two semiconductor switching elements is connected to a terminal of a corresponding phase among different terminals of the load; and a capacitor connected to both ends of each of the first and second legs; and a controller to generate first gate signals for controlling an operation of the three-phase inverter circuit on the basis of sinusoidal phase voltage commands and second gate signals for controlling operations of the first and second legs in the three single-phase bridge circuits, wherein the controller divides the sinusoidal phase voltage commands into three-phase pulse voltage commands to be issued to the three-phase inverter circuit and first phase voltage commands that are voltage commands to be issued to the three single-phase bridge circuits, respectively; generates the first gate signals on the basis of the three-phase pulse voltage commands; calculates a first three-phase common voltage common to three phases, and generates second phase voltage commands obtained by superimposing the first three-phase common voltage calculated on the first phase voltage commands; further calculates a second three-phase common voltage common to the three phases, and generates third phase voltage commands obtained by superimposing the second three-phase common voltage calculated on the second phase voltage commands; generates the second gate signals to be applied to one of the first and second legs on the basis of positive/negative polarity of the third phase voltage commands, and concurrently generates the second gate signals to be applied to another one of the first and second legs in accordance with the third phase voltage commands; and calculates the second three-phase common voltage so that the positive/negative polarity of the third phase voltage commands is not switched during a period in which a three-phase sum of the three-phase pulse voltage commands is not zero.
2. The power converter according to claim 1, wherein the controller calculates the second three-phase common voltage so that the positive/negative polarity of the third phase voltage commands does not change from that of the first phase voltage commands.
3. The power converter according to claim 1, wherein a capacitor voltage that is a voltage across the capacitor is a quarter or less of a voltage of the direct current power supply.
4. The power converter according to claim 3, wherein the controller calculates the first three-phase common voltage so that an absolute value of a voltage value for each phase of the second phase voltage commands does not exceed the capacitor voltage.
5. The power converter according to claim 1, wherein when a modulation factor is defined as a value obtained by dividing an amplitude of the sinusoidal phase voltage command by a half of the voltage of the direct current power supply, in a case where the modulation factor is 0.61 or more and 0.79 or less, where the modulation factor is 0.90 or more and 0.99 or less, or where the modulation factor is 1.23 or more, the controller calculates the second three-phase common voltage so that a maximum value of the second phase voltage commands is zero or negative when a three-phase sum of the three-phase pulse voltage commands is positive; and calculates the second three-phase common voltage so that a minimum value of the second phase voltage commands is zero or positive when the three-phase sum of the three-phase pulse voltage commands is negative.
6. The power converter according to claim 1, wherein when the modulation factor is defined as a value obtained by dividing an amplitude of the sinusoidal phase voltage command by a half of the voltage of the direct current power supply, in a case where the modulation factor is 0.90 or more and 0.99 or less, the controller calculates the second three-phase common voltage so that the maximum value of the second phase voltage commands is zero or positive when the three-phase sum of the three-phase pulse voltage commands is positive; and calculates the second three-phase common voltage so that the minimum value of the second phase voltage commands is zero or negative when the three-phase sum of the three-phase pulse voltage commands is negative.
7. The power converter according to claim 1, wherein the controller generates, as the first three-phase common voltage, a value obtained by inverting polarity of an average value of a maximum value and a minimum value of the first phase voltage commands.
8. The power converter according to claim 1, wherein when a modulation factor is defined as a value obtained by dividing an amplitude of the sinusoidal phase voltage command by a half of the voltage of the direct current power supply, in a case where the modulation factor is 0.67 or more and 0.97 or less, or where the modulation factor is 1.11 or more, the controller calculates the second three-phase common voltage so that a maximum value of the second phase voltage commands is zero or negative when a three-phase sum of the three-phase pulse voltage commands is positive; and calculates the second three-phase common voltage so that a minimum value of the second phase voltage commands is zero or positive when the three-phase sum of the three-phase pulse voltage commands is negative.
9. The power converter according to claim 1, wherein when the modulation factor is defined as a value obtained by dividing an amplitude of the sinusoidal phase voltage command by a half of the voltage of the direct current power supply, in a case where the modulation factor is 0.86 or more and 0.97 or less, the controller calculates the second three-phase common voltage so that a middle value of the second phase voltage commands is zero or negative when the three-phase sum of the three-phase pulse voltage commands is positive; and calculates the second three-phase common voltage so that the middle value of the second phase voltage commands is zero or positive when the three-phase sum of the three-phase pulse voltage commands is negative.
10. The power converter according to claim 1, wherein the three-phase inverter circuit is configured to use a semiconductor switching element formed of a narrow bandgap semiconductor, and the single-phase bridge circuit is configured to use a semiconductor switching element formed of a wide bandgap semiconductor.
11. The power converter according to claim 1, wherein of the first and second legs constituting the single-phase bridge circuit, the leg to be controlled by the second gate signal generated on the basis of the positive/negative polarity of the third phase voltage command is configured to use a semiconductor switching element formed of a narrow bandgap semiconductor.
12. The power converter according to claim 1, wherein the number of times the positive/negative polarity is switched by the third phase voltage commands is ten times or less in a fundamental wave period of the sinusoidal phase voltage commands.
Description
BRIEF DESCRIPTION OF DRAWINGS
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DESCRIPTION OF EMBODIMENTS
[0053] Hereinafter, a power converter according to embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
First Embodiment
[0054]
[0055] The H-bridge circuits 5, 6, and 7 each include a first leg in which two semiconductor switching elements having a reverse conducting function are connected to each other in series, and a corresponding midpoint 5a1, 6a1, or 7a1 that is a connecting end of the two semiconductor switching elements is connected to a corresponding one of the alternating current ends 4a, 4b, and 4c of the three-phase inverter circuit, that is, an alternating current end for a corresponding phase among the different alternating current ends. Moreover, the H-bridge circuits 5, 6, and 7 each include a second leg in which. two semiconductor switching elements having a reverse conducting function. are connected to each other in series, and a corresponding midpoint 5a2, 6a2, or 7a2 that is a connecting end of the two semiconductor switching elements is connected to a terminal for a corresponding phase of the motor 2, that is, a terminal for a corresponding phase among different terminals of the motor 2. Furthermore, the H-bridge circuits 5, 6, and 7 each include a capacitor Cs connected to both ends of each of the first and second legs.
[0056]
[0057] Also, in a typical configuration, an IGBT made of silicon (Si), which is a narrow bandgap semiconductor element, is used for each semiconductor switching element of the inverter circuit 4. An IGBT made of Si is also used for each semiconductor switching element of the first leg in each of the H-bridge circuits 5, 6, and 7, that is, the leg whose midpoint is connected to the inverter circuit 4. On the other hand, a MOSFET made of, for example, silicon carbide (SiC), which is a wide band gap semiconductor element, is used for each semiconductor switching element of the second. leg in each of the H-bridge circuits 5, 6, and 7, that is, the leg whose midpoint is connected to the motor 2. While SiC has a feature of being able to form a semiconductor element having smaller on-voltage and switching loss as compared with Si, SiC has another feature in which an element made of SiC is difficult to obtain and more expensive as compared. with an element made of Si. For this reason, using the IGBT made of Si for the first leg and using the MOSFET made of SiC for the second leg can achieve the problems on both the manufacturing cost and the difficulty of obtaining the element. Note that considering the symmetry of the H-bridge circuits 5, 6, and 7, functionally, there is no problem even when usage relation is changed between the first leg and the second leg. Thus, it is also possible to use the MOSFET made of SiC for the first leg and the IGBT made of Si for the second leg.
[0058] A torque command T* is inputted to a motor controller 8. The motor controller 8 calculates sinusoidal phase voltage commands v.sub.su*, v.sub.sv*, and v.sub.sw* such that the motor 2 generates a desired torque based on the torque command T*, and outputs the sinusoidal phase voltage commands v.sub.su*, v.sub.sv*, and v.sub.sw* to the power conversion controller 9A. The power conversion controller 9A generates gate signals g.sub.mu1 to g.sub.mu4, g.sub.mv1 to g.sub.mv4, and g.sub.mw1 to g.sub.mw4 as first gate signals, and gate signals g.sub.su1 to g.sub.su4, g.sub.sv1 to g.sub.sv4, and g.sub.sw1 to g.sub.sw4 as second gate signals so that voltages based on the sinusoidal phase voltage commands v.sub.su*, v.sub.sv*, and v.sub.sw* are applied to the motor 2.
[0059] The gate signals g.sub.mu1 to g.sub.mu4, g.sub.mv1 to g.sub.mv4, and g.sub.mw1 to g.sub.mw4 are signals for controlling the operation or the inverter circuit 4, that is, gate signals for performing switching control on the semiconductor switching elements of the inverter circuit 4. More specific description is as follows.
[0060] The gate signal g.sub.mu1 is a signal applied to a gate of a first semiconductor switching element of a first phase (for example, a u-phase), the gate signal g.sub.mu2 is a signal applied to a gate of a second semiconductor switching element of the first phase, the gate signal g.sub.mu3 is a signal applied to a gate of a third semiconductor switching element of the first phase, and the gate signal g.sub.mu4 is a signal applied to a gate of a fourth semiconductor switching element of the first phase.
[0061] The gate signal g.sub.mv1 is a signal applied to a gate of a first semiconductor switching element of a second phase (for example, a v-phase), the gate signal g.sub.mv2 is a signal applied to a gate of a second semiconductor switching element of the second phase, the gate signal g.sub.mv3 is a signal applied to a gate of a third semiconductor switching element of the second phase, and the gate signal g.sub.mv4 is a signal applied to a gate of a fourth semiconductor switching element of the second phase.
[0062] The gate signal g.sub.mw1 is a signal applied to a gate of a first semiconductor switching element of a third phase (for example, a w-phase), the gate signal g.sub.mw2 is a signal applied to a gate of a second semiconductor switching element of the third phase, the gate signal g.sub.mw3 is a signal applied to a gate of a third semiconductor switching element of the third phase, and the gate signal g.sub.mw4 is a signal applied to a gate of a fourth semiconductor switching element of the third phase.
[0063] Next, the gate signals g.sub.su1 to g.sub.su4, g.sub.sv1 to g.sub.sv4, and g.sub.sw1 to g.sub.sw4 to will be described.
[0064] The gate signals g.sub.su1 to g.sub.su4 are signals for controlling the operation of the H-bridge circuit 5, that is, gate signals for performing switching control on the semiconductor switching elements of the H-bridge circuit 5. Specifically, the gate signal g.sub.su1 is a signal applied to a gate of a first semiconductor switching element placed on a high electric potential side of the second leg, the gate signal g.sub.su2 is a signal applied to a gate of a second semiconductor switching element on a low electric potential side of the first leg, the gate signal g.sub.su3 is a signal applied to a gate of a third semiconductor switching element on a low electric potential side of the second leg, and the gate signal g.sub.su4 is a signal applied to a gate of a fourth semiconductor switching element on a high electric potential side of the first leg.
[0065] The gate signals g.sub.sv1 to g.sub.sv4 are signals for controlling the operation of the H-bridge circuit 6, that is, gate signals for performing switching control on the semiconductor switching elements of the H-bridge circuit 6. Specifically, the gate signal g.sub.sv1 is a signal applied to a gate of a first semiconductor switching element placed on a high electric potential side of the second leg, the gate signal g.sub.sv2 is a signal applied to a gate of a second semiconductor switching element on a low electric potential side of the first leg, the gate signal g.sub.sv3 is a signal applied to a gate of a third semiconductor switching element on a low electric potential side of the second leg, and the gate signal g.sub.sv4 is a signal applied to a gate of a fourth semiconductor switching element on a high electric potential side of the first leg.
[0066] The gate signals g.sub.sw1 to g.sub.sw4 are signals for controlling the operation of the H-bridge circuit 7, that is, gate signals for performing switching control on the semiconductor switching elements of the H-bridge circuit 7. Specifically, the gate signal g.sub.sw1 is a signal applied to a gate of a first semiconductor switching element placed on a high electric potential side of the second leg, the gate signal g.sub.sw2 is a signal applied to a gate of a second semiconductor switching element on a low electric potential side of the first leg, the gate signal g.sub.sw3 is a signal applied to a gate of a third semiconductor switching element on a low electric potential side of the second leg, and the gate signal g.sub.sw4 is a signal applied to a gate of a fourth semiconductor switching element on a high electric potential side of the first leg.
[0067] In the configuration of
[0068] In the configuration of
[0069]
[0070] The three-phase pulse voltage command calculator 901 calculates three-phase pulse voltage commands v.sub.smu*, v.sub.smv*, and v.sub.smv* to be issued to the inverter circuit 4.
[0071] The voltage waveform illustrated in
[0072] In
[0073] As illustrated in
[0074] Specifically, in the example of
[0075] Here, in order to equalize the fundamental wave components of both the sinusoidal phase voltage command v.sub.s* and the three-phase pulse voltage command v.sub.sm*, the aforementioned phase angle α is determined by the following expression (1) with v*.sub.sphp as the amplitude of the sinusoidal phase voltage command v.sub.s*.
α=cos.sup.−1(v*.sub.sphp.Math.π/(2v.sub.dc)) (1)
[0076] When the above expression (1) is satisfied, the inverter circuit 4 outputs the voltage of the fundamental wave component and shares all the electric power of the fundamental wave component supplied to the motor 2. Therefore, when the above expression (1) is satisfied, no direct current power supply is required on the direct current side of the H-bridge circuits 5, 6, and 7, whereby the power converter 1 can be reduced in size and cost. At this time, since the H-bridge circuits 5, 6, and 7 do not bear active power, the capacitor voltage v.sub.ca is maintained at about a quarter of the direct current voltage v.sub.dc that is the specified value.
[0077] Returning to the description for
[0078] Table 1 below illustrates a relationship between an output voltage v.sub.sm outputted by the inverter circuit 4 and the gate signals g.sub.m1 to g.sub.m4 to the inverter circuit 4. The three-phase pulse voltage command calculator 901 generates the gate signals to the inverter circuit 4 using the relationship of Table 1.
TABLE-US-00001 TABLE 1 OUTPUT VOLTAGE V.sub.sm −V.sub.dc/2 0 V.sub.dc/2 g.sub.m1 L L H g.sub.m2 L H H g.sub.m3 H H L g.sub.m4 H L L
[0079] In Table 1 above, “H” represents “high” and means a gate signal for controlling a corresponding semiconductor switching element to be on. Also, “L” represents “low” and means a gate signal for controlling a corresponding semiconductor switching element to be off.
[0080] In the subtractor 908, the three-phase pulse voltage commands v.sub.smu*, v.sub.smv*, and v.sub.smw* to be issued to the inverter circuit 4 are subtracted from the sinusoidal phase voltage commands v.sub.su*, v.sub.sv*, and v.sub.sw*, and first phase voltage commands v.sub.ssu1*, v.sub.ssv1*, ad v.sub.ssw1*, which are voltage commands to be issued to the H-bridge circuits 5, 6, and 7, are generated. That is, the three-phase pulse voltage command calculator 901 and the subtractor 908 divide the sinusoidal phase voltage commands v.sub.su*, v.sub.sv*, and v.sub.sw* into: the three-phase pulse voltage commands v.sub.smu*, v.sub.smv*, and v.sub.smw*; and the first phase voltage commands v.sub.ssu1*, v.sub.ssv1*, and v.sub.ssw1*. The first phase voltage commands v.sub.ssu1*, v.sub.ssv1*, and v.sub.ssw1* are calculated by the subtractor 908 so as to cancel changes in the output voltage outputted by the inverter circuit 4. With this processing, the power converter 1 can supply. electric power to the load while reducing noise and harmonics.
[0081] The first common voltage superimposer 903A calculates a first three-phase common voltage common to the three phases on the basis of the three-phase pulse voltage commands v.sub.smu*, v.sub.smv*, and v.sub.smw*. The first common voltage superimposer 903A superimposes the calculated first three-phase common voltage on the first phase voltage commands v.sub.ssu1*, v.sub.ssv1*, and v.sub.ssw1*, and outputs voltages obtained by the superimposing process to the second common voltage superimposer 904A as second phase voltage commands v.sub.ssu2*, v.sub.ssv2*, and v.sub.ssw2*. The capacitor voltage v.sub.cs is used for generating the second phase voltage commands v.sub.ssu2*, v.sub.ssv2*, and v.sub.ssw2* The first three-phase common voltage is calculated so that peak values of the second phase voltage commands v.sub.ssu2*, v.sub.ssv2*, and v.sub.ssw2* are reduced.
[0082] The second common voltage superimposer 904A calculates a second three-phase common voltage common to the three phases on the basis of the three-phase pulse voltage commands v.sub.smu*, v.sub.smv*, and v.sub.smv*. The second common voltage superimposer 904A superimposes the calculated second three-phase common voltage on the second phase voltage commands v.sub.ssu2*, v.sub.ssv2*, and v.sub.ssw2*, and outputs voltages obtained by the superimposing process to the voltage polarity controller 905 as third phase voltage commands v.sub.ssu3*, v.sub.ssv3*, and v.sub.ssw3*.
[0083] The operations of the first common voltage superimposer 903A and the second common voltage superimposer 904A will be further described with reference to
[0084] In
v.sub.smcm*=(v.sub.smu*+v.sub.smv*+v.sub.smw*)/3 (2)
[0085] Next, the first common voltage superimposer 903A determines whether the common mode voltage v.sub.smcm* is positive (step 90302), or negative or zero (step 90303). If the common mode voltage v.sub.smcm* is zero (No in step 90302 and No in step 90303), the first common voltage superimposer 903A sets the first three-phase common voltage as v.sub.ofst1=0 (step 90304).
[0086] If the common mode voltage v.sub.smcm* of the three-phase pulse voltage commands v.sub.smu*, v.sub.smv*, and v.sub.smw* is positive (Yes in step 90302), the operation is performed such that the common mode voltage of the first phase voltage commands v.sub.ssu1*, v.sub.ssv1*, and v.sub.ssw1* and is negative in order to reduce a change in voltage of the common mode voltage v.sub.smcm*. At this time, it is determined whether the minimum phase v.sub.min1 does not exceed a minimum value −v.sub.cs that can be outputted, that is, whether or not the value of the minimum phase v.sub.min1 is less than the minimum value −v.sub.cs (step 90305). If the minimum phase v.sub.min1 is less than the minimum value −v.sub.cs (Yes in step 90305), the first three-phase common voltage v.sub.ofst1 is determined such that the minimum phase v.sub.min1 is equal to the minimum value −v.sub.cs (step 90306). On the other hand, if the minimum phase v.sub.min1 is not less than the minimum value −v.sub.cs (No in step 90305), the first three-phase common voltage is set as v.sub.ofst1=0 (step 90307).
[0087] If the common mode voltage v.sub.smcm* of the three-phase pulse voltage commands v.sub.smu*, v.sub.smv*, and v.sub.smw* and is negative in step 90303), the operation is performed such that the common mode voltage of the first phase voltage commands v.sub.ssu1*, v.sub.ssv1*, and v.sub.ssw1* is positive in order to reduce a change in voltage of the common mode voltage v.sub.smcm*. At this time, it is determined whether or not the maximum phase v.sub.max1 exceeds a maximum value v.sub.cs that can be outputted (step 90308). If the maximum phase v.sub.max1 exceeds the maximum, value v.sub.cs (Yes in step 90308), the first three-phase common voltage v.sub.ofst1 is determined so that the maximum phase v.sub.max1 is equal to the maximum value v.sub.cs (step 90309). On the other hand, if the maximum phase v.sub.max1 does not exceed the maximum value v.sub.cs (No in step 90308), the first three-phase common voltage is set as v.sub.ofst1=0 (step 90310).
[0088] Finally, the first common voltage superimposer 903A superimposes the first three-phase common voltage v.sub.ofst1 on the first phase voltage commands v.sub.ssu1*, v.sub.ssv1*, and v.sub.ssw1* to generate the second phase voltage commands v.sub.ssu2*, v.sub.ssv2*, and v.sub.ssw2* (step 90311). Note that the second phase voltage commands v.sub.ssu2*, v.sub.ssv2*, and v.sub.ssw2* are phase voltage commands that are temporarily generated and are in the process of being corrected.
[0089] Next, the operation of the second common voltage superimposer 904A will be described with reference to
[0090] In
[0091] Note that when the amplitude of the sinusoidal phase voltage commands v.sub.su*, v.sub.sv*, and v.sub.sw* and is represented by “v*.sub.sphp”, a value obtained by dividing the amplitude v*.sub.sphp by a half of the direct current voltage v.sub.dc of the direct current power supply 3 is defined as a modulation factor “m”. Specifically, the modulation factor “m” can be expressed by the following expression (3).
m=(v*.sub.sphp/(v.sub.dc/2)) (3)
[0092] The second common voltage superimposer 904A determines whether or not the modulation factor “m” is 0.61 or more and 0.79 or less, whether or not it is 0.90 or more and 0.99 or less, or whether or not it is 1.23 or more (step 90402). If none of these conditions is satisfied (No in step 90402), the second three-phase common voltage is set as v.sub.ofst2=0 (step 90403). On the other hand, if any one of the conditions is satisfied (Yes in step 90402), the second common voltage superimposer 904A determines whether the common mode voltage v.sub.smcm* is positive (step 90404), or whether it is negative or zero (step 90408). If the common mode voltage v.sub.smcm* is zero (No in step 90404 and No in step 90408), the second common voltage superimposer 904A sets the second three-phase common voltage as v.sub.ofst2=0 (step 90412).
[0093] If the common mode voltage v.sub.smcm* of the three-phase pulse voltage commands v.sub.smu*, and v.sub.smv*, and v.sub.smw* is positive (Yes in step 90404), it is determined whether or not the maximum phase v.sub.max2 exceeds zero (step 90405). If the maximum phase v.sub.max2 exceeds zero (Yes in step 90405), the second three-phase common voltage is set as v.sub.ofst2=−v.sub.max2 (step 90406), or if the maximum phase v.sub.max2 does not exceed zero (No in step 90405), the second three-phase common voltage is set as v.sub.ofst2=0 (step 90407). As a result, the maximum phase v.sub.max2 is controlled to be zero or negative.
[0094] If the common mode voltage v.sub.smcm* of the three-phase pulse voltage commands v.sub.smu*, v.sub.smv*, and v.sub.smw* is negative in step 90408), it is determined whether or not the minimum phase v.sub.min2 is less than zero (step 90409). If the minimum phase v.sub.min2 is less than zero (Yes in step 90409), the second three-phase common voltage is set as v.sub.ofst2=−v.sub.min2 (step 90410), or if the minimum phase v.sub.min2 is zero or more (No in step 90409), the second three-phase common voltage is set as v.sub.ofst2=0 (step 90411). As a result, the minimum phase v.sub.min2 is controlled to be zero or positive.
[0095] Finally, the second common voltage superimposer 904A superimposes the second three-phase common voltage v.sub.ofst2 on the second phase voltage commands v.sub.ssu2*, v.sub.ssv2*, and v.sub.ssw2* to generate the third. phase voltage commands v.sub.ssu3*, v.sub.ssv3*, and v.sub.ssw3* (step 90413). As described above, the third phase voltage commands v.sub.ssu3*, v.sub.ssv3*, and v.sub.ssw3* are phase voltage commands having been. subjected to correction, which are generated using the phase voltage commands being corrected.
[0096] By the above processing, in a period in which the common mode voltage v.sub.smcm* of the three-phase pulse voltage commands v.sub.smu*, v.sub.smv*, and v.sub.smw*, that is, a three-phase sum of the three-phase pulse voltage commands v.sub.smu*, v.sub.smv*, and v.sub.smw* is not zero, the positive/negative polarity of the third phase voltage commands v.sub.ssu3*, v.sub.ssv3*, and v.sub.ssw3* is not switched. Furthermore, the positive/negative polarity of the third phase voltage commands v.sub.ssu3*, v.sub.ssv3*, and v.sub.ssw3* does not change from that of the first phase voltage commands v.sub.ssu1*, v.sub.ssv1*, and v.sub.ssw1* and that are voltage commands before the correction. This can reduce the number of switching operations in the H-bridge circuits 5, 6, and 7, and thus can reduce the switching loss in the power converter 1.
[0097] Returning to the description for
[0098] The PWM controller 906 generates the gate signals g.sub.su1′, g.sub.su3′, g.sub.sv1′, g.sub.sv3′, g.sub.sw1′, and g.sub.sw3′ for the second legs in the H-bridge circuits 5, 6, and 7 on the basis of the fourth phase voltage commands v.sub.ssu4*, v.sub.ssv4*, and v.sub.ssw4*.
[0099]
[0100] The horizontal axes in
[0101]
[0102]
[0103] In the case of
[0104] Table 2 below represents a relationship between an output voltage V.sub.ss of the H-bridge circuits 5, 6, and 7 and the gate signals g.sub.s1 to g.sub.s4 to the H-bridge circuits 5, 6, and 7. The voltage polarity controller 905 and the PWM controller 906 generate the gate signals to the H-bridge circuits 5, 6, and 7 using the relationship of Table 2.
TABLE-US-00002 TABLE 2 OUTPUT VOLTAGE V.sub.ss −v.sub.cs 0 v.sub.dc/2 g.sub.m1 L H L H g.sub.m2 L L H H g.sub.m3 H L H L g.sub.m4 H H L L
[0105] In Table 2 above, “H” represents “high”, which means a gate signal for controlling a corresponding semiconductor switching element to be on. In addition, “L” represents “low”, which means a gate signal for controlling a corresponding semiconductor switching element to be off.
[0106] Returning to the description for
[0107] In
[0108] Next, main points of the operation of the power converter 1 according to the first embodiment will be described using operation waveforms of main parts.
[0109] On the left side of
[0110] The “corrected H-bridge voltage command polarity” represents the polarity of the corrected H-bridge voltage commands. The “H-bridge output voltages” are the output voltages of the H-bridge circuits 5, 6, and 7. The “phase voltages” are the voltages outputted from the phases of the inverter circuit 4. The operation waveforms are normalized with “v.sub.dc/2”. In the operation waveforms, a U-phase waveform is represented by a solid line, a V-phase waveform is represented by a broken line, and a W-phase waveform is represented by an alternate long and short dash line. These representations are applied in common to other operation. waveforms described below.
[0111] The operation waveforms of
[0112] As described above, in the power converter 1, the “sinusoidal phase voltage commands” are calculated so that the motor 2 is operated with the desired torque command T*. Moreover, the “pulse voltage commands” are calculated by the three-phase pulse voltage command calculator 901, and the “H-bridge voltage commands” are obtained by subtracting the “three-phase pulse voltage commands” from the “sinusoidal phase voltage commands”. In the example of
[0113] Referring now to the waveform of the “corrected H-bridge voltage command polarity” in
[0114] In a case where the first common voltage superimposer 903A is absent, as illustrated in
[0115] In
[0116] However, referring to the waveform of the “corrected H-bridge voltage command polarity” in
[0117] During a period in which a three-phase sum of the “three-phase pulse voltage commands” is not zero, the second common voltage superimposer 904A calculates the second three-phase common voltage so that the positive/negative polarity of the “corrected H-bridge voltage commands” is not switched, and superimposes the calculated second three-phase common. voltage on the “H-bridge voltage commands being corrected”. In the example of
[0118] Next,
[0119] Referring to the waveform of the “corrected H-bridge voltage command polarity” in
[0120] Now,
[0121] In
[0122] Next,
[0123] As can be understood from the flowchart of
[0124] Next,
[0125] Referring to the waveform of the “corrected. H--bridge voltage command polarity” in
[0126] Next,
[0127] In
[0128] Next,
[0129] As can be understood from the flowchart of
[0130] As described above, in the power converter according to the first embodiment, the power conversion controller calculates the first three-phase common voltage common to the three phases, and generates the second phase voltage commands obtained by superimposing the calculated first three-phase common voltage on the first phase voltage commands. Moreover, the power conversion controller calculates the second three-phase common voltage common to the three phases, and generates the third phase voltage commands obtained by superimposing the calculated second three-phase common voltage on the second phase voltage commands. The power conversion controller generates the second gate signals to be applied to one leg of the first and second legs on the basis of the positive/negative polarity of the third phase voltage commands, and at the same time generates the second gate signals to be applied to another leg of the first and second legs on the basis of the third phase voltage commands. During the period in which the three-phase sum of the three-phase pulse voltage commands is not zero, the power conversion controller calculates the second three-phase common voltage so that the positive/negative polarity of the third phase voltage commands is not switched. As a result, the number of switching operations of the switching elements in one of the first and second legs is reduced, thereby making it possible to reduce the switching loss of the one leg. Therefore, the power converter can be efficiently controlled while reducing noise and harmonics.
[0131] Note that in the power converter according to the first embodiment, the capacitor voltage that is a voltage across the capacitor is preferably half or less of a half of the step width of the phase voltages of the inverter circuit, that is, a quarter or less of the voltage of the direct current power supply. Such setting can reduce harmonics and obtain the output voltage closer to a sine wave.
[0132] Moreover, in the power converter according to the first embodiment, the power conversion controller calculates the first three-phase common voltage so that the absolute value of the voltage value of each phase in the second phase voltage commands does not exceed the capacitor voltage. This restrains output of a voltage of a portion exceeding the maximum value and the minimum value that can be outputted by the first phase voltage commands, so that distortion of the phase voltages can be reduced.
[0133] Moreover, in the power converter according to the first embodiment, in the case where the modulation factor “m” is 0.61 or more and 0.79 or less, in the case where it is 0.90 or more and 0.99 or less, or in the case where it is 1.23 or more, the power conversion controller calculates the second three-phase common voltage so that the maximum value for three phases of the second phase voltage commands is zero or negative when the three-phase sum of the three-phase pulse voltage commands is positive. Also, the power conversion controller calculates the second three-phase common voltage so that the minimum value for three phases of the second phase voltage commands is zero or positive when the three-phase sum of the three-phase pulse voltage commands is negative. This makes the number of switching operations of the first leg of the single-phase bridge circuit smaller, so that the switching loss of the single-phase bridge circuit can be reduced.
[0134] Note that in the configuration of the power converter according to the first embodiment, a semiconductor switching element formed of a narrow band gap semiconductor can be used for the inverter circuit, and a semiconductor switching element formed of a wide band gap semiconductor can be used for the single-phase bridge circuit. With such a configuration, the switching loss of one leg of the first and second legs can be reduced, and the cost of the other leg of the first and second legs can be reduced. As a result, an increase in manufacturing cost of the power converter can be prevented while improving the efficiency of the operation of the power converter. Moreover, the problems on both the manufacturing cost and the difficulty of obtaining the element can be achieved.
[0135] Moreover, in the above-described configuration, of the first leg and the second leg constituting the single-phase bridge circuit, the leg controlled by the second gate signal generated on the basis of the positive/negative polarity of the third phase voltage commands may be configured to use a semiconductor switching element formed of a narrow bandgap semiconductor. With such a configuration, the cost in configuring the power converter can be further reduced.
[0136] Note that the capacitor voltage of the single-phase bridge circuit is preferably half or less of the step width of the phase voltages of the inverter circuit. Such setting can obtain the output voltage closer to a sine wave while reducing harmonics. Moreover, lowering the capacitor voltage of the single-phase bridge circuit can obtain an advantageously effect of reducing the switching loss in the single-phase bridge circuit.
Second Embodiment
[0137] In a general inverter circuit, a rated voltage is often set to a value at which the amplitude of the voltage between output lines is equal to the direct current voltage. The modulation factor “m” at this time is m=1.15.
[0138] Referring to the waveform of the “corrected H-bridge voltage command polarity” in
[0139] On the other hand, in the case of the operation with the operation waveforms of
[0140]
[0141]
[0142]
[0143] Next, processing different from that of
[0144] If the common mode voltage v.sub.smcm* of the three-phase pulse voltage commands v.sub.smu*, v.sub.smv*, and v.sub.smw* is positive (Yes in step 90814), it is determined whether or not the maximum phase v.sub.max2 is less than zero (step 90815). If the maximum phase v.sub.max2 is less than zero (Yes in step 90815), the second three-phase common voltage is set as v.sub.ofst2=−v.sub.max2 (step 90816), or if the maximum phase v.sub.max2 is zero or more (No in step 90815), the second three-phase common voltage is set as v.sub.ofst2=0 (step 90817). As a result, the maximum phase v.sub.max2 is controlled to be zero or positive.
[0145] If the common mode voltage of the three-phase pulse voltage commands v.sub.smu*, v.sub.smv*, and v.sub.smw* is negative (Yes in step 90818), it is determined whether or not the minimum phase v.sub.min2 exceeds zero (step 90819). If the minimum phase v.sub.min2 exceeds zero (Yes in step 90819), the second three-phase common voltage is set as v.sub.ofst2=−v.sub.min2 (step 90820), or if the minimum phase v.sub.min2 does not exceed zero (No in step 90819), the second three-phase common voltage is set as v.sub.ofst2=0 (step 90821). As a result, the minimum phase v.sub.min2 is controlled to be zero or negative.
[0146] Finally, the second common voltage superimposer 904B superimposes the second three-phase common voltage v.sub.ofst2 on the second phase voltage commands v.sub.ssu2*, v.sub.ssv2*, and v.sub.ssw2* to generate the third phase voltage commands v.sub.ssu3*, v.sub.ssv3*, and v.sub.ssw3* (step 90823).
[0147]
[0148]
[0149] Here, in the second embodiment, the “corrected H-bridge voltage commands” allow a change in the positive/negative polarity from that of the “H-bridge voltage commands” before the correction. As a result, the number of changes in polarity of the “corrected H-bridge voltage commands” is ten times in the fundamental wave period of the “sinusoidal phase voltage commands”. Although this shows an increase from six times in
[0150] As described above, in the power converter according to the second embodiment, in the case where the modulation factor is 0.90 or more and 0.99 or less, the power conversion controller calculates the second three-phase common voltage so that the maximum value for three phases of the second phase voltage commands is zero or positive when the three-phase sum of the three-phase pulse voltage commands is positive. On the other hand, the power conversion controller calculates the second three-phase common voltage so that the minimum value for three phases of the second phase voltage commands is zero or negative when the three-phase sum of the three-phase pulse voltage commands is negative. This enables control that fully exploits the allowable number of switching operations, so that noise and harmonics can be reduced while reducing the switching loss of the single-phase bridge circuit. As a result, an unprecedented and remarkable effect is obtained in which voltage with significantly small distortion can be applied to the load.
Third Embodiment
[0151] The first common voltage superimposer 903A of the first and second embodiments calculates the first three-phase common voltage so that the peak values of the second phase voltage commands v.sub.ssu2*, v.sub.ssv2*, and v.sub.ssw2* can be reduced. That is, the first three-phase common voltage is calculated so as not to exceed the maximum value v.sub.cs and the minimum value −v.sub.cs that can be outputted by the first phase voltage commands v.sub.ssu1*, v.sub.ssv2*, and v.sub.ssw1*. However, there is room for improvement in the control in the first embodiment and the second embodiment. If the peak values can be further reduced, the switching loss of the H-bridge circuits 5, 6, and 7 can be further reduced. Therefore, a third embodiment discloses a power converter that is configured to further reduce the peak values of the second phase voltage commands v.sub.ssu2*, v.sub.ssv2*, and v.sub.ssw2* to further reduce the switching loss of the H-bridge circuits 5, 6, and 7.
[0152]
[0153]
[0154] The first common voltage superimposer 903B calculates the first three-phase common voltage so that the peak values of the second phase voltage commands v.sub.ssu2*, v.sub.ssv2*, and v.sub.ssw2* can be reduced. The first common voltage superimposer 903B superimposes the calculated first three-phase common voltage on the first phase voltage commands v.sub.ssu1*, v.sub.ssv1*, and v.sub.ssw1*, and outputs the voltages obtained by the superimposition process to the second common voltage superimposer 904C as the second phase voltage commands v.sub.ssu2*, v.sub.ssv2*, and v.sub.ssw2*.
[0155]
[0156] In
v.sub.ofst1=−0.5×(v.sub.max1+v.sub.min1) (4)
[0157] Finally, the first common voltage superimposer 903B superimposes the first three-phase common voltage v.sub.ofst1 on the first phase voltage commands v.sub.ssu1*, v.sub.ssv1*, and v.sub.ssw1*, and generates the second phase voltage commands v.sub.ssu2*, v.sub.ssv2*, and v.sub.ssw2* (step 90903).
[0158] Next, the operation of the second common voltage superimposer 904C will be described.
[0159] In
[0160] The second common voltage superimposer 904C determines whether or not the modulation factor “m” is 0.67 or more and. 0.97 or less, or whether or not it is 1.11 or more (step 91002). If none of these conditions is satisfied. (No in step 91002), the second three-phase common voltage is set as v.sub.ofst2=0 (step 91003). On the other hand, if any one of the conditions is satisfied (Yes in step 91002), the second common voltage superimposer 904C determines whether the common mode voltage v.sub.smcm* is positive (step 91004), or whether it is negative or zero (step 91008). If the common mode voltage v.sub.smcm* is zero (No in step 91004 and No in step 91008), the second common voltage superimposer 904C sets the second three-phase common voltage as v.sub.ofst2=0 (step 91012).
[0161] If the common mode voltage v.sub.smcm* of the three-phase pulse voltage commands v.sub.smu*, v.sub.smv*, and v.sub.smw* is positive (Yes in step 91004), it is determined whether or not the maximum phase v.sub.max2 exceeds zero (step 91005). If the maximum phase v.sub.max2 exceeds zero (Yes in step 91005), the second three-phase common voltage is set as v.sub.ofst2=−v.sub.max2 (step 91006), but otherwise if the maximum phase v.sub.max2 does not exceed zero (No in step 91005), the second three-phase common voltage is set as v.sub.ofst2=0 (step 91007). As a result, the maximum phase v.sub.max2 is controlled to be zero or negative.
[0162] If the common mode voltage v.sub.smcm* of the three-phase pulse voltage commands v.sub.smu*, v.sub.smv*, and v.sub.smw* is negative (Yes in step 91008), it is determined whether or not the minimum phase v.sub.min2 is less than zero (step 91009). If the minimum phase v.sub.min2 is less than zero (Yes in step 91009), the second three-phase common voltage is set as v.sub.ofst2=−v.sub.min2 (step 91010), but otherwise if the minimum phase v.sub.min2 is zero or more (No in step 91009), the second three-phase common voltage is set as v.sub.ofst2=0 (step 91011). As a result, the minimum phase v.sub.min2 is controlled to be zero or positive.
[0163] Finally, the second common voltage superimposer 904C superimposes the second three-phase common voltage v.sub.ofst2 on the second phase voltage commands v.sub.ssu2*, v.sub.ssv2*, and v.sub.ssw2* to generate the third phase voltage commands v.sub.ssu3*, v.sub.ssv3*, and v.sub.ssw3* (step 91013).
[0164] By the above processing, in a period in which the common mode voltage v.sub.smcm* of the three-phase pulse voltage commands v.sub.smu*, v.sub.smv*, and v.sub.smw*, that is, a three-phase sum of the three-phase pulse voltage commands v.sub.smu*, v.sub.smv*, and v.sub.smw* is not zero, the positive/negative polarity of the third phase voltage commands v.sub.ssu3*, v.sub.ssv3*, and v.sub.ssw3* is not switched. Furthermore, the positive/negative polarity of the third phase voltage commands v.sub.ssu3*, v.sub.ssv3*, and v.sub.ssw3* does not change from that of the first phase voltage commands v.sub.ssu1*, v.sub.ssv1*, and v.sub.ssw1* that are voltage commands before the correction. This can reduce the number of switching operations in the H-bridge circuits 5, 6, and 7, so that the switching loss in the power converter 12 can be reduced.
[0165] Next, main points of the operation of the power converter 12 according to the third embodiment will be described.
[0166] In the example of
[0167] In addition, in a case where the first common voltage superimposer 903B is absent, the “H-bridge voltage commands” exceed the maximum value v.sub.cs (=0.45×v.sub.dc/2) and the minimum value −v.sub.cs that can be outputted. For this reason, distortion occurs in the “phase voltages” outputted by the power converter 12.
[0168] Next,
[0169] In
[0170] However, referring to the waveform of the “corrected H-bridge voltage command polarity” in
[0171] During a period in which a three-phase sum of the “three-phase pulse voltage commands” is not zero, the second common voltage superimposes 904C calculates the second three-phase common voltage so that the positive/negative polarity of the “corrected H-bridge voltage commands” is not switched, and superimposes the calculated second three-phase common voltage on the “H-bridge voltage commands being corrected”. In the example of
[0172] Next,
[0173] Referring the waveform of the “corrected H-bridge voltage command polarity” in
[0174] Next,
[0175] In
[0176] Next,
[0177] As can be understood from the flowchart of
[0178] As described above, in the power converter according to the third embodiment, the power conversion controller calculates the second three-phase common voltage so that the positive/negative polarity of the third phase voltage commands does not change from that of the first phase voltage commands. As a result, compared to the first embodiment and the second embodiment, the switching loss can be further reduced, thereby leading to an unprecedented and remarkable effect that a more efficient power converter can be configured.
[0179] Moreover, in the power converter according to the third embodiment, the power conversion controller generates, as the first three-phase common voltage, the value obtained by inverting the polarity of the average value of the maximum value and the minimum value of the first phase voltage commands. As a result, the peak value of the first phase voltage command can be reduced, so that the power converter can be efficiently controlled while reducing the possible distortion of the phase voltage outputted therefrom.
[0180] Moreover, in the power converter according to the third embodiment, in the case where the modulation factor “m” is 0.67 or more and 0.97 or less, or in the case where it is 1.11 or more, the power conversion controller calculates the second three-phase common voltage so that the maximum value of the second phase voltage commands zero or negative when the three-phase sum of the three-phase pulse voltage commands is positive. On the other hand, the power conversion. controller calculates the second three-phase common voltage so that the minimum value of the second phase voltage commands is zero or positive when the three-phase sum of the three-phase pulse voltage commands is negative. This reduces the number of switching operations of the first leg of the single-phase bridge circuit, and thus can reduce the switching loss of the single-phase bridge circuit.
Fourth Embodiment
[0181] In the third embodiment, in the case of the operation waveforms in
[0182]
[0183]
[0184] In a period in which a three-phase sum of the three-phase pulse voltage commands v.sub.smu*, v.sub.smv*, and v.sub.smw* is not zero, the second common voltage superimposer 904D calculates the second three-phase common voltage and superimposes the second three-phase common voltage on the second phase voltage commands v.sub.ssu2*, v.sub.ssv2*, and v.sub.ssw2* so that the positive/negative polarity of the third phase voltage commands v.sub.ssu3*, v.sub.ssv3*, and v.sub.ssw3* is not switched.
[0185]
[0186] In
[0187] The second common voltage superimposer 904D determines whether or not the modulation factor “m” is 0.67 or more and less than 0.86, or whether or not it is 1.11 or more (step 91102). If none of these conditions is satisfied (No in step 91102), the operation proceeds to step 91103. On the other hand, if any one of the conditions is satisfied (Yes in step 91102), the second common voltage superimposer 904D determines whether the common mode voltage v.sub.smcm* is positive (step 91105), or negative or zero (step 91109). If the common mode voltage v.sub.smcm* is zero (No in step 91105 and No in step 91109), the second common voltage superimposer 904D sets the second three-phase common voltage at v.sub.ofst2=0 (step 91113).
[0188] If the common mode voltage v.sub.smcm* of the three-phase pulse voltage commands v.sub.smu*, v.sub.smv*, and v.sub.smw* is positive (Yes in step 91105), it is determined whether or not the maximum phase v.sub.max2 exceeds zero (step 91106). If the maximum phase v.sub.max2 exceeds zero (Yes in step 91106), the second three-phase common voltage is set as v.sub.ofst2=−v.sub.max2 (step 91107), or if the maximum phase v.sub.max2 does not exceed zero (No in step 91106), the second three-phase common voltage is set as v.sub.ofst2=0 (step 91108). As a result, the maximum phase v.sub.max2 is controlled to be zero or negative.
[0189] If the common mode voltage v.sub.smcm* of the three-phase pulse voltage commands v.sub.smu*, v.sub.smv*, and v.sub.smw* is negative (Yes in step 91109), it is determined whether or not the minimum phase v.sub.min2 is less than zero (step 91110). If the minimum phase v.sub.min2 is less than zero (Yes in step 91110), the second three-phase common voltage is set as v.sub.ofst2=−v.sub.min2 (step 91111), or if the minimum phase v.sub.min2 is zero or more (No in step 91110), the second three-phase common voltage is set as v.sub.ofst2=0 (step 91112). As a result, the minimum phase v.sub.min2 is controlled to be zero or positive.
[0190] After the processing of steps 91107, 91108, and 91111 to 91113 is completed, the second common voltage superimposer 904D superimposes the second three-phase common voltage v.sub.ofst2 on the second phase voltage commands v.sub.ssu2*, v.sub.ssv2*, and v.sub.ssw2* to generate the third phase voltage commands v.sub.ssu3*, v.sub.ssv3*, and v.sub.ssw3* (step 91123).
[0191] Moreover, the second. common voltage superimposer 904D determines whether or not the modulation factor “m” is 0.86 or more and 0.97 or less (step 91103). If this condition is not satisfied. (No in step 91103), the second three-phase common voltage is set as v.sub.ofst2=0 (step 91104). On the other hand, if the condition in step 91103 is satisfied (Yes in step 91103), the second common voltage superimposer 904D determines whether the common mode voltage v.sub.smcm* is positive (step 91114), or whether it is negative or zero (step 91118). If the common mode voltage v.sub.smcm* is zero (No in step 91114 and No in step 91118), the second common voltage superimposer 904D sets the second three-phase common voltage as v.sub.ofst2=0 (step 91122).
[0192] If the common mode voltage v.sub.smcm* of the three-phase pulse voltage commands v.sub.smu*, v.sub.smv*, and v.sub.smw* is positive (Yes in step 91114), it is determined whether or not the middle phase v.sub.mid2 exceeds zero (step 91115). If the middle phase v.sub.mid2 exceeds zero (Yes in step 91115), the second three-phase common voltage is set as v.sub.ofst2=−v.sub.mid2 (step 91116), or if the middle phase v.sub.mid2 does not exceed zero (No in step 91115), the second three-phase common voltage is set as v.sub.ofst2=0 (step 91117). As a result, the middle phase v.sub.mid2 is controlled to be zero or positive.
[0193] If the common mode voltage v.sub.smcm* of the three-phase pulse voltage commands v.sub.smu*, v.sub.smv*, and v.sub.smw* is negative (YES in step 91118), it is determined whether or not the middle phase v.sub.mid2 is less than zero (step 91119). If the middle phase v.sub.mid2 is less than zero (Yes in step 91119), the second three-phase common voltage is set as v.sub.ofst2=−v.sub.mid2 (step 91120), or if the middle phase v.sub.mid2 is zero or more (No in step 91119), the second three-phase common voltage is set as v.sub.ofst2=0 (step 91121). As a result, the middle phase v.sub.mid2 is controlled to be zero or negative.
[0194] Finally, the second common voltage superimposer 904D superimposes the second three-phase common voltage v.sub.ofst2 on the second phase voltage commands v.sub.ssu2*, v.sub.ssv2*, and v.sub.ssw2* to generate the third phase voltage commands v.sub.ssu3*, v.sub.ssv3*, and v.sub.ssw3* (step 91123).
[0195] Next, main points of the operation of the power converter 14 according to the fourth embodiment will be described. Note that the modulation factor “m” is m=0.95.
[0196]
[0197] Referring to the waveform of the “corrected H-bridge voltage command polarity” in
[0198] On the other hand, referring to
[0199] Here, in the fourth embodiment, the “corrected H-bridge voltage commands” allow a change in positive/negative polarity from that of the “H-bridge voltage commands” before the correction. As a result, the number of changes in polarity of the “corrected H-bridge voltage commands” is ten times in the fundamental wave period of the “sinusoidal phase voltage commands”. Although this is an increase from six times in
[0200] As described above, in the power converter according to the fourth embodiment, in the case where the modulation factor is 0.86 or more and 0.97 or less, the power conversion controller calculates the second three-phase common voltage so that the middle value for three phases of the second phase voltage commands is zero or negative when the three-phase sum of the three-phase pulse voltage commands is positive. On the other hand, the power conversion controller calculates the second three-phase common voltage so that the middle value for three phases of the second phase voltage commands is zero or positive when the three-phase sum of the three-phase pulse voltage commands is negative. This enables control that fully exploits the allowable number of switching operations, so that noise and harmonics can be reduced while reducing the switching loss of the single-phase bridge circuit. As a result, an unprecedented and remarkable effect is exerted in which a voltage with smaller distortion can be applied to the load.
[0201] The following lays out conditions of the modulation factor “m” when the second three-phase common voltage is superimposed in the second common voltage superimposer of the first to fourth embodiments.
[0202]
[0203] As described above, in a general inverter circuit, the number of switching operations with the modulation factor of m=1.15 that is a condition in the rated voltage is ten times. In contrast to this, as illustrated in
[0204]
[0205]
[0206]
[0207]
[0208]
[0209] Next, a hardware configuration of the power converter according to the first to fourth embodiments described above will be described with reference to
[0210] The functions of the power conversion controller can be implemented using a processing circuitry. In
[0211] In
[0212] In the case where the processor 17 and the storage device 18 are used, the functions of the power conversion controller are implemented by software, firmware, or a combination thereof. The software or firmware is described as a program and stored in the storage device 18. The processor 17 reads and executes the programs stored in the storage device 18. It can also be said that these programs cause a computer to execute procedure and method in the functions of the power conversion controller.
[0213] One or some of the functions of the power conversion controller may be implemented by hardware and the some other thereof may be implemented by software or firmware. For example, the functions of the dead time inserters 902 and 907 and the PWM controller 906 may be implemented using dedicated hardware, and the functions of the three-phase pulse voltage command calculator 901, the first common voltage superimposers 903A and 903B, the second common. voltage superimposers 904A, 904B, 904C, and 904D, the voltage polarity controller 905, and the subtractor 908 may be implemented using the processor 17 and the storage device 18.
[0214] Note that the present description has been given by way of example, in which the load is the motor and the motor is subjected to torque control in terms of the operation waveforms and the like, but the present disclosure is not limited to this example. The motor may be subjected to speed control. Also, the load may be something other than the motor. Moreover, as an example of connection to the load, the power converter may be connected to a system power supply or another power converter, so as to be used for controlling active electric power and reactive electric power. In addition, although the direct current power supply has been described using the symbol of a voltage source, a battery may be used therefor, or a voltage rectified using a transformer and a semiconductor element, which is originated from an electric power system may be used therefor. Furthermore, although the three-phase three-level inverter exemplified as the inverter circuit is of a diode clamp type as an example, the three-phase three-level inverter may be of a capacitor clamp type, or another type in which a bidirectional switch is used between an output terminal and a direct current neutral point for each phase.
[0215] The semiconductor switching element used in the three-phase inverter circuit and the single-phase bridge circuit has been described using the symbol of IGBT or MOSFET, but any element can be used as long as the semiconductor element can be turned on and off. In addition, as the wide bandgap semiconductor element, not only an element using SiC but also an element using GaN can be used, and the direct current voltage and the element withstand voltage can be freely set without being limited to the values used in the embodiments. Furthermore, the present description has been given for use of the element made of Si for the three-phase inverter circuit and the element made of SiC for the H-bridge circuit, but the former element and the latter element can be interchanged in usage between these circuits for different application. Using the element made of SiC on the high voltage side as just described can construct the power converter having a higher direct current voltage. Although the description has been based on the assumption that the voltage waveform of the three-phase inverter circuit is on one pulse voltage, the voltage waveform is not limited to the number of pulses in the examples. In other respects, a voltage of a plurality of numbers of pulses may be Generated by PWM control in which the voltage command and the carrier are compared to each other, or a pulse pattern in which the phase angle α is optimized to minimize the loss of the inverter or the load may be used.
[0216] The configurations illustrated in the above embodiments illustrate examples, each of which can be combined with. other publicly known. techniques, and the embodiments can. be combined together. The illustrated configuration. can. be partially omitted and/or modified without departing from. the scope of the present disclosure.
REFERENCE SIGNS LIST
[0217] 1, 10, 12, 14 power converter; 2 motor; 3 direct current power supply; 4 inverter circuit; 4a, 4b, 4c alternating current end; 5, 6, 7 H-bridge circuit; 5a1, 5a2, 6a1, 6a2, 7a1, 7a2 midpoint; 8 motor controller; 9A, 11B, 13C, 15D power conversion controller; 16 dedicated processing circuitry; 17 processor; 18 storage device; 901 three-phase pulse voltage command calculator; 902, 907 dead time inserter; 903A, 903B first common voltage superimposer; 904A, 904B, 904C, 904D second common voltage superimposer; 905 voltage polarity controller; 906 PWM controller; 908 subtractor.