Device and method of performing signal compensation

Abstract

A signal compensation device comprises a first filter circuit, for processing a broadband signal, to generate a first analog time-domain signal; a second filter circuit, for processing the broadband signal, to generate a second analog time-domain signal; a first transform circuit, for transforming the first analog time-domain signal to a first digital time-domain signal; a second transform circuit, for transforming the second analog time-domain signal to a second digital time-domain signal; a third transform circuit, for transforming the first digital time-domain signal to a first frequency-domain signal; a fourth transform circuit, for transforming the second digital time-domain signal to a second frequency-domain signal; and a processing circuit, for generating a time-domain compensation response according to the first frequency-domain signal and the second frequency-domain signal.

Claims

1. A signal compensation device comprising: a first filter circuit, for processing a broadband signal, to generate a first analog time-domain signal; a second filter circuit, for processing the broadband signal, to generate a second analog time-domain signal; a first transform circuit, coupled to the first filter circuit, for transforming the first analog time-domain signal to a first digital time-domain signal; a second transform circuit, coupled to the second filter circuit, for transforming the second analog time-domain signal to a second digital time-domain signal; a third transform circuit, coupled to the first transform circuit, for transforming the first digital time-domain signal to a first frequency-domain signal; a fourth transform circuit, coupled to the second transform circuit, for transforming the second digital time-domain signal to a second frequency-domain signal; and a processing circuit, coupled to the third transform circuit and the fourth transform circuit, for generating a time-domain compensation response according to the first frequency-domain signal and the second frequency-domain signal, wherein the time-domain compensation response is for compensating the first digital time-domain signal; wherein the processing circuit comprising: a computing circuit, coupled to the third transform circuit and the fourth transform circuit, for generating a frequency-domain compensation response according to the first frequency-domain signal and the second frequency-domain signal; and a fifth transform circuit, coupled to the computing circuit, for transforming the frequency-domain compensation response to the time-domain compensation response; wherein the frequency-domain compensation response is defined according to the following equation: $H=\left[\begin{array}{c}C\left(-\frac{f_S}{2}\right)\\ C\left(-\frac{f_S}{2}+f_{\mathrm{step}}\right)\\ C\left(-\frac{f_S}{2}+2f_{\mathrm{step}}\right)\\ \mathrm{.Math.}\\ C\left(\mathrm{DC}\right)\\ C\left(f_{\mathrm{step}}\right)\\ \mathrm{.Math.}\\ C\left(\frac{f_S}{2}-f_{\mathrm{step}}\right)\end{array}\right],$ wherein C(ω) is a difference function related to the first frequency-domain signal and the second frequency-domain signal, f.sub.S is a sampling rate of the first transform circuit and the second transform circuit, and f.sub.step is a frequency interval.

2. The signal compensation device of claim 1, further comprising: a signal generating circuit, coupled to the first filter circuit and the second filter circuit, for generating the broadband signal.

3. The signal compensation device of claim 1, wherein the broadband signal is an impulse signal.

4. The signal compensation device of claim 1, wherein the first filter circuit and the second filter circuit are analog baseband filters.

5. The signal compensation device of claim 1, wherein the first transform circuit and the second transform circuit are analog-to-digital converters (ADCs).

6. The signal compensation device of claim 1, wherein the third transform circuit and the fourth transform circuit perform a Fast Fourier Transform (FFT), to transform the first digital time-domain signal and the second digital time-domain signal to the first frequency-domain signal and the second frequency-domain signal, respectively.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic diagram of a communication system according to an example of the present invention.

(2) FIG. 2 is a schematic diagram of a signal compensation device according to an example of the present invention.

(3) FIG. 3 is a schematic diagram of a processing circuit according to an example of the present invention.

(4) FIG. 4 is a schematic diagram of a signal compensation device according to an example of the present invention.

(5) FIG. 5 is a schematic diagram of a signal compensation device according to an example of the present invention.

(6) FIG. 6 is a schematic diagram of a plurality of frequency-domain signals according to an example of the present invention.

(7) FIG. 7 is a flowchart of a process according to an example of the present invention.

(8) FIG. 8 is a flowchart of a process according to an example of the present invention.

DETAILED DESCRIPTION

(9) FIG. 1 is a schematic diagram of a communication system 10 according to an example of the present invention. The communication system 10 may be any communication system using an orthogonal frequency-division multiplexing (OFDM) technique (or termed as discrete multi-tone modulation (DMT) technique), and is briefly composed of a transmitter TX and a receiver RX. In FIG. 1, the transmitter TX and the receiver RX are simply utilized for illustrating the structure of the communication system 10. For example, the communication system 10 may be any wired communication system such as an asymmetric digital subscriber line (ADSL) system, a power line communication (PLC) system or an Ethernet over coax (EOC), or may be any wireless communication system such as a wireless local area network (WLAN), a Digital Video Broadcasting (DVB) system, a Long Term Evolution (LTE) system, a Long Term Evolution-advanced (LTE-A) system or a 5th generation (5G) system. In addition, the transmitter TX and the receiver RX may be installed in a mobile phone, a laptop, etc., but are not limited herein.

(10) FIG. 2 is a schematic diagram of a signal compensation device 20 according to an example of the present invention. The signal compensation device 20 may be utilized in the transmitter TX or the receiver RX of FIG. 1, for generating a compensation response, to eliminate the IQ imbalance (or the IQ mismatch). The signal compensation device 20 includes a first filter circuit 200, a second filter circuit 210, a first transform circuit 202, a second transform circuit 212, a third transform circuit 204, a fourth transform circuit 214 and a processing circuit 206. In detail, the first filter circuit 200 processes a broadband signal sig_broadband, to generate a first analog time-domain signal sig_time_anal1. The second filter circuit 210 processes the broadband signal sig_broadband, to generate a second analog time-domain signal sig_time_anal2. The first transform circuit 202 is coupled to the first filter circuit 200, for transforming the first analog time-domain signal sig_time_anal1 to a first digital time-domain signal sig_time_dig1. The second transform circuit 212 is coupled to the second filter circuit 210, for transforming the second analog time-domain signal sig_time_anal2 to a second digital time-domain signal sig_time_dig2. The third transform circuit 204 is coupled to the first transform circuit 202, for transforming the first digital time-domain signal sig_time_dig1 to a first frequency-domain signal sig_freq1. The fourth transform circuit 214 is coupled to the second transform circuit 212, for transforming the second digital time-domain signal sig_time_dig2 to a second frequency-domain signal sig_freq2. The processing circuit 206 is coupled to the third transform circuit 204 and the fourth transform circuit 214, for generating a time-domain compensation response resp_comp_time according to the first frequency-domain signal sig_freq1 and the second frequency-domain signal sig_freq2.

(11) In one example, the first analog time-domain signal sig_time_anal1, the first digital time-domain signal sig_time_dig1 and the first frequency-domain signal sig_freq1 are signals on an in-phase signal path, and the second analog time-domain signal sig_time_anal2, the second digital time-domain signal sig_time_dig2 and the second frequency-domain signal sig_freq2 are signals on a quadrature-phase signal path. In one example, the first analog time-domain signal sig_time_anal1, the first digital time-domain signal sig_time_dig1 and the first frequency-domain signal sig_freq1 are signals on the quadrature-phase signal path, and the second analog time-domain signal sig_time_anal2, the second digital time-domain signal sig_time_dig2 and the second frequency-domain signal sig_freq2 are signals on the in-phase signal path.

(12) FIG. 3 is a schematic diagram of a processing circuit 30 according to an example of the present invention. The processing circuit 30 may be used for realizing the processing circuit 206 of FIG. 2, but is not limited herein. The processing circuit 30 includes a computing circuit 300 and a fifth transform circuit 302. The computing circuit 300 is coupled to the third transform circuit 204 and the fourth transform circuit 214, for generating a frequency-domain compensation response resp_comp_freq according to the first frequency-domain signal sig_freq1 and the second frequency-domain signal sig_freq2. The fifth transform circuit 302 is coupled to the computing circuit 300, for transforming the frequency-domain compensation response resp_comp_freq to the time-domain compensation response resp_comp_time. In one example, the frequency-domain compensation response resp_comp_freq is related to a difference between the first frequency-domain signal sig_freq1 and the second frequency-domain signal sig_freq2. The difference may include a magnitude response difference and/or a phase response difference, but is not limited herein.

(13) FIG. 4 is a schematic diagram of a signal compensation device 40 according to an example of the present invention. The signal compensation device 40 may be utilized in the transmitter TX or the receiver RX of FIG. 1. The signal compensation device 40 includes a signal generating circuit 400 and the signal compensation device 20. In detail, the signal generating circuit 400 is coupled to the signal compensation device 20 (e.g., the first filter circuit 200 and the second filter circuit 210), for generating the broadband signal sig_broadband. The signal compensation device 20 uses the broadband signal sig_broadband to generate the time-domain compensation response resp_comp_time. The operations of the signal compensation device 20 can be referred to the previous description, and are not narrated herein.

(14) In one example, the broadband signal sig_broadband is an impulse signal. That is, the impulse signal is used as an input signal (or a testing signal). In addition, after a Fast Fourier Transform (FFT) is performed, the impulse signal is a constant in the frequency spectrum. In other words, the impulse signal has the same energy at each frequency point. In one example, the first filter circuit 200 and the second filter circuit 210 are analog baseband filters. In one example, the first transform circuit 202 and the second transform circuit 212 are analog-to-digital converters (ADCs). In one example, the third transform circuit 204 and the fourth transform circuit 214 perform the FFT, to transform the first digital time-domain signal sig_time_dig1 and the second digital time-domain signal sig_time_dig2 to the first frequency-domain signal sig_freq1 and the second frequency-domain signal sig_freq2, respectively.

(15) FIG. 5 is a schematic diagram of a signal compensation device 50 according to an example of the present invention. The signal compensation device 50 may be utilized in the transmitter TX or the receiver RX of FIG. 1, for eliminating the IQ imbalance (or the IQ mismatch). The signal compensation device 50 includes a first filter circuit 500 (e.g., the first filter circuit 200), a second filter circuit 510 (e.g., the second filter circuit 210), a first transform circuit 502 (e.g., the first transform circuit 202), a second transform circuit 512 (e.g., the second transform circuit 212) and a compensation circuit 504. In detail, the first filter circuit 500 is for processing an input signal sig_input, to generate a first analog signal sig_anal1. The second filter circuit 510 is for processing the input signal, to generate a second analog signal sig_anal2. The first transform circuit 502 is coupled to the first filter circuit 500, for transforming the first analog signal sig_anal1 to a first digital signal sig_dig1. The second transform circuit 512 coupled to the second filter circuit, for transforming the second analog signal sig_anal2 to a second digital signal sig_dig2. The compensation circuit 504 is coupled to the first transform circuit 502, for compensating the first digital signal sig_dig1 according to a compensation response, to generate a compensation signal sig_comp. That is, the compensation circuit 504 compensates the first digital signal sig_dig1 according to the compensation response, such that the responses on the in-phase signal path and the quadrature-phase signal path are the same. The IQ imbalance caused by the response different is eliminated.

(16) In one example, the compensation circuit 504 is a digital baseband filter. In one example, the compensation response is the time-domain compensation response resp_comp_time generated by the signal compensation device 20. In one example, the first analog signal sig_anal1, the second analog signal sig_anal2, the first digital signal sig_dig1, the second digital signal sig_dig2 and the compensation signal sig_comp are time-domain signals.

(17) In one example, the first analog signal sig_anal1, the first digital signal sig_dig1 and the compensation signal sig_comp are signals on the in-phase signal path, and the second analog signal sig_anal2 and the second digital signal sig_dig2 are signals on the quadrature-phase signal path. In one example, the first analog signal sig_anal1, the first digital signal sig_dig1 and the compensation signal sig_comp are signals on the quadrature-phase signal path, and the second analog signal sig_anal2 and the second digital signal sig_dig2 are signals on the in-phase signal path.

(18) The following example is used for illustrating how the signal compensation devices 40 and 50 compensate the signal(s) on the in-phase signal path, to eliminate the IQ imbalance. First, the signal generating circuit 400 generates an impulse signal x(t) (i.e., the broadband signal sig_broadband). The first filter circuit 200 and the second filter circuit 210 generate time-domain signals y.sub.I(t) and y.sub.Q(t) (e.g., the first analog time-domain signal sig_time_anal1 and the second analog time-domain signal sig_time_anal2), respectively, according to the impulse signal x(t), as follows:
y.sub.I(t)=h.sub.I(x(t))=conv(h.sub.I(t),x(t)),  (Eq. 1)
y.sub.Q(t)=h.sub.Q(x(t))=conv(h.sub.Q(t),x(t)),  (Eq. 2)
wherein h.sub.I(t) and h.sub.Q(t) are impulse responses of the first filter circuit 200 and the second filter circuit 210, respectively, and conv( ) is a convolution function. Then, the third transform circuit 204 and the fourth transform circuit 214 transform the time-domain signals y.sub.I(t) and y.sub.Q(t) to frequency-domain signals Y.sub.I(ω) and Y.sub.Q(ω), respectively (e.g., the first frequency-domain signal sig_freq1 and the second frequency-domain signal sig_freq2), after the time-domain signals y.sub.I(t) and y.sub.Q(t) pass via ADCs. The frequency-domain signals Y.sub.I(ω) and Y.sub.Q(ω) can be expressed as following equations according to a convolution theory:
Y.sub.I(ω)=H.sub.I(ω)X(ω),  (Eq. 3)
Y.sub.Q(ω)=H.sub.Q(ω)X(ω),  (Eq. 4)
wherein X(ω) is the impulse signal x(t) after the FFT is performed, and H.sub.I(ω) and H.sub.Q(ω) are frequency responses of the first filter circuit 200 and the second filter circuit 210, respectively. Due to that the impulse signal X(ω) is a constant, the equations (Eq. 3) and (Eq. 4) can be derived as follows:
H.sub.I(ω)∝Y.sub.I(ω),  (Eq. 5)
H.sub.Q(ω)∝Y.sub.Q(ω).  (Eq. 6)

(19) That is, the frequency response H.sub.I(ω) is proportional to the frequency-domain signal Y.sub.I(ω), and the frequency response H.sub.Q(ω) is proportional to the frequency-domain signal Y.sub.Q(ω). Thus, the computing circuit 300 may use the frequency-domain signals Y.sub.I(ω) and Y.sub.Q(ω) to compute a frequency compensation response H. According to the equations (Eq. 3) and (Eq. 4), the computing circuit 300 computes magnitude responses (|Y.sub.I(ω)| and Y.sub.Q(ω)|) and phase responses (∠Y.sub.I(ω) and ∠Y.sub.Q(ω)) of the frequency-domain signals Y.sub.I(ω) and Y.sub.Q(ω) as shown in subfigures (a) and (b) of FIG. 6. Thus, a magnitude response difference G(ω) and a phase response difference P(ω) can be obtained according to the following equations:

(20) $\begin{array}{cc}G\left(\omega \right)=\frac{.Math.Y_Q\left(\omega \right).Math.}{.Math.Y_I\left(\omega \right).Math.},& \left(\mathrm{Eq}.7\right)\\ P\left(\omega \right)=\angle Y_Q\left(\omega \right)-\angle Y_I\left(\omega \right).& \left(\mathrm{Eq}.8\right)\end{array}$

(21) In the equation (Eq. 7), the magnitude response |Y.sub.Q(ω)| of the frequency-domain signal Y.sub.Q(w) is normalized according to the magnitude response |Y.sub.I(ω)| of the frequency-domain signal Y.sub.I(ω). Thus, a product of the magnitude response difference G(ω) and the magnitude response |Y.sub.I(ω)| is the same as the magnitude response |Y.sub.Q(ω)|. In other words, the compensated magnitude response on the in-phase signal path is the same as the magnitude response on the quadrature-phase signal path. In addition, a sum of the phase response difference P(ω) and the phase response ∠Y.sub.I(ω) is the same as the phase response ∠Y.sub.Q(ω). The compensated phase response on the in-phase signal path is the same as the phase response on the quadrature-phase signal path. According to the equations (Eq. 7) and (Eq. 8), the computing circuit 300 computes a difference function C(ω) and the frequency compensation response H (e.g., the frequency-domain compensation response resp_comp_freq) as follows:

(22) $\begin{array}{cc}C\left(\omega \right)=G\left(\omega \right).Math.\exp \left(i.Math.P\left(\omega \right)\right)=\frac{.Math.Y_Q\left(\omega \right).Math.}{.Math.Y_I\left(\omega \right).Math.}.Math.\exp \left(i.Math.\left(\angle Y_Q\left(\omega \right)-\angle Y_I\left(\omega \right)\right)\right),& \left(\mathrm{Eq}.9\right)\\ H=\left[\begin{array}{c}C\left(-\frac{f_S}{2}\right)\\ C\left(-\frac{f_S}{2}+f_{\mathrm{step}}\right)\\ C\left(-\frac{f_S}{2}+2f_{\mathrm{step}}\right)\\ \mathrm{.Math.}\\ C\left(\mathrm{DC}\right)\\ C\left(f_{\mathrm{step}}\right)\\ \mathrm{.Math.}\\ C\left(\frac{f_S}{2}-f_{\mathrm{step}}\right)\end{array}\right],& \left(\mathrm{Eq}.10\right)\end{array}$
wherein f.sub.S is a sampling rate of the first transform circuit 202 and the second transform circuit 212, and f.sub.step is a frequency interval. In addition, the fifth transform circuit 302 may transform the frequency compensation response H to an impulse compensation response h[n] (e.g., the time-domain compensation response resp_comp_time) via an Inverse Discrete Fourier Transform (IDFT) as follows:

(23) $\begin{array}{cc}h\left[n\right]=\mathrm{IDFT}\left(H\right)=\frac{1}{N}\underset{k=0}{\overset{N-1}{.Math.}}\exp \left(\frac{i2\pi \mathrm{nk}}{N}\right)\times H\left[k\right],\mathrm{wherein}N=\frac{f_S}{f_{\mathrm{step}}}.& \left(\mathrm{Eq}.11\right)\end{array}$

(24) Then, the signal compensation device 50 generates a time-domain signal k.sub.I[n] (e.g., the first digital signal sig_dig1) according to an input signal via the first filter circuit 500 and the first transform circuit 502. The signal compensation device 50 generates a time-domain signal k.sub.Q[n] (e.g., the second digital signal sig_dig2) according to the input signal via the second filter circuit 510 and the second transform circuit 512. The compensation circuit 504 uses the impulse compensation response h[n] to compensate the time-domain signal k.sub.I[n] as follows:
k.sub.I′[n]=conv(h[n],k.sub.I[n]),  (Eq. 12)
wherein k.sub.I′[n] is a compensation result (e.g., the compensation signal sig_comp) of the time-domain signal k.sub.I[n]. Thus, the responses (e.g., the magnitude responses and the phase responses) on the in-phase signal path and the quadrature-phase signal path are the same. The problem of the IQ imbalance can be solved.

(25) FIG. 6 is a schematic diagram of a plurality of frequency-domain signals Y.sub.I(ω) and Y.sub.Q(ω) according to an example of the present invention. The subfigure (a) illustrates the magnitude responses of the frequency-domain signals Y.sub.I(ω) and Y.sub.Q(ω). The subfigure (b) illustrates the phase responses of the frequency-domain signals Y.sub.I(ω) and Y.sub.Q(ω). The subfigure (c) illustrates the magnitude response difference G(ω) (or termed as an IQ amplitude mismatch) of the frequency-domain signals Y.sub.I(ω) and Y.sub.Q(ω). The subfigure (d) illustrates the phase response difference P(ω) (or termed as an IQ phase mismatch) of the frequency-domain signals Y.sub.I(ω) and Y.sub.Q(ω). The computing circuit 300 computes the difference function C(ω) according to the subfigures (c) and (d), to obtain the frequency compensation response H. Operations of the computing circuit 300 can be referred to the previous description, and are not narrated herein.

(26) Operations of the signal compensation device 20 in the above examples can be summarized into a process 70 shown in FIG. 7. The process 70 is utilized in the transmitter TX or the receiver RX, and includes the following steps:

(27) Step 700: Start.

(28) Step 702: Process a broadband signal, to generate a first analog time-domain signal.

(29) Step 704: Process the broadband signal, to generate a second analog time-domain signal.

(30) Step 706: Transform the first analog time-domain signal to a first digital time-domain signal.

(31) Step 708: Transform the second analog time-domain signal to a second digital time-domain signal.

(32) Step 710: Transform the first digital time-domain signal to a first frequency-domain signal.

(33) Step 712: Transform the second digital time-domain signal to a second frequency-domain signal.

(34) Step 714: Generate a time-domain compensation response according to the first frequency-domain signal and the second frequency-domain signal.

(35) Step 716: End.

(36) Operations of the signal compensation device 50 in the above examples can be summarized into a process 80 shown in FIG. 8. The process 80 is utilized in the transmitter TX or the receiver RX, and includes the following steps:

(37) Step 800: Start.

(38) Step 802: Process an input signal, to generate a first analog signal.

(39) Step 804: Process the input signal, to generate a second analog signal.

(40) Step 806: Transform the first analog signal to a first digital signal.

(41) Step 808: Transform the second analog signal to a second digital signal.

(42) Step 810: Compensate the first digital signal according to a compensation response, to generate a compensation signal.

(43) Step 812: End.

(44) The processes 70 and 80 are used for illustrating the operations of the signal compensation devices 20 and 50, respectively. Detailed description and variations of the processes 70 and 80 can be referred to the previous description, and are not narrated herein.

(45) It should be noted that realizations of the signal compensation devices 20, 40 and 50 (including the first filter circuits 200 and 500, the second filter circuits 210 and 510, the first transform circuits 202 and 502, the second transform circuits 212 and 512, the third transform circuit 204, the fourth transform circuit 214, the processing circuit 206, the signal generating circuit 400 and the compensation circuit 504) are various. For example, the devices (circuits) mentioned above may be integrated into one or more devices (circuits). In addition, the signal compensation devices 20, 40 and 50 may be realized by hardware (e.g., circuit), software, firmware (known as a combination of a hardware device, computer instructions and data that reside as read-only software on the hardware device), an electronic system or a combination of the devices mentioned above, but are not limited herein.

(46) To sum up, the present invention provides a device and a method of performing signal compensation. The signal compensation device uses the broadband signal to obtain the compensation response, and compensates the signal(s) on the in-phase signal path or the quadrature-phase signal path according to the compensation response, to eliminate the IQ imbalance at the plurality of frequency points. The present invention provides a better performance than the prior art.

(47) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.