Method for improved manufacturing of a photodiode-based optical sensor and associated device

Abstract

A process for fabricating a hybrid optical detector, includes the steps of: assembling, via an assembly layer, on the one hand an absorbing structure and on the other hand a read-out circuit, locally etching, through the absorbing structure, the assembly layer and the read-out circuit up to the contacts, so as to form electrical via-holes, depositing a protective layer on the walls of the via-holes, producing a doped region of a second doping type different from the first doping type by diffusing a dopant into the absorbing structure through the protective layer, the region extending annularly around the via-holes so as to form a diode, depositing a metallization layer on the walls of the via-holes allowing the doped region to be electrically connected to the contact.

Claims

1. A process for fabricating a hybrid optical detector comprising the steps of: assembling, via an assembly layer, (i) an absorbing structure (Sabs) that is sensitive in a wavelength band of interest, said structure comprising at least one absorbing layer (AL) made of III-V semiconductor having a first doping type chosen from n or p, and (ii) a read-out circuit (ROIC) comprising a plurality of buried contacts (TLC), the read-out circuit receiving an electrical signal generated from carriers photogenerated by absorption of light by the absorbing semiconductor layer (AL) and, locally etching, through the absorbing structure, the assembly layer and the read-out circuit up to the contacts, so as to form electrical via-holes (IH), depositing a protective layer (PL, PLsca, PLd, PLscna, PLsc0) on the walls of the via-holes, producing a doped region (DZ) of a second doping type different from the first doping type by diffusing a dopant (Dop) into the absorbing structure through said protective layer, said region extending annularly around said via-holes (IH) so as to form a diode (PhD) comprising a p-n junction allowing the photogenerated carriers to be separated and transported, depositing a metallization layer (ML) on the walls of the via-holes (IH) allowing the doped region (DZ) to be electrically connected to the contact (TLC), so as to make an electrical connection between absorbing layer (AL) and read-out circuit (ROIC).

2. The process as claimed in claim 1, further comprising a step of removing said protective layer (PLsca, PLd, PLscna) after the step of producing the doped region and prior to the step (500) of depositing the metallization layer.

3. The process as claimed in claim 2, wherein the protective layer (PLsca) is a layer comprising a semiconductor that is substantially lattice matched with the one or more semiconductors of the absorbing structure, and wherein the protective layer has a defect concentration making said protective layer incompatible with a correct operation of said diode.

4. The process as claimed in claim 3, wherein the method used to deposit the protective layer is an epitaxial method.

5. The process as claimed in claim 2, wherein the protective layer (PLd) is a dielectric layer.

6. The process as claimed in claim 2, wherein the protective layer (PLscna) is a semiconductor layer belonging to a family of materials different from that of the one or more materials of the absorbing structure, said layer then not being lattice matched with the one or more semiconductors of the absorbing structure.

7. The process as claimed in claim 5, wherein the method used to deposit the protective layer is an atomic-layer-deposition (ALD) method.

8. The process as claimed in claim 1, wherein the protective layer is a layer (PLsc0) comprising a semiconductor that is lattice matched with the one or more semiconductors of the absorbing structure and wherein the protective layer has a sufficiently low defect concentration to be compatible with a correct operation of the p-n diode.

9. The process as claimed in claim 1, wherein the via-holes are cylindrical and of square cross section.

10. The process as claimed in claim 9, wherein the via-holes of square cross section are oriented horizontally so as to select two preset crystal planes.

11. The process as claimed in claim 1, wherein the via-holes are conical and of square cross section.

12. The fabricating process as claimed in claim 1, wherein the protective layer has a thickness comprised between 1 and 50 nm.

13. The fabricating process as claimed in claim 1, wherein the protective layer is deposited at a temperature below 450° C.

14. The fabricating process as claimed in claim 1, wherein the dopant is zinc.

15. The process as claimed in claim 1, wherein the III-V material of the absorbing layer is InGaAs having an n first doping type, the absorbing layer being placed between two encapsulating layers made of InP also doped n-type.

16. A hybrid optical detector comprising: an absorbing structure (Sabs) that is sensitive in a wavelength band of interest, said structure comprising at least one absorbing layer (AL) made of III-V semiconductor having a first doping type chosen from n or p, and a read-out circuit (ROIC) comprising a plurality of buried contacts (TLC), the read-out circuit receiving an electrical signal generated from carriers photogenerated by absorption of light by the absorbing semiconductor layer (AL), the absorbing structure and the read-out circuit being assembled via an assembly layer to form the hybrid optical detector, the detector further comprising electrical via-holes (IH) that pass through the absorbing structure, the assembly layer and the read-out circuit (ROIC) up to the contacts (TLC), the absorbing structure comprising a doped region (DZ) of a second doping type different from the first doping type extending annularly around said via-holes (IH), so as to form a diode (PhD) comprising a p-n junction allowing the photogenerated carriers to be separated and transported, the walls of the via-hole facing the doped region (DZ) being covered with a protective layer (PLsc0) made of a semiconductor that is lattice matched with the one or more semiconductors of the absorbing structure, the protective layer being of single-crystal quality, the via-hole walls further being covered with a metallization layer (ML), in order to electrically connect the doped region (DZ) to the contact (TLC), so as to make an electrical connection between absorbing layer (AL) and read-out circuit (ROIC).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other features, aims and advantages of the present invention will become apparent on reading the following detailed description and with reference to the appended drawings, which are given by way of nonlimiting example, and in which:

(2) FIGS. 1a-1b illustrate an optical detector comprising a matrix array of loop-hole photodiodes based on III-V materials.

(3) FIG. 2 illustrates an assembling first step of a process for fabricating the detector 20.

(4) FIG. 3 illustrates a step of depositing and masking a masking dielectric.

(5) FIG. 4 illustrates a step of producing via-holes.

(6) FIG. 5 illustrates a step of producing a doped region around a via-hole.

(7) FIG. 6 illustrates a final step of metallizing the walls of the via-holes.

(8) FIG. 7 illustrates the steps of the process according to the invention.

(9) FIG. 8 illustrates a first variant of the process according to the invention.

(10) FIG. 9 is a graph representing various semiconductor compounds as points, with bandgap on the x-axis and the value in Ångstroms of the lattice constant on the y-axis.

(11) FIG. 10 illustrates a second variant of the process according to the invention, in which the protective layer is a semiconductor layer that is lattice matched with the one or more semiconductors and of crystallographic quality.

(12) FIG. 11 illustrates a variant in which the via-holes of square cross section are oriented horizontally by a defined angle.

(13) FIG. 12 illustrates an embodiment in which the via-holes are of cone shape.

(14) FIG. 13 illustrates a detector according to the invention.

DETAILED DESCRIPTION

(15) The process 700 for fabricating a hybrid optical detector according to invention is illustrated in FIG. 7.

(16) The process comprises a first step 100 consisting in assembling, via an assembly layer 11, on the one hand an absorbing structure Sabs that is sensitive in a wavelength band of interest, and on the other hand a read-out circuit ROIC comprising a plurality of buried contacts TLC. The structure Sabs comprises at least one absorbing layer AL made of III-V semiconductor having a first doping type chosen from n or p. The total thickness of the structure is about a few microns.

(17) The read-out circuit ROIC is intended to receive an electrical signal generated from carriers photogenerated by absorption of light by the absorbing semiconductor layer AL.

(18) It is a question of a step similar to the step described with reference to FIG. 2.

(19) Here, the assembly is preferably achieved by direct bonding. This method consists in specifically preparing the surface of the two structures with deposits of silica and planarization then in bringing them mechanically into contact, then in carrying out a thermal anneal (at about 200° C.).

(20) According to one embodiment, also illustrated in FIG. 7, the absorbing structure Sabs comprises two encapsulating layers EL placed on either side of the absorbing layer AL and having a bandgap of a value higher than the value of the bandgap of the absorbing layer. These layers are also referred to as “window layers” and mainly serve to screen surface states that could generate a parasitic signal.

(21) The window layers must be lattice matched with the absorbing layer. The entirety of the stack Sabs is produced during the same epitaxial growth. For example, the III-V material of the absorbing layer is InGaAs having an n first doping type (which may be intrinsic), the absorbing layer being placed between two encapsulating layers made of InP (which are typically weakly n-doped, i.e. with a concentration between 10.sup.15 and 10.sup.17 cm.sup.−3). Detection in the so-called SWIR range is then obtained (SWIR being the acronym of Short Wavelength InfraRed, this range extending from 0.9 to 1.7 μm).

(22) In a second step 200 local etching is carried out through the absorbing structure Sabs, the assembly layer 11 and the read-out circuit up to the contacts TLC, so as to form electrical via-holes IH. This step is similar to the step described with reference to FIGS. 3 and 4. The diameter of the via-holes is preferably comprised between 1 and 4 μm.

(23) The process according to the invention then comprises a third step 300 consisting in depositing a protective layer PL on the walls of the via-holes IH.

(24) As described below, this protective layer PL may be of various natures.

(25) Next, in a fourth step 400, a doped region DZ of a second doping type different from the first doping type is produced by diffusing, into the absorbing structure, a dopant Dop through the protective layer PL via the holes IH. The doped region DZ extends into the absorbing structure annularly around the holes IH so as to form a loop-hole diode comprising a p-n junction allowing the carriers photogenerated when the detector is illuminated by a light beam to be detected to be separated and transported.

(26) All of the steps, and particularly the step of depositing PL and the diffusing step, must be carried out at a temperature compatible with what the circuit ROIC is able to withstand, i.e. typically a temperature below 400° C.

(27) The layer PL must not be degraded during the diffusion, and allows the constituent layers of the absorbing structure Sabs to be protected during the diffusing step. Preferably, the protective layer is thin, having a thickness comprised between 1 and 50 nm, and more preferably between 1 and 20 nm, because it must allow the dopant Dop to diffuse into the materials of the structure Sabs to be doped.

(28) Furthermore, this layer has an influence on the depth and level of doping of the region DZ, essentially because of the modification that its presence induces in the surface finish of the walls through which the diffusion occurs (vacancy concentration, etc.). In the case of an InP/InGaAs/InP absorbing structure, the protective layer will allow the InP layers, which are degraded by zinc as described above, to be protected.

(29) According to one embodiment, the dopant Dop is zinc, the doping with zinc atoms inducing a doping of p-type.

(30) Lastly, the process according to the invention comprises a step 500 of depositing a metallization layer ML on the walls of the via-holes, allowing the doped region DZ to be electrically connected to the contact TLC, so as to make an electrical connection between absorbing layer AL and read-out circuit ROIC.

(31) The process according to the invention thus allows a hybrid optical detector based on loop-hole photodiodes to be produced while guaranteeing that the diffusing step does not degrade the walls of the holes, leading subsequently to p-n (or n-p) loop-hole diodes that operate correctly. Furthermore, the layer PL acts as a diffusion “engine”, this improving the penetration depth of the atoms of the dopant Dop and increasing the concentration thereof and hence the doping level. This allows the electronic defects induced by the via-hole to be more effectively screened, improving the performance of the detector in terms of parasitic signals.

(32) According to a first variant of the fabricating process according to the invention, the protective layer does not have a sufficient quality to be preserved. According to this variant, the process according to the invention furthermore comprises a step 450 of removing the protective layer PL once the step 400 of diffusing the dopant has been carried out and prior to the step 500 of depositing the metallization layer, such as illustrated in FIG. 8.

(33) The removal is typically achieved by wet or dry (plasma) chemical etching.

(34) According to a first embodiment requiring the removal of the layer PL, the protective layer is a layer PLsca comprising a semiconductor that is substantially lattice matched with the one or more semiconductors from which the absorbing structure is made. This embodiment corresponds to the case where the semiconductor protective layer PL has too high a defect concentration, preventing a transport of carriers compatible with correct operation of the loop-hold diode.

(35) By substantially lattice matched what is meant is a sufficient match to allow use, to deposit the layer PLsca, of an epitaxial method. It may be a question of molecular beam epitaxy (MBE), gas-source molecular beam epitaxy (GSMBE), metalorganic vapor phase epitaxy (MOVPE), hydride vapor phase epitaxy (HVPE), etc.

(36) Typically, the layer PL has a thickness from 1 to 100 nm, and preferably from 1 to 50 nm. This thickness depends on the ease of deposition and the aspect ratio of the via (diameter versus depth).

(37) The layer is preferably localized to the walls of the via corresponding to the edge face of the absorbing structure Sabs, but may potentially form on the edge face of the passivation layer and at the bottom on the contact. There are families of semiconductor compounds having a good lattice match, as illustrated in FIG. 9. FIG. 9 plots the various compounds as points on a graph with bandgap in eV on the x-axis and the value in Angstroms of the lattice constant on the y-axis.

(38) In the case of an InP/InGaAs/InP absorbing structure, the deposition of a protective layer made of Ga.sub.0.47In.sub.0.53As allows such a lattice match.

(39) According to a second embodiment requiring the removal of the layer PL, also illustrated in FIG. 8, the protective layer is a dielectric layer PLd. Typically, the dielectric is chosen from: HfO.sub.2, SiO.sub.2, and Al.sub.2O.sub.3.

(40) The advantage of using a dielectric is that the lattice-match condition is not a constraint and that lower-temperature deposition methods, such as sputtering, evaporation and plasma-phase deposition, may be used. The nature of this layer is very different from that of the absorbing structure, it is easier to remove.

(41) The layer completely covers the walls and bottom of the via.

(42) Preferably, to obtain a very thin deposition of a few nm having a controlled thickness, an atomic layer deposition (ALD) is carried out.

(43) According to a third embodiment, the protective layer is a semiconductor layer PLscna of a family different from that of the absorbing-structure compounds, and is therefore not lattice matched therewith. This layer may also be deposited with a conformal method such as ALD.

(44) Typically, the semiconductor is ZnO or ZnSe—this is an embodiment equivalent to the production with dielectric.

(45) According to a second variant illustrated in FIG. 10, the protective layer is a semiconductor layer PLsc0 that is lattice matched with the one or more semiconductors of the absorbing structure, and that has a sufficiently low defect concentration to allow the transport of the carriers. The layer PLsc0 is thus compatible with correct operation of the p-n loop-hole diode. It is therefore no longer removed.

(46) FIG. 10 illustrates the example of an InP/InGaAs/InP absorbing structure.

(47) This layer is deposited using an epitaxial method in which the control of all of the parameters of the deposition is increased. “Epitaxial regrowth” is spoken of, and the layer PLsc0 is therefore single-crystal.

(48) Because it is a question of epitaxial regrowth, this layer is localized solely to the walls of the via corresponding to the edge face of the layers from which the absorbing layer is made, as illustrated in FIG. 10 by the schematics corresponding to steps 300, 400 and 500.

(49) For an InP/InGaAs/InP structure, this layer is made of Ga.sub.0.47In.sub.0.53As.

(50) This layer is trickier to produce, but has the advantage of being compatible with the operation of the loop-hole diode—there is no need to remove it after the diffusing step. Specifically, it has the same type of doping as Sabs for a given dopant and is electrically conductive, this allowing electrical continuity with the structure.

(51) The metallization layer ML is therefore deposited on top of the epitaxial layer PLsc0, as illustrated in FIG. 10 by the schematic located next to the final step 500.

(52) According to one embodiment, the via-holes are of cylindrical shape and of square cross section. The vertical planar walls of the via-hole IH that result therefrom allow a number of growth directions limited to 2 to be obtained. Thus it becomes simpler to determine the thermodynamic conditions of the epitaxial growth. As a variant, the via-holes of square cross section are oriented horizontally by an angle θ defined so as to select, in the via IH, the crystal planes most suitable for the growth process used, such as illustrated in FIG. 11, which corresponds to a top view of the optical detector. The angle θ is for example measured with respect to the direction D perpendicular to the primary flat. In the case of an absorbing structure made of InP and InGaAs, it is known that an angle of 0° gives the best quality regrowth material.

(53) According to another embodiment, the via-holes are of cone shape, such as illustrated in FIG. 12 for a detector fabricated with a fabricating method according to the first variant (removal of the layer PL). Preferably the vias are of square cross section.

(54) As regards the constituent materials of the (so-called active) absorbing structure, the InP of the wide-bandgap and electron-collecting encapsulating layers may be replaced by InAlSb, GaSb or Al.sub.xGa.sub.(1-x)As.sub.ySb.sub.(1-y). As regards the narrower-bandgap absorbing layer, the InGaAs may be replaced by InSb or InAsSb in order to obtain imagers in MWIR bands.

(55) Other associations of semiconductors are possible, depending on the desired wavelength range of interest. The examples below are given indicatively and non-exhaustively.

(56) TABLE-US-00001 Spectral Wide-bandgap window Narrower-bandgap range of interest layer absorbing layer SWIR InP InGaAs SWIR Si SiGe or Ge MWIR GaSb or InAsSb or InAsSb/InAs Al.sub.xGa.sub.(1−x)As.sub.ySb.sub.(1−y) SRL MWIR InAlSb InSb LWIR GaSb or GaSb/InAs Al.sub.xGa.sub.(1−x)As.sub.ySb.sub.(1−y) SRL UV AlGaN or AlInN GaN or AlGaN

(57) According to another aspect, the invention relates to a hybrid optical detector 30 (illustrated in FIG. 13) comprising: an absorbing structure Sabs that is sensitive in a wavelength band of interest, said structure comprising at least one absorbing layer AL made of III-V semiconductor having a first doping type chosen from n or p, and a read-out circuit ROIC comprising a plurality of buried contacts TLC. The read-out circuit is intended to receive an electrical signal generated from the carriers photogenerated by absorption of light by the absorbing semiconductor layer AL. The absorbing structure and the read-out circuit are assembled via an assembly layer 11 in order to form the hybrid optical detector 30.

(58) The detector 30 furthermore comprises electrical via-holes IH that pass through the absorbing structure Sabs, the assembly layer 11 and the read-out circuit ROIC up to the contacts TLC.

(59) The absorbing structure comprises a region DZ doped a second doping type different from the first doping type, extending annularly around said via-holes IH, so as to form a diode PhD comprising a p-n junction allowing the photogenerated carriers to be separated and transported.

(60) The walls of the via-holes facing the doped region (DZ) are covered with a protective layer (PLsc0) made of a semiconductor that is lattice matched with the one or more semiconductors of the absorbing structure, the protective layer being of crystallographic quality.

(61) The walls of the via-holes are furthermore covered with a metallization layer ML, in order to electrically connect the doped region (DZ) to the contact TLC, so as to make an electrical connection between absorbing layer AL and read-out circuit ROIC.

(62) The detector 30 is the detector produced according to the variant of the fabricating method according to the invention illustrated in FIG. 10. The protective layer PLsc0 is deposited using an epitaxial method on the walls of the doped region.