Ion trap array for high throughput charge detection mass spectrometry

Abstract

An electrostatic linear ion trap (ELIT) array includes multiple elongated charge detection cylinders arranged end-to-end and each defining an axial passageway extending centrally therethrough, a plurality of ion mirror structures each defining a pair of axially aligned cavities and an axial passageway extending centrally therethrough, wherein a different ion mirror structure is disposed between opposing ends of each cylinder, and front and rear ion mirrors each defining at least one cavity and an axial passageway extending centrally therethrough, the front ion mirror positioned at one end of the arrangement of charge detection cylinders and the rear ion mirror positioned at an opposite end of the arrangement of charge detection cylinders, wherein the axial passageways of the charge detection cylinders, the ion mirror structures, the front ion mirror and the rear ion mirror are coaxial to define a longitudinal axis passing centrally through the ELIT array. In a second aspect, an ELIT array comprises a plurality of non-coaxial ELIT regions, wherein ions are selectively guided into each of the ELIT regions.

Claims

1. An electrostatic linear ion trap (ELIT) array, comprising: a plurality of elongated charge detection cylinders arranged end-to-end and each defining an axial passageway extending centrally therethrough, a plurality of ion mirror structures each defining a pair of axially aligned cavities and each defining an axial passageway therethrough extending centrally through both cavities, wherein a different one of the plurality of ion mirror structures is disposed between opposing ends of each arranged pair of the elongated detection cylinders, and front and rear ion mirrors each defining at least one cavity and an axial passageway extending centrally therethrough, the front ion mirror positioned at one end of the plurality of charge detection cylinders and the rear ion mirror positioned at an opposite end of the plurality of charge detection cylinders, wherein the axial passageways of the plurality of charge detection cylinders, the plurality of ion mirror structures, the front ion mirror and the rear ion mirror are axially aligned with one another to define a longitudinal axis passing centrally through the ELIT array.

2. The ELIT array of claim 1, wherein each of the plurality of ion mirror structures comprise a single ion mirror defining a single cavity, a first aperture at one end of the ion mirror open to the single cavity, a second aperture at an opposite end of the ion mirror and open to the single cavity, and a plate or ring positioned centrally with the single cavity and axially bisecting the single cavity into the pair of axially aligned cavities, the plate or ring defining a third aperture therethrough and open to both of the axially aligned cavities, and wherein the longitudinal axis of the ELIT array extends centrally through first aperture, the second aperture, third aperture and the pair of axially aligned cavities of each of the plurality of ion mirror structures.

3. The ELIT array of any of claim 1, wherein the front ion mirror defines a single cavity, a first aperture at one end of the front ion mirror open to the single cavity of the front ion mirror and a second aperture at an opposite end of the front ion mirror and open to the single cavity of the front ion mirror, and wherein the longitudinal axis of the ELIT array extends centrally through the first and second apertures and through the single cavity of the front ion mirror, and wherein the first aperture of the front ion mirror defines an ion inlet to the ELIT array and the second aperture of the front ion mirror is positioned opposite to an exposed end of the one of the plurality of charge detection cylinders at the one end of the plurality of charge detection cylinders.

4. The ELIT array of claim 1, wherein the rear ion mirror defines a single cavity, a first aperture at one end of the rear ion mirror open to the single cavity of the rear ion mirror and a second aperture at an opposite end of the rear ion mirror and open to the single cavity of the rear ion mirror, and wherein the longitudinal axis of the ELIT array extends centrally through first and second apertures and through single cavity of the rear ion mirror, and wherein the first aperture of the rear ion mirror is positioned opposite to an exposed end of the one of the plurality of charge detection cylinders at the opposite end of the plurality of charge detection cylinders and the second aperture of the rear ion mirror defines an ion outlet of the ELIT array.

5. The ELIT array of claim 1, further comprising at least one voltage source operatively coupled to each of the front ion mirror, the rear ion mirror and the plurality of ion mirror structures and configured to produce voltages for selectively establishing an ion transmission electric field or an ion reflection electric field therein, the ion transmission electric field configured to focus an ion passing through a respective one of the front ion mirror, the rear ion mirror and the plurality of ion mirror structures toward the longitudinal axis and the ion reflection electric field configured to cause an ion entering a respective one of the front ion mirror, the rear ion mirror and the plurality of ion mirror structures from a respective one of the plurality of charge detection cylinders to stop and accelerate in an opposite direction back through the respective one of the plurality of charge detection cylinders while also focusing the ion toward the longitudinal axis.

6. The ELIT array of claim 5, further comprising: a processor operatively coupled to the at least one voltage source, and a memory having instructions stored therein which, when executed by the processor, cause the processor to control the at least one voltage source to establish an ion transmission field with the cavities of each of the front ion mirror, the rear ion mirror and the plurality of ion mirror structures such that ions entering the front ion mirror pass through each of the front ion mirror, the rear ion mirror, each of the plurality of ion mirror structures and each of the plurality of charge detection cylinders and exit the ELIT array.

7. The ELIT array of claim 6, wherein the instructions stored in the memory further include instructions which, when executed by the processor, cause the processor to control the at least one voltage source to establish the ion reflection field with the at least one cavity of the rear ion mirror while maintaining the ion transmission electric field in the cavities of the front ion mirror and the plurality of ion mirror structures.

8. The ELIT array of claim 7, wherein the ELIT defines a plurality of axially aligned ELIT regions each including a different one of the plurality of charge detection cylinders and cavities of respective ones of the front ion mirror, the rear ion mirror and the plurality of ion mirror structures positioned at opposite ends thereof, and wherein the instructions stored in the memory further include instructions which, when executed by the processor, cause the processor to control the at least one voltage source to sequentially establish the ion reflection field with the cavities each of the plurality of ion mirror structures, beginning with the one of the plurality of ion mirror structures positioned at the opposite end of the one of the plurality of cylinders disposed between the rear ion mirror and the one of the plurality of ion mirror structures, while maintaining the ion transmission electric field in the cavities of the front ion mirror and each of the remaining plurality of ion mirror structures, followed by controlling the at least one voltage source to establish the ion reflection field with the at least one cavity of the front ion mirror, in a manner which successively traps a different one of the ions entering the front ion mirror in each of the plurality of ELIT regions such that an ion trapped within each of the plurality of ELIT regions oscillates back and forth between the cavities of the respective ones of the front ion mirror, the rear ion mirror and the plurality of ion mirror structures each time passing through a respective one of the plurality of charge detection cylinders.

9. The ELIT array of claim 8, further comprising a plurality of charge preamplifiers each having an input operatively coupled to a different one of the plurality of charge detection cylinders and each having an output operatively coupled to the processor, each of the plurality of charge preamplifiers configured to produce charge detection signals upon detection of a charge induced on the respective one of the plurality of charge detection cylinders as a respective ion passes therethrough, and wherein the instructions stored in the memory further include instructions which, when executed by the processor, cause the processor to record the charge detection signals produced by each of the plurality of charge preamplifiers.

10. The ELIT array of claim 9, wherein the instructions stored in the memory further include instructions which, when executed by the processor, cause the processor to control the at least one voltage source to trap one of the ions entering the front ion mirror in any of the plurality of ELIT regions by controlling the at least one voltage source to establish the ion reflection electric field in the cavity of a corresponding upstream one of the front ion mirror and the plurality of ion mirror structures upon detection of a charge detection signal produced by a respective one of the plurality of charge preamplifiers.

11. The ELIT array of claim 9, wherein the instructions stored in the memory further include instructions which, when executed by the processor, cause the processor to determine a respective ion charge and at least one of an ion mass-to-charge ratio and an ion mass based on the recorded charge detection signals produced by each of the plurality of charge preamplifiers.

12. The ELIT array of claim 8, wherein the instructions stored in the memory further include instructions which, when executed by the processor, cause the processor to control the at least one voltage source to trap one of the ions entering the front ion mirror in any of the plurality of ELIT regions by controlling the at least one voltage source to establish the ion reflection electric field in the cavity of a corresponding upstream one of the front ion mirror and the plurality of ion mirror structures after a time delay has elapsed since controlling the at least one voltage source to establish the ion reflection electric field in the cavity of a corresponding downstream one of the rear ion mirror and the plurality of ion mirror structures.

13. A charge detection mass spectrometer (CDMS), comprising: a source of ions configured to generate and supply ions, an electrostatic linear ion trap (ELIT) array of claim 8, the ELIT array configured to receive at least some of the ions supplied by the source of ions, and means for controlling each of the plurality of ion mirrors to trap a different one of the ions supplied by the source of ions in each of the plurality of ELIT regions and to cause the ion trapped in each of the plurality of ELIT regions to oscillate back and forth between the respective pair of the plurality of ion mirrors each time passing through a respective one of the plurality of charge detection cylinders.

14. The CDMS of claim 13, wherein the ELIT regions are arranged in line with one another such that the axial passageways of the plurality of ion mirrors and the axial passageways of the plurality of charge detection cylinders are coaxial and such that a longitudinal axis extending through the ELIT array extends centrally through each of the passageways of each of the plurality of ion mirrors and each of the plurality of charge detection cylinders, and wherein the means for controlling each of the plurality of ion mirrors includes means for guiding the ions supplied by the source of ions into and through the axially aligned passageways of each of the plurality of ELIT regions of the ELIT.

15. The CDMS of claim 13, wherein the axial passageways of at least one of the plurality of ELIT regions are not aligned with the axial passageways of at least another of the plurality of ELIT regions, and further comprising means for selectively guiding ions supplied by the ion source into each of the ELIT regions.

16. The CDMS of claim 13, further comprising: a plurality of charge preamplifiers each having an input coupled to a respective one of the plurality of charge detection cylinders and an output, each of the plurality of charge preamplifiers configured to produce a charge detection signal at the output thereof upon detection at the respective input of a charge induced on the respective one of the plurality of charge detection cylinders resulting from passage of an ion axially therethrough, a processor operatively coupled to the output of each of the plurality of charge preamplifiers, and a memory having instructions stored therein which, when executed by the processor, cause the processor to monitor the outputs of the plurality of charge preamplifiers and to record in the memory a plurality of sets of charge detection signals each containing recorded charge detection signals produced by a different one of the plurality of charge preamplifiers, wherein the instructions stored in the memory include instructions which, when executed by the processor, cause the processor to process the plurality of sets of recorded charge detection signals to determine a corresponding plurality of ion charge values and associated ion mass-to-charge ratio or mass values.

17. A system for separating ions comprising: an ion source configured to generate ions from a sample, at least one ion separation instrument configured to separate the generated ions as a function of at least one molecular characteristic, and the ELIT array of claim 1, wherein ions exiting the at least one ion separation instrument pass into the ELIT array via the front ion mirror.

18. A system for separating ions comprising: an ion source configured to generate ions from a sample, a first mass spectrometer configured to separate the generated ions as a function of mass-to-charge ratio, an ion dissociation stage positioned to receive ions exiting the first mass spectrometer and configured to dissociate ions exiting the first mass spectrometer, a second mass spectrometer configured to separate dissociated ions exiting the ion dissociation stage as a function of mass-to-charge ratio, and a charge detection mass spectrometer (CDMS), including the ELIT array of claim 1, coupled in parallel with and to the ion dissociation stage such that the CDMS can receive ions exiting either of the first mass spectrometer and the ion dissociation stage, wherein masses of precursor ions exiting the first mass spectrometer are measured using the CDMS, mass-to-charge ratios of dissociated ions of precursor ions having mass values below a threshold mass are measured using the second mass spectrometer, and mass-to-charge ratios and charge values of dissociated ions of precursor ions having mass values at or above the threshold mass are measured using the CDMS.

19. A method of measuring ions supplied to an ion inlet of an electrostatic linear ion trap (ELIT) array having a plurality of ion mirrors and a plurality of elongated charge detection cylinders each defining a respective axial passageway therethrough, wherein the plurality of charge detection cylinders are arranged end-to-end in cascaded relationship with a different one of the plurality of ion mirrors positioned between each arranged pair of the elongated charge detection cylinders and with first and last ones of the plurality of ion mirrors positioned at respective opposite ends of the cascaded arrangement, wherein the first and last ion mirrors define the ion inlet and an ion exit of the ELIT array respectively, and wherein the axial passageways of each of the plurality of ion mirrors and charge detection cylinders are collinear with one another and define a longitudinal axis centrally therethrough to form a sequence of axially aligned ELIT regions each defined by a combination of one of the plurality of charge detection cylinders and a respective pair of the plurality of ion mirrors at each end thereof, the method comprising: controlling at least one voltage source to apply voltages to each of the plurality of ion mirrors to establish an ion transmission electric field therein to pass the ions entering the ion inlet of the ELIT through each of the plurality of ion mirrors and charge detection cylinders and the ion exit of the ELIT array, wherein each ion transmission field is configured to focus ions passing therethrough toward the longitudinal axis, and controlling the at least one voltage source to sequentially modify the voltages applied to each the plurality of ion mirrors while maintaining previously applied voltages to remaining ones of the plurality of ion mirrors, beginning with the last ion mirror and ending with the first ion mirror, to sequentially establish an ion reflection electric field in each of the plurality of ion mirrors in a manner that sequentially traps a different ion in each of the ELIT regions, wherein each ion reflection electric field is configured to cause an ion entering a respective ion mirror from an adjacent one of the plurality of charge detection cylinders to stop and accelerate in an opposite direction back through the respective one of the plurality of charge detection cylinders, wherein the ion trapped in each respective ELIT region oscillates back and forth between the respective ones of the plurality of ion mirrors, under the influence of the ion reflection electric fields established therein, each time passing through a respective one of the plurality of charge detection cylinders and inducing a corresponding charge thereon, detecting the charge induced on each of the plurality of charge detection cylinders by a respective trapped ion with each pass therethrough, and recording in a memory the charges induced on each of the plurality of charge detection cylinders by a respective trapped ion over a duration of a respective charge measurement event, wherein each charge measurement event has a duration defined by one of a passage of a predefined period of time and a predefined number of passes of the respective ion through the respective charge detection cylinder.

20. The method of claim 19, further comprising determining an ion charge and at least one of an ion mass-to-charge ratio and an ion mass based on the recorded charges for each of the ELIT regions.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a simplified diagram of an ion mass detection system including an embodiment of an electrostatic linear ion trap (ELIT) array with control and measurement components coupled thereto.

(2) FIG. 2A is a magnified view of an example one of the ion mirrors of the ELIT array illustrated in FIG. 1 in which the mirror electrodes are controlled to produce an ion transmission electric field within the example ion mirror.

(3) FIG. 2B is a magnified view of another example one of the ion mirrors of the ELIT array illustrated in FIG. 1 in which the mirror electrodes are controlled to produce an ion reflection electric field within the example ion mirror.

(4) FIG. 3 is a simplified flowchart illustrating an embodiment of a process for controlling operation of the ELIT array of FIG. 1 to determine ion mass and charge information.

(5) FIGS. 4A-4E are simplified diagrams of the ELIT array of FIG. 1 demonstrating sequential control and operation of the multiple ion mirrors according to the process illustrated in FIG. 3.

(6) FIG. 5A is a simplified block diagram of an embodiment of an ion separation instrument including any of the ELIT arrays illustrated and described herein and showing example ion processing instruments which may form part of the ion source upstream of the ELIT array(s) and/or which may be disposed downstream of the ELIT array(s) to further process ion(s) exiting the ELIT array(s).

(7) FIG. 5B is a simplified block diagram of another embodiment of an ion separation instrument including any of the ELIT arrays illustrated and described herein and showing example implementation which combines conventional ion processing instruments with any of the embodiments of the ion mass detection system illustrated and described herein.

(8) FIG. 6 is a simplified diagram of an ion mass detection system including another embodiment of an electrostatic linear ion trap (ELIT) array with control and measurement components coupled thereto.

(9) FIG. 7A is a simplified perspective view of an example embodiment of a single ion steering channel that may be implemented in the ion steering channel array illustrated in FIG. 6.

(10) FIG. 7B is a simplified perspective diagram illustrating an example operating mode of the ion steering channel illustrated in FIG. 7A.

(11) FIG. 7C is a simplified perspective diagram illustrating another example operating mode of the ion steering channel illustrated in FIG. 7A.

(12) FIGS. 8A-8F are simplified diagrams of the ELIT array of FIG. 6 demonstrating example control and operation of the ion steering channel array and of the ELIT array.

(13) FIG. 9 is a simplified diagram of an ion mass detection system including yet another embodiment of an electrostatic linear ion trap (ELIT) array with control and measurement components coupled thereto.

DESCRIPTION OF THE ILLUSTRATIVE EMBODIMENTS

(14) For the purposes of promoting an understanding of the principles of this disclosure, reference will now be made to a number of illustrative embodiments shown in the attached drawings and specific language will be used to describe the same.

(15) This disclosure relates to an electrostatic linear ion trap (ELIT) array including two or more ELITs or ELIT regions and means for controlling them such that at least two of the ELITs or ELIT regions simultaneously operate to measure a mass-to-charge ratio and a charge of an ion trapped therein. In this manner, the rate of ion measurement is increased by at a factor of two or more as compared with conventional single ELIT systems, and a corresponding reduction in total ion measurement time is realized. In some embodiments, an example of which will be described in detail below with respect to FIGS. 1-4E, an ELIT array may be implemented in the form of two or more ELIT regions arranged in series, i.e., cascaded and axially aligned, and ion mirrors at opposite ends of each of the two or more cascaded ELITs or ELIT regions are controlled in a manner which sequentially traps an ion in each ELIT or ELIT region and which causes each of the trapped ions to oscillate back and forth through a respective charge detector positioned within the respective ELIT or ELIT region to measure the mass-to-charge ratios and charges of the trapped ions. In other embodiments, as will be described in detail below with respect to FIGS. 6-10, an ELIT array may be implemented in the form of two or more ELITs arranged in parallel relative to one another. An ion steering array may be controlled to direct ions sequentially or simultaneously into each of the parallel-arranged ELITs, after which the two or more ELITs are controlled in a manner which causes the ions trapped therein to oscillate back and forth through a charge detector thereof to measure the mass-to-charge ratios and charges of the trapped ions.

(16) Referring to FIG. 1, charge detection mass spectrometer (CDMS) 10 is shown including an embodiment of an electrostatic linear ion trap (ELIT) array 14 with control and measurement components coupled thereto. In the illustrated embodiment, the CDMS 10 includes an ion source 12 operatively coupled to an inlet of the ELIT array 14. As will be described with respect to FIG. 5, the ion source 12 illustratively includes any conventional device or apparatus for generating ions from a sample and may further include one or more devices and/or instruments for separating, collecting, filtering, fragmenting and/or normalizing ions according to one or more molecular characteristics. As one illustrative example, which should not be considered to be limiting in any way, the ion source 12 may include a conventional electrospray ionization source, a matrix-assisted laser desorption ionization (MALDI) source or the like, coupled to an inlet of a conventional mass spectrometer. The mass spectrometer may be of any conventional design including, for example, but not limited to a time-of-flight (TOF) mass spectrometer, a reflectron mass spectrometer, a Fourier transform ion cyclotron resonance (FTICR) mass spectrometer, a quadrupole mass spectrometer, a triple quadrupole mass spectrometer, a magnetic sector mass spectrometer, or the like. In any case, the ion outlet of the mass spectrometer is operatively coupled to an ion inlet of the ELIT array 14. The sample from which the ions are generated may be any biological or other material.

(17) In the embodiment illustrated in FIG. 1, the ELIT array 14 is illustratively provided in the form of a cascaded, i.e., series or end-to-end, arrangement of three ELITs or ELIT regions. Three separate charge detectors CD1, CD2, CD3, are each surrounded by a respective ground cylinder GC1-GC3 and are operatively coupled together by opposing ion mirrors. A first or front ion mirror M1 is operatively positioned between the ion source 12 and one end of the charge detector CD1, a second ion mirror M2 is operatively positioned between the opposite end of the charge detector CD1 and one end of the charge detector CD2, a third ion mirror M3 is operatively positioned between the opposite end of the charge detector CD2 and one end of the charge detector CD3, and a fourth or rear ion mirror is operatively positioned at the opposite end of the charge detector CD3. In the illustrated embodiment, each of the ion mirrors M1-M3 define axially aligned and adjacent but oppositely-facing ion mirror regions or cavities R1, R2 separated from one another by a plate, ring or grid defining an aperture therethrough, and the ion mirror M4 illustratively defines a single ion mirror region or cavity R1. In some alternate embodiments, the ion mirror M4 may be identical to the ion mirrors M1-M3, i.e., the ion mirror M4 may define axially aligned and adjacent but oppositely-facing ion mirror regions R1, R. Alternatively or additionally, the ion mirror M1 may be provided in the form of a single region ion mirror, e.g., the region R2.

(18) In the illustrated embodiment, the region or cavity R2 of the first ion mirror M1, the charge detector CD1, the region or cavity R1 of the second ion mirror M2 and the spaces between CD1 and the ion mirrors M1, M2 together define a first ELIT or ELIT region E1 of the ELIT array 14, the region or cavity R2 of the second ion mirror M2, the charge detector CD2, the region or cavity R1 of the third ion mirror M3 and the spaces between CD2 and the ion mirrors M2, M3 together define a second ELIT or ELIT region E2 of the ELIT array 14, and the region or cavity R2 of the third ion mirror M3, the charge detector CD3, the region or cavity R1 of the ion mirror M4 and the spaces between CD3 and the mirror electrodes M3, M4 together define a third ELIT or ELIT region E3 of the ELIT array 14. It will be understood that in some alternate embodiments, the ELIT array 14 may include fewer cascaded ELITs or ELIT regions, e.g., two cascaded ELITs or ELIT regions, and that in other alternate embodiments the ELIT array 14 may include more cascaded ELITs or ELIT regions, e.g., four or more cascaded ELITs or ELIT regions. The construction and operation of any such alternate ELIT array 14 will generally follow that of the embodiment illustrated in FIGS. 1-4E and described below.

(19) In the illustrated embodiment, four corresponding voltage sources V1-V4 are electrically connected to the ion mirrors M1-M4 respectively. Each voltage source V1-V4 illustratively includes one or more switchable DC voltage sources which may be controlled or programmed to selectively produce a number, N, of programmable or controllable voltages, wherein N may be any positive integer. Illustrative examples of such voltages will be described below with respect to FIGS. 2A and 2B to separately and/or together establish one of two different operating modes of each ion mirror M1-M4 as will be described in detail below. In any case, a longitudinal axis 24 extends centrally through each of the charge detectors CD1-CD3 and the regions or cavities R1, R2 of each of the ion mirrors M1-M4 (and passing centrally through each of the apertures defined in and through each of the ion mirrors M1-M4), and the central axis 24 defines an ideal travel path along which ions move within the ELIT array 14 and portions thereof under the influence of electric fields selectively established by the voltage sources V1-V4.

(20) The voltage sources V1-V4 are illustratively shown electrically connected by a number, P, of signal paths to a conventional processor 16 including a memory 18 having instructions stored therein which, when executed by the processor 16, cause the processor 16 to control the voltage sources V1-V4 to produce desired DC output voltages for selectively establishing electric fields within the ion mirror regions or cavities R1, R2 of the respective ion mirrors M1-M4. P may be any positive integer. In some alternative embodiments, one or more of the voltage sources V1-V4 may be programmable to selectively produce one or more constant output voltages. In other alternative embodiments, one or more of the voltage sources V1-V4 may be configured to produce one or more time-varying output voltages of any desired shape. It will be understood that more or fewer voltage sources may be electrically connected to the mirror electrodes M1-M4 in alternate embodiments.

(21) Each charge detector CD1-CD3 is electrically connected to a signal input of a corresponding one of three charge sensitive preamplifiers CP1-CP3, and the signal outputs of each charge preamplifier CP1-CP3 is electrically connected to the processor 16. The charge preamplifiers CP1-CP3 are each illustratively operable in a conventional manner to receive detection signals detected by a respective one of the charge detectors CD1-CD3, to produce charge detection signals corresponding thereto and to supply the charge detection signals to the processor 16. The processor 16 is, in turn, illustratively operable to receive and digitize the charge detection signals produced by each of the charge preamplifiers CP1-CP3, and to store the digitized charge detection signals in the memory 18. The processor 16 is further illustratively coupled to one or more peripheral devices 20 (PD) for providing signal input(s) to the processor 16 and/or to which the processor 16 provides signal output(s). In some embodiments, the peripheral devices 20 include at least one of a conventional display monitor, a printer and/or other output device, and in such embodiments the memory 18 has instructions stored therein which, when executed by the processor 16, cause the processor 16 to control one or more such output peripheral devices 20 to display and/or record analyses of the stored, digitized charge detection signals. In some embodiments, a conventional microchannel plate (MP) detector 22 may be disposed at the ion outlet of the ELIT array 14, i.e., at the ion outlet of the ion mirror M4, and electrically connected to the processor 16. In such embodiments, the microchannel plate detector 22 is operable to supply detection signals to the processor 16 corresponding to detected ions and/or neutrals.

(22) As will be described in greater detail below, the voltage sources V1-V4 are illustratively controlled in a manner which selectively and successively guides ions entering the ELIT array 14 from the ion source 12 into each of the three separate ELITs or ELIT regions E1-E3 such that a different ion is trapped in each of the three regions E1-E3 and oscillates therein between respective ones of the ion mirrors M1-M4 each time passing through a respective one of the charge detectors CD1-CD3. A plurality of charge and oscillation period values are measured at each charge detector CD1-CD3, and the recorded results are processed to determine charge, mass-to-charge ratio and mass values of the ions in each of the three ELITs or ELIT regions E1-E3. Depending upon a number of factors including, but not limited to, the dimensions of the three ELITs or ELIT regions E1-E3, the ion oscillation frequency and the resident times of the ions within each of the three ELITs or ELIT regions E1-E3, the trapped ions oscillate simultaneously within at least two of the three ELITs or ELIT regions E1-E3, and in typical implementations within each of the three of the ELITs or ELIT regions E1-E3, such that ion charge and mass-to-charge ratio measurements can be collected simultaneously from at least two of the three ELITs or ELIT regions E1-E3.

(23) Referring now to FIGS. 2A and 2B, an embodiment is shown of one of the ion mirrors MX of the ELIT array 14 of FIG. 1, where X=1-4, illustrating example construction and operation thereof. In each of FIGS. 2A and 2B, the illustrated ion mirror MX includes a cascaded arrangement of 7 axially spaced-apart, electrically conductive mirror electrodes. For each of the ion mirrors M2-M4, a first electrode 30.sub.1 is formed by the ground cylinder, GC.sub.X-1, disposed about a respective one of the charge detectors CD.sub.X-1. The first electrode 30.sub.1 of the ion mirror M1, on the other hand, is formed by an ion outlet of the ion source 12 (IS) or as part of an ion focusing or transition stage between the ion source 12 and the ELIT array 14. FIG. 2B illustrates the former and FIG. 2A illustrates the latter. In either case, the first mirror electrode 30.sub.1 defines an aperture A1 centrally therethrough which serves as an ion entrance and/or exit to and/or from the corresponding ion mirror MX. The aperture A1 of the first electrode 30.sub.1 of the ion mirror M1 illustratively serves as the ion inlet to the ELIT array 14. The aperture A1 is illustratively conical in shape which increases linearly between the internal and external faces of GC.sub.X-1 or IS from a first diameter P1 defined at the internal face of GC.sub.X-1 or IS to an expanded diameter P2 at the external face of GC.sub.X-1 or IS. The first mirror electrode 30.sub.1 illustratively has a thickness of D1.

(24) A second mirror electrode 30.sub.2 of the ion mirror MX is spaced apart from the first mirror electrode 30.sub.1 and defines a passageway therethrough of diameter P2. A third mirror electrode 30.sub.3 is spaced apart from the second mirror electrode 30.sub.2 and likewise defines a passageway therethrough of diameter P2. The second and third mirror electrodes 30.sub.2, 30.sub.3 illustratively have equal thickness of D2≥D1. A fourth mirror electrode 30.sub.4 is spaced apart from the third mirror electrode 30.sub.3. The fourth mirror electrode 30.sub.4 defines a passageway therethrough of diameter P2 and illustratively has a thickness D3 of between approximately 2D2 and 3D2. A plate, ring or grid 30A is illustratively positioned centrally within the passageway of the fourth mirror electrode 30.sub.4 and defines a central aperture CA therethrough having a diameter P3. In the illustrated embodiment, P3<P1 although in other embodiments P3 may be greater than or equal to P1. A fifth mirror electrode 30.sub.5 is spaced apart from the fourth mirror electrode 30.sub.4, and a sixth mirror electrode 30.sub.6 is spaced apart from the fifth mirror electrode 30.sub.5. Illustratively, the fifth and sixth mirror electrodes 30.sub.5, 30.sub.6 are identical to the third and second mirror electrodes 30.sub.3, 30.sub.2 respectively.

(25) For each of the ion mirrors M1-M3, a seventh mirror electrode 30.sub.7 is formed by the ground cylinder, GC.sub.X, disposed about a respective one of the charge detectors CD.sub.X. The seventh electrode 30.sub.7 of the ion mirror M4, on the other hand, may be a stand-alone electrode since the ion mirror M4 is the last in the sequence. In either case, the seventh mirror electrode 30.sub.7 defines an aperture A2 centrally therethrough which serves as an ion entrance and/or exit to and/or from the ion mirror MX. The aperture A2 is illustratively the mirror image of the aperture A1, and is of a conical shape which decreases linearly between the external and internal faces of GC.sub.X from expanded diameter P2 defined at the external face of GC.sub.X to the reduced diameter P1 at the internal face of GC.sub.X. The seventh mirror electrode 30.sub.7 illustratively has a thickness of D1. In some embodiments, as illustrated by example in FIG. 1, the last ion mirror in the sequence, i.e., M4 in FIG. 1, may terminate at the plate or grid 30A such that M4 includes only the mirror electrodes 30.sub.1-30.sub.3 and only part of the mirror electrode 30.sub.4 including the plate or grid 30A so that M4 includes only the ion mirror region R1 depicted in FIGS. 2A and 2B. In such embodiments, the central aperture CA of M4 defines an ion exit passageway from the ELIT array 14. Similarly, the first ion mirror in the sequence, i.e., M1 in FIG. 1, may, in some embodiments, terminate at the plate or grid 30A such that M1 includes only the mirror electrodes the mirror electrodes 30.sub.5-30.sub.7 and only part of the mirror electrode 30.sub.4 including the plate or grid 30A so that M4 includes only the ion mirror region R2 depicted in FIGS. 2A and 2B. In such embodiments, the central aperture CA of M1 defines the ion inlet to the ELIT array 14.

(26) The mirror electrodes 30.sub.1-30.sub.7 are illustratively equally spaced apart from one another by a space S1. Such spaces S1 between the mirror electrodes 30.sub.1-30.sub.7 may be voids in some embodiments, i.e., vacuum gaps, and in other embodiments such spaces S1 may be filled with one or more electrically non-conductive, e.g., dielectric, materials. The mirror electrodes 30.sub.1-30.sub.7 are axially aligned, i.e., collinear, such that a longitudinal axis 24 passes centrally through each aligned passageway and also centrally through the apertures A1, A2 and CA. In embodiments in which the spaces S1 include one or more electrically non-conductive materials, such materials will likewise define respective passageways therethrough which are axially aligned, i.e., collinear, with the passageways defined through the mirror electrodes 30.sub.1-30.sub.7 and which have diameters of P2 or greater.

(27) In each of the ion mirrors M1-M4, the region R1 is defined between the aperture A1 of the mirror electrode 30.sub.1 and the central aperture CA defined through the plate or grid 30A. In each of the ion mirrors M1-M3, the adjacent region R2 is defined between the central aperture CA defined through the plate or grid 30A and the aperture A2 of the mirror electrode 30.sub.7. In the illustrated embodiment, the ion mirrors M1-M3 are each shown in the form of a single mirror structure defining two adjacent and opposed, i.e., back-to-back, and axially aligned ion mirror regions R1, R2 separated by a plate 30A defining an aperture CA centrally therethrough. In some alternate embodiments, one or more of the ion mirrors M1-M3 (and/or M4 in embodiments in which M4 is configured identically to M1-M3), may instead be implemented as separate, axially aligned ion mirror structures arranged back-to-back relative to one another and spaced apart from one another by a conventional, electrically non-conductive spacer, e.g., an electrically insulating plate or ring. In some such embodiments, the separate, back-to-back ion mirror structures may be coupled together, i.e., affixed or mounted to one another, and in other embodiments such structures may be spaced apart from one another but not physically coupled together. In one illustrative example of this alternate embodiment using selected parts of the ion mirror structures illustrated in FIGS. 2A and 2B as example components, the ion mirror defining R1 may include the mirror electrodes 30.sub.1-30.sub.3, one transverse half of the mirror electrode 30.sub.4 adjacent to the mirror electrode 30.sub.3 and the plate, ring or grid 30A modified to be secured to the exposed end of the mirror electrode 30.sub.4 such that the longitudinal axis 24 passes through the aperture CA. The oppositely-facing ion mirror defining R2 may similarly include the mirror electrodes 30.sub.5-30.sub.7, one transverse half of the mirror electrode 30.sub.4 adjacent to the mirror electrode 30.sub.5 and the plate, ring or grid 30A modified to be secured to the exposed end of the mirror electrode 30.sub.5 such that the longitudinal axis 24 passes through the aperture CA. Those skilled in the art will recognize other ion mirror designs which may be used and which define R1 and R2 in a single structure or in separate structures, and it will be understood that any such alternate ion mirror designs are intended to fall within the scope of this disclosure.

(28) Within each ELIT or ELIT region E1-E3, a respective charge detector CD1-CD3, each in the form of an elongated, electrically conductive cylinder, is positioned and spaced apart between corresponding ones of the ion mirrors M1-M4 by a space S2. Illustratively, S2>S1, although in alternate embodiments S2 may be less than or equal to S2. In any case, each charge detection cylinder CD1-CD3 illustratively defines a passageway axially therethrough of diameter P4, and each charge detection cylinder CD1-CD3 is oriented relative to the ion mirrors M1-M4 such that the longitudinal axis 24 extends centrally through the passageway thereof. In the illustrated embodiment, P1<P4<P2, although in other embodiments the diameter of P4 may be less than or equal to P1, or greater than or equal to P2. Each charge detection cylinder CD1-CD3 is illustratively disposed within a field-free region of a respective one of the ground cylinders GC1-GC3, and each ground cylinder GC1-GC3 is positioned between and forms part of respective ones of the ion mirrors M1-M4 as described above. In operation, the ground cylinders GC1-G3 are illustratively controlled to ground potential such that the first and seventh electrodes 30.sub.1, 30.sub.7 are at ground potential at all times. In some alternate embodiments, either or both of first and seventh electrodes 30.sub.1, 30.sub.7 in one or more of the ion mirrors M1-M4 may be set to any desired DC reference potential, and in other alternate embodiments either or both of first and seventh electrodes 30.sub.1, 30.sub.7 in one or more of the ion mirrors M1-M4 may be electrically connected to a switchable DC or other time-varying voltage source.

(29) As briefly described above, the voltage sources V1-V4 are illustratively controlled in a manner which causes ions entering into the ELIT array 14 from the ion source 12 to be selectively trapped within each of the ELITs or ELIT regions E1-E3. More specifically, the voltage sources V1-V4 are controlled in a manner which sequentially traps an ion in each ELIT or ELIT region illustratively beginning with E3 and ending with E1, and which causes each trapped ion to oscillate within a respective one of the ELITs or ELIT regions E1-E3 between respective ones of the ion mirrors M1-M4. Each such trapped, oscillating ion thus repeatedly passes through a respective one of the charge detectors CD1-CD3 in a respective one of the three ELITs or ELIT regions E1-E3, and charge and oscillation period values are measured and recorded at each charge detector CD1-CD3 each time a respective oscillating ion passes therethrough. The measurements are recorded and the recorded results are processed to determine charge, mass-to-charge ratio and mass values of each of the three ions.

(30) Within each ELIT or ELIT region E1-E3 of the ELIT array 14, an ion is captured and made to oscillate between opposed regions of the respective ion mirrors M1-M4 by controlling the voltage sources V1-V4 to selectively establish ion transmission and ion reflection electric fields within the regions R1, R2 of the ion mirrors M1-M4. In this regard, each voltage source VX is illustratively configured in one embodiment to produce seven DC voltages DC1-DC7, and to supply each of the voltages DC1-DC7 to a respective one of the mirror electrodes 30.sub.1-30.sub.7 of the respective ion mirror MX. In some embodiments in which one or more of the mirror electrodes 30.sub.1-30.sub.7 is to be held at ground potential at all times, the one or more such mirror electrodes 30.sub.1-30.sub.7 may alternatively be electrically connected to the ground reference of the voltage supply VX and the corresponding one or more voltage outputs DC1-DC7 may be omitted. Alternatively or additionally, in embodiments in which any two or more of the mirror electrodes 30.sub.1-30.sub.7 are to be controlled to the same non-zero DC values, any such two or more mirror electrodes 30.sub.1-30.sub.7 may be electrically connected to a single one of the voltage outputs DC1-DC7 and superfluous ones of the output voltages DC1-DC7 may be omitted.

(31) As illustrated by example in FIGS. 2A and 2B, each ion mirror MX is controllable, by selective application of the voltages DC1-DC7, between an ion transmission mode (FIG. 2A) in which the voltages DC1-DC7 produced by the voltage source VX establish ion transmission electric fields in each of the regions R1, R2 of the ion mirror MX, and an ion reflection mode (FIG. 2B) in which the voltages DC1-DC7 produced by the voltage source VX establish ion trapping or reflection electric fields in each of the regions R1, R2 of the ion mirror MX. In the ion transmission mode, the voltages DC1-DC7 are selected to establish an ion transmission electric field TEF1 within the region R1 of the ion mirror MX and to establish another ion transmission electric field TEF2 within the region R2 of the ion mirror MX. Example ion transmission electric field lines are depicted in each of the ion mirror regions R1 and R2 of the ion mirror illustrated in FIG. 2A. The ion transmission electric fields TEF1 and TEF2 are illustratively established so as to focus ions toward the central, longitudinal axis 24 within the ion mirror MX so as to maintain a narrow ion trajectory about the axis 24 as ions pass through both regions R1, R2 the ion mirror MX into an adjacent charge detection cylinder CDX.

(32) In the ion reflection mode, the voltages DC1-DC7 are selected to establish an ion reflection electric field REF1 within the region R1 of the ion mirror MX and to establish another ion reflection electric field REF2 within the region R2 of the ion mirror MX. Example ion reflection electric field lines are depicted in each of the ion mirror regions R1 and R2 of the ion mirror illustrated in FIG. 2B. The ion reflection electric fields REF2 and REF2 are illustratively established so as to cause an ion traveling axially into the respective region R1, R2 toward the central aperture CA of MX to reverse direction and be accelerated by the reflection electric field REF1, REF2 in an opposite direction axially away from the central aperture CA. Each ion reflection electric field REF1, REF2 does so by first decelerating and stopping the ion traveling into the respective region R1, R2 of the ion mirror MX, and then accelerating the ion in the opposite direction back through the respective region R1, R2 while focusing the ion toward the longitudinal axis 24 such that the ion travels away from the respective region R1, R2 along a narrow trajectory in an opposite direction from which the ion entered the respective region R1, R2. Thus, an ion traveling from the charge detection cylinder CD.sub.X-1 into the region R1 of the ion mirror MX along or close to the central, longitudinal axis 24 is reflected by reflective electric field REF1 back toward and into the charge detection cylinder CD.sub.X-1 along or close to the central, longitudinal axis 24, and another ion traveling from the charge detection cylinder CDX into the region R2 of the ion mirror MX along or close to the central, longitudinal axis 24 is reflected by the reflective electric field REF2 back toward and into the charge detection cylinder CDX along or close to the central, longitudinal axis 24. An ion that traverses the length of the ELIT or ELIT region E1-E3 and is reflected by the ion reflection electric field REF in the ion regions R1, R2 of the respective ion mirrors M1-M4 in a manner that enables the ion to continue traveling back and forth through the charge detection cylinder CD between such the ion mirrors as just described is considered to be trapped within that ELIT or ELIT region E1-E3.

(33) Example sets of output voltages DC1-DC7 produced by the voltage sources V1-V4 respectively to control a corresponding one of the ion mirrors M1-M4 to the ion transmission and reflection modes described above are shown in TABLE I below. It will be understood that the following values of DC1-DC7 are provided only by way of example, and that other values of one or more of DC1-DC7 may alternatively be used.

(34) TABLE-US-00001 TABLE I Ion Mirror Operating Mode Output Voltages (volts DC) Transmission DC1 = DC2 = DC3 = DC5 = DC6 = DC7 = 0 (single ion DC4 = 880 mirror) Transmission V1: DC1 = DC2 = DC3 = DC5 = DC6 = DC7 = 0 (all ion mirrors - DC4 = 830 all-pass) V2-V4: DC1 = DC2 = DC3 = DC5 = DC6 = DC7 = 0 DC4 = 880 Reflection DC1 = DC7 = 0 (single ion DC2 = DC6 = 1350 mirror) DC3 = DC5 = 1250 DC4 = 1900

(35) In the examples illustrated in FIGS. 2A and 2B and described above, the voltage sources V1-V4 are controlled to establish or maintain at any point in time identical electric fields, e.g., ion transmission electric fields TEF or ion reflection electric fields REF, in each of the ion mirror regions R1, R2 of each of the ion mirrors. Such control may also be carried out in embodiments in which one or more of the ion mirror structures is provided in the form of separate, back-to-back ion mirrors as described above. It will be understood, however, that such control represents only one example ion mirror control arrangement, and that in alternate embodiments the voltage sources V1-V4 (and perhaps one or more additional voltage sources) may be controlled to establish, at any particular time or times, different electric fields within the oppositely-facing regions R1, R2 of one or more of the ion mirrors whether provided as a single ion mirror structure or as separate ion mirror structures. Using the arrangement illustrated in FIG. 2B in which an ion reflection electric field REF is established in R1 and R2, for example, the voltage sources V1-V4 (and any additional voltage source(s)) may alternatively be selectively controlled to maintain the ion reflection electric field REF in R1 while at the same time establishing an ion transmission electric field TEF within R2 or vice versa.

(36) Referring now to FIG. 3, a simplified flowchart is shown of a process 100 for controlling the voltage sources V1-V4 to selectively and sequentially control the ion mirrors M1-M4 between their transmission and reflection modes described above to cause an ion entering into the ELIT array 14 from the ion source 12 to be trapped in each of three separate ELITs or ELIT regions E1-E3 such that each trapped ion repeatedly passes through a respective one of the charge detectors CD1-CD3 in a respective one of the three ELITs or ELIT regions E1-E3. The charge and oscillation period values are measured and recorded at each charge detector CD1-CD3 each time a respective oscillating ion passes therethrough, and ion charge, mass-to-charge and mass values are then determined based on the recorded data. In the illustrated embodiment, the process 100 is illustratively stored in the memory 18 in the form of instructions which, when executed by the processor 16, cause the processor 16 to perform the stated functions. In alternate embodiments in which one or more of the voltage sources V1-V4 is/are programmable independently of the processor 16, one or more aspects of the process 100 may be executed in whole or in part by the one or more such programmable voltage sources V1-V4. For purposes of this disclosure, however, the process 100 will be described as being executed solely by the processor 16. With the aid of FIGS. 4A-4E, the process 100 will be described as operating on positively charged ions, although it will be understood that the process 100 may alternatively operate on one or more negatively charges particles.

(37) With reference to FIG. 4A, the process 100 begins at step 102 where the processor 16 is operable to control the voltage sources V1-V4 to set the voltages DC1-DC7 of each in a manner which causes all of the ion mirrors M1-M4 to operate in the ion transmission mode such that the transmission electric fields TEF1, TEF2 established in the respective regions R1, R2 of each operates to pass ions therethrough while focusing the ions toward the longitudinal axis 24 so as to follow a narrow trajectory through the ELIT array 14. In one example embodiment, the voltage sources V1-V4 are illustratively controlled at step 102 of the process 100 to produce the voltages DC1-DC7 according to the all-pass transmission mode as illustrated in Table I above. In any case, with each of the voltage sources V1-V4 set at step 102 to control the ion mirrors M1-M4 to operate in the ion transmission mode, ions entering M1 from the ion source 12 pass through all of the ion mirrors M1-M4 and all of the charge detectors CD1-CD3 and exit M4 as illustrated by the example ion trajectory 50 depicted in FIG. 4A. Such control of the ion mirrors M1-M4 to their respective transmission modes thus passes one or more ions entering the ELIT array 14 from the ion source 12 into and through the entire ELIT array 14 as shown in FIG. 4A. The ion trajectory 50 depicted in FIG. 4A may illustratively represent a single ion or a collection of ions.

(38) Following step 102, the process 100 advances to step 104 where the processor 16 is operable to pause and determine when to advance to step 106. In one embodiment of step 102, the ELIT array 14 is illustratively controlled in a “random trapping mode” in which the ion mirrors M1-M4 are held in their transmission modes for a selected time period during which one or more ions generated by the ion source 12 will be expected to enter and travel through the ELIT array 14. As one non-limiting example, the selected time period which the processor 16 spends at step 104 before moving on to step 106 when operating in the random trapping mode is on the order of 1-3 millisecond (ms) depending upon the axial length of the ELIT array 14 and of the velocity of ions entering the ELIT array 14, although it will be understood that such selected time period may, in other embodiments, be greater than 3 ms or less than 1 ms. Until the selected time period has elapsed, the process 100 follows the NO branch of step 104 and loops back to the beginning of step 104. After passage of the selected time period, the process 100 follows the YES branch of step 104 and advances to step 106. In some alternate embodiments of step 104, such as in embodiments which include the microchannel plate detector 22, the processor 16 may be configured to advance to step 106 only after one or more ions has been detected by the detector 22, with or without a further additional delay period, so as to ensure that ions are being moved through the ELIT array 14 before advancing to step 106. In other alternate embodiments, the ELIT array 14 may illustratively be controlled by the processor 16 in a “trigger trapping mode” in which the ion mirrors M1-M4 are held in their ion transmission modes until an ion is detected at the charge detector CD3. Until such detection, the process 100 follows the NO branch of step 104 and loops back to the beginning of step 104. Detection by the processor 16 of an ion at the charge detector CD3 is indicative of the ion passing through the charge detector CD3 toward the ion mirror M4 and serves as a trigger event which causes the processor 16 to follow the YES branch of step 104 and advance to step 106 of the process 100.

(39) Following the YES branch of step 104 and with reference to FIG. 4B, the processor 16 is operable at step 106 to control the voltage source V4 to set the output voltages DC1-DC7 thereof in a manner which changes or switches the operation of the ion mirror M4 from the ion transmission mode of operation to the ion reflection mode of operation in which an ion reflection electric field R4.sub.1 is established within the region R1 of M4. The ion reflection electric field R4.sub.1 operates, as described above, to reflect the one or more ions entering the region R1 of M4 back toward the ion mirror M3 (and through the charge detector CD3) as described above with respect to FIG. 2B. The output voltages DC1-DC7 produced by the voltage sources V1-V3 respectively are unchanged at step 106 so that the ion mirrors M1-M3 each remain in the ion transmission mode. As a result, an ion traveling in the ELIT array 14 toward the ion mirror M4 is reflected back toward the ion mirror M3 and will be focused toward the axis 24 as the ion moves toward the ion inlet of M3, as illustrated by the ion trajectory 50 illustrated in FIG. 4B.

(40) Following step 106, the process 100 advances to step 108 where the processor 16 is operable to pause and determine when to advance to step 110. In embodiments of step 108 in which the ELIT array 14 is controlled by the processor 16 in random trapping mode, the ion mirrors M1-M3 are held at step 108 in their transmission modes for a selected time period during which an ion may enter the ELIT or ELIT region E3. As one non-limiting example, the selected time period which the processor 16 spends at step 108 before moving on to step 110 when operating in the random trapping mode is on the order of 0.1 millisecond (ms), although it will be understood that such selected time period may, in other embodiments, be greater than 0.1 ms or less than 0.1 ms. Until the selected time period has elapsed, the process 100 follows the NO branch of step 108 and loops back to the beginning of step 108. After passage of the selected time period, the process 100 follows the YES branch of step 108 and advances to step 110. In alternate embodiments of step 108 in which the ELIT array 14 is controlled by the processor 16 in trigger trapping mode, the ion mirrors M1-M3 are held in their ion transmission modes until an ion is detected at the charge detector CD3. Until such detection, the process 100 follows the NO branch of step 108 and loops back to the beginning of step 108. Detection by the processor 16 of an ion at the charge detector CD3 ensures that the ion is moving through the charge detector CD3 and serves as a trigger event which causes the processor 16 to follow the YES branch of step 108 and advance to step 110 of the process 100.

(41) Following the YES branch of step 108 and with reference to FIG. 4C, the processor 16 is operable at step 110 to control the voltage source V3 to set the output voltages DC1-DC7 thereof in a manner which changes or switches the operation of the ion mirror M3 from the ion transmission mode of operation to the ion reflection mode of operation in which an ion reflection electric field R3.sub.1 is established within the region R1 of M3 and an ion reflection electric field R3.sub.2 is established within the region R2 of M3. As a result, an ion is trapped within the ELIT or ELIT region E3, and due to the reflection electric fields R3.sub.2 and R4.sub.1 established within region R2 of the ion mirror M3 and the region R1 of the ion mirror M4 respectively, the trapped ion oscillates between M3 and M4, each time passing through the charge detection cylinder CD3 as illustrated by the ion trajectory 50.sub.3 depicted in FIG. 4C. Each time the ion passes through the charge detection cylinder CD3 it induces a charge on the cylinder CD3 which is detected by the charge preamplifier CP3 (see FIG. 1). At step 112, the processor 16 is operable, as the ion oscillates back and forth between the ion mirrors M3, M4 and through the charge detection cylinder CD3, to record an amplitude and timing of each such CD3 charge detection event and to store it in the memory 18.

(42) The ion reflection electric field R3.sub.1 operates, as described above, to reflect an ion entering the region R1 of M3 back toward the ion mirror M2 (and through the charge detector CD2) as described above with respect to FIG. 2B. The output voltages DC1-DC7 produced by the voltage sources V1-V2 respectively are unchanged at steps 110 and 112 so that the ion mirrors M1-M2 each remain in the ion transmission mode. As a result, an ion traveling in the ELIT array 14 toward the ion mirror M3 is reflected back toward the ion mirror M2 and will be focused toward the axis 24 as it moves toward the ion inlet of M1, as illustrated by the ion trajectory 50.sub.1, 2 illustrated in FIG. 4C.

(43) Following steps 110 and 112, the process 100 advances to step 114 where the processor 16 is operable to pause and determine when to advance to step 116. In embodiments of step 114 in which the ELIT array 14 is controlled by the processor 16 in random trapping mode, the ion mirrors M1-M2 are held at step 114 in their transmission modes for a selected time period during which one or more ions may enter the ELIT or ELIT region E2. As one non-limiting example, the selected time period which the processor 16 spends at step 114 before moving on to step 116 when operating in the random trapping mode is on the order of 0.1 millisecond (ms), although it will be understood that such selected time period may, in other embodiments, be greater than 0.1 ms or less than 0.1 ms. Until the selected time period has elapsed, the process 100 follows the NO branch of step 114 and loops back to the beginning of step 108. After passage of the selected time period, the process 100 follows the YES branch of step 114 and advances to step 116. In alternate embodiments of step 114 in which the ELIT array 14 is controlled by the processor 16 in trigger trapping mode, the ion mirrors M1-M2 are held in their ion transmission modes until an ion is detected at the charge detector CD2. Until such detection, the process 100 follows the NO branch of step 114 and loops back to the beginning of step 114. Detection by the processor 16 of an ion at the charge detector CD2 ensures that the ion is moving through the charge detector CD2 and serves as a trigger event which causes the processor 16 to follow the YES branch of step 114 and advance to step 116 of the process 100.

(44) The ion reflection electric field R2.sub.1 operates, as described above, to reflect an ion entering the region R1 of M2 back toward the ion mirror M1 (and through the charge detector CD1) as described above with respect to FIG. 2B. The output voltages DC1-DC7 produced by the voltage source V1 are unchanged at steps 116 and 118 so that the ion mirror M1 remains in the ion transmission mode. As a result, an ion traveling in the ELIT array 14 toward the ion mirror M2 is reflected back toward the ion mirror M1 and will be focused toward the axis 24 as the ion moves toward the ion inlet of M1, as illustrated by the ion trajectory 50.sub.1 illustrated in FIG. 4D.

(45) Following the YES branch of step 114 and as the ion in the ELIT or ELIT region E3 continues to oscillate back and forth through the charge detection cylinder CD3 between the ion mirrors M3 and M4, the process 100 advances to step 116. With reference to FIG. 4D, the processor 16 is operable at step 116 to control the voltage source V2 to set the output voltages DC1-DC7 thereof in a manner which changes or switches the operation of the ion mirror M2 from the ion transmission mode of operation to the ion reflection mode of operation in which an ion reflection electric field R2.sub.1 is established within the region R1 of M2 and an ion reflection electric field R2.sub.2 is established within the region R2 of M2. As a result, an ion is trapped within the ELIT or ELIT region E2, and due to the reflection electric fields R2.sub.2 and R3.sub.1 established within region R2 of the ion mirror M2 and the region R1 of the ion mirror M3 respectively, the trapped ion oscillates between M2 and M3, each time passing through the charge detection cylinder CD2 as illustrated by the ion trajectory 50.sub.2 depicted in FIG. 4D. Each time the ion passes through the charge detection cylinder CD2 it induces a charge on the cylinder CD2 which is detected by the charge preamplifier CP2 (see FIG. 1). At step 118, the processor 16 is operable, as the ion oscillates back and forth between the ion mirrors M2, M3 and through the charge detection cylinder CD2, to record an amplitude and timing of each such CD2 charge detection event and to store it in the memory 18. Thus, following step 116, an ion is oscillating back and forth through the charge detection cylinder CD3 of the ELIT or ELIT region E3 between the ion mirrors M3 and M4 and, simultaneously, another ion is oscillating back and forth through the charge detection cylinder CD2 of the ELIT or ELIT region E2 between the ion mirrors M2 and M3.

(46) Following steps 116 and 118, the process 100 advances to step 120 where the processor 16 is operable to pause and determine when to advance to step 122. In embodiments of step 120 in which the ELIT array 14 is controlled by the processor 16 in random trapping mode, the ion mirror M1 is held at step 120 in its transmission mode of operation for a selected time period during which one or more ions may enter the ELIT or ELIT region E1. As one non-limiting example, the selected time period which the processor 16 spends at step 120 before moving on to step 122 when operating in the random trapping mode is on the order of 0.1 millisecond (ms), although it will be understood that such selected time period may, in other embodiments, be greater than 0.1 ms or less than 0.1 ms. Until the selected time period has elapsed, the process 100 follows the NO branch of step 120 and loops back to the beginning of step 120. After passage of the selected time period, the process 100 follows the YES branch of step 120 and advances to step 122. In alternate embodiments of step 120 in which the ELIT array 14 is controlled by the processor 16 in trigger trapping mode, the ion mirror M1 is held in its ion transmission mode of operation until an ion is detected at the charge detector CD1. Until such detection, the process 100 follows the NO branch of step 120 and loops back to the beginning of step 120. Detection by the processor 16 of an ion at the charge detector CD1 ensures that an ion is moving through the charge detector CD1 and serves as a trigger event which causes the processor 16 to follow the YES branch of step 120 and advance to step 122 of the process 100.

(47) Following the YES branch of step 120, and an ion in the ELIT or ELIT region E3 continues to oscillate back and forth through the charge detection cylinder CD3 between the ion mirrors M3 and M4 and also as another ion in the ELIT or ELIT region E2 simultaneously continues to oscillate back and forth through the charge detection cylinder CD2 between the ion mirrors M2 and M3 the process 100 advances to step 122. With reference to FIG. 4E, the processor 16 is operable at step 122 to control the voltage source V1 to set the output voltages DC1-DC7 thereof in a manner which changes or switches the operation of the ion mirror M1 from the ion transmission mode of operation to the ion reflection mode of operation in which an ion reflection electric field R1.sub.1 is established within the region R1 of M1 and an ion reflection electric field R12 is established within the region R1 of M1. As a result, an ion is trapped within the ELIT or ELIT region E1, and due to the reflection electric fields R12 and R2.sub.1 established within region R2 of the ion mirror M1 and the region R2 of the ion mirror M2 respectively, the trapped ion oscillates between M1 and M2, each time passing through the charge detection cylinder CD1 as illustrated by the ion trajectory 50.sub.1 depicted in FIG. 4E. Each time the ion passes through the charge detection cylinder CD1 it induces a charge on the cylinder CD1 which is detected by the charge preamplifier CP1 (see FIG. 1). At step 124, the processor 16 is operable, as the ion oscillates back and forth between the ion mirrors M1, M2 and through the charge detection cylinder CD1, to record an amplitude and timing of each such CD1 charge detection event and to store it in the memory 18. Thus, following step 122, an ion is oscillating back and forth through the charge detection cylinder CD3 of the ELIT or ELIT region E3 between the ion mirrors M3 and M4 and, simultaneously, another ion is oscillating back and forth through the charge detection cylinder CD2 of the ELIT or ELIT region E2 between the ion mirrors M2 and M3, and also simultaneously yet another ion is oscillating back and forth through the charge detection cylinder CD1 of the ELIT or ELIT region E1 between the ion mirrors M1 and M2.

(48) Following steps 122 and 124, the process 100 advances to step 126 where the processor 16 is operable to pause and determine when to advance to step 128. In one embodiment, the processor 16 is configured, i.e. programmed, to allow the ions to oscillate back and forth simultaneously through each of the ELITs or ELIT regions E1-E3 for a selected time period, i.e., a total ion cycle measurement time, during which ion detection events, i.e., by each of the charge detectors CD1-CD3, are recorded by the processor 16. As one non-limiting example, the selected time period which the processor 16 spends at step 126 before moving on to step 128 is on the order of 100-300 millisecond (ms), although it will be understood that such selected time period may, in other embodiments, be greater than 300 ms or less than 100 ms. Until the selected time period has elapsed, the process 100 follows the NO branch of step 126 and loops back to the beginning of step 126. After passage of the selected time period, the process 100 follows the YES branch of step 126 and advances to steps 128 and 140. In some alternate embodiments of the process 100, the voltage sources V1-V4 may illustratively be controlled by the processor 16 at step 126 to allow the ions to oscillate back in forth through the charge detectors CD1-CD3 a selected number of times, i.e., a total number of measurement cycles, during which ion detection events, i.e., by each of the charge detectors CD1-CD3, are recorded by the processor 16. Until the processor counts the selected number ion detection events of one or more of the charge detectors CD1-CD3, the process 100 follows the NO branch of step 126 and loops back to the beginning of step 126. Detection by the processor 16 of the selected number of ion detection events serves as a trigger event which causes the processor 16 to follow the YES branch of step 126 and advance to steps 128 and 140 of the process 100.

(49) Following the YES branch of step 126, the processor 16 is operable at step 128 to control the voltage sources V1-V4 to set the output voltages DC1-DC7 of each in a manner which changes or switches the operation of all of the ion mirrors M1-M4 from the ion reflection mode of operation to the ion transmission mode of operation in which the ion mirrors M1-M4 each operate to allow passage of ions therethrough. Illustratively, the voltage sources V1-V4 are illustratively controlled at step 128 of the process 100 to produce the voltages DC1-DC7 according to the all-pass transmission mode as illustrated in Table I above, which re-establishes the ion trajectory 50 illustrated in FIG. 4A in which (i) all ions within the ELIT array 14 are focused by the ion transmission electric fields TEF1, TEF2 established in each of the ion mirrors M1-M4 toward the axis 24 such that the ions move through and out of the ELIT array 14, and (ii) all ions entering M1 from the ion source 12 pass through all of the ion mirrors M1-M4 and all of the charge detectors CD1-CD3.

(50) Following step 128, the processor 16 is operable at step 130 to pause for a selected time period to allow the ions contained within the ELIT array 14 to travel out of the ELIT array 14. As one non-limiting example, the selected time period which the processor 12 spends at step 130 before looping back to step 102 to restart the process 100 is on the order of 1-3 milliseconds (ms), although it will be understood that such selected time period may, in other embodiments, be greater than 3 ms or less than 1 ms. Until the selected time period has elapsed, the process 100 follows the NO branch of step 130 and loops back to the beginning of step 130. After passage of the selected time period, the process 100 follows the YES branch of step 130 and loops back to step 102 to restart the process 100.

(51) Also following the YES branch of step 126, the process 100 additionally advances to step 140 to analyze the data collected during steps 112, 118 and 124 of the process 100 just described. In the illustrated embodiment, the data analysis step 140 illustratively includes step 142 in which the processor 16 is operable to compute Fourier transforms of the recorded sets of stored charge detection signals provided by each of the charge preamplifiers CP1-CP3. The processor 16 is illustratively operable to execute step 142 using any conventional digital Fourier transform (DFT) technique such as for example, but not limited to, a conventional Fast Fourier Transform (FFT) algorithm. In any case, the processor 16 is operable at step 142 to compute three Fourier Transforms, FT.sub.1, FT.sub.2 and FT.sub.3, wherein FT.sub.1 is the Fourier Transform of the recorded set of charge detection signals provided by the first charge preamplifier CP1, thus corresponding to the charge detection events detected by the charge detection cylinder CD1 of the ELIT or ELIT region E1, FT.sub.2 is the Fourier Transform of the recorded set of charge detection signals provided by the first charge preamplifier CP2, thus corresponding to the charge detection events detected by the charge detection cylinder CD2 of the ELIT or ELIT region E2 and FT.sub.3 is the Fourier Transform of the recorded set of charge detection signals provided by the first charge preamplifier CP3, thus corresponding to the charge detection events detected by the charge detection cylinder CD3 of the ELIT or ELIT region E3.

(52) Following step 142, the process 100 advances to step 144 where the processor 16 is operable to compute three sets of ion mass-to-charge ratio values (m/z.sub.1, m/z.sub.2 and m/z.sub.3), ion charge values (z.sub.1, z.sub.2 and z.sub.3) and ion mass values (m.sub.1, m.sub.2 and m.sub.3), each as a function of a respective one of the computed Fourier Transform values FT.sub.1, FT.sub.2, FT.sub.3). Thereafter at step 146 the processor 16 is operable to store the computed results in the memory 18 and/or to control one or more of the peripheral devices 20 to display the results for observation and/or further analysis.

(53) It is generally understood that the mass-to-charge ratio (m/z) of ion(s) oscillating back and forth between opposing ion mirrors in any of the ELITs or ELIT regions E1-E3 is inversely proportional to the square of the fundamental frequency ff of the oscillating ion(s) according to the equation:
m/z=C/ff.sup.2,
where C is a constant that is a function of the ion energy and also a function of the dimensions of the respective ELIT or ELIT region, and the fundamental frequency ff is determined directly from the respective computed Fourier Transform. Thus, ff.sub.1 is the fundamental frequency of FT.sub.1, ff.sub.2 is the fundamental frequency of FT.sub.2 and ff.sub.3 is the fundamental frequency of FT.sub.3. Typically, C is determined using conventional ion trajectory simulations. In any case, the value of the ion charge, z, is proportional to the magnitude FT.sub.MAG of the fundamental frequency of the respective Fourier Transform FT, taking into account the number of ion oscillation cycles. In some cases, the magnitude(s) of one or more of the harmonic frequencies of the FFT may be added to the magnitude of the fundamental frequency for purposes of determining the ion charge values. In any case, ion mass, m, is then calculated as a product of m/z and z. Thus, with respect to the recorded set of charge detection signals provided by the first charge preamplifier CP1, the processor 16 is operable at step 144 to compute m/z.sub.1=C/ff.sub.1.sup.2, z.sub.1=F(FT.sub.MAG1) and m.sub.1=(m/z.sub.1)(z.sub.1). With respect to the recorded set of charge detection signals provided by the second charge preamplifier CP2, the processor 16 is similarly operable at step 144 to compute m/z.sub.2=C/ff.sub.2.sup.2, z.sub.2=F(FT.sub.MAG2) and m.sub.2=(m/z.sub.2)(z.sub.2), and with respect to the recorded set of charge detection signals provided by the third charge preamplifier CP3, the processor 16 is likewise operable at step 144 to compute m/z.sub.3=C/ff.sub.3.sup.2, z.sub.3=F(FT.sub.MAG3) and m.sub.3=(m/z.sub.3)(z.sub.3).

(54) Referring now to FIG. 5A, a simplified block diagram is shown of an embodiment of an ion separation instrument 60 which may include any of the ELIT arrays 14, 205, 302 illustrated and described herein and which may include any of the charge detection mass spectrometers (CDMS) 10, 200, 300 illustrated and described herein, and which may include any number of ion processing instruments which may form part of the ion source 12 upstream of the ELIT array(s) and/or which may include any number of ion processing instruments which may be disposed downstream of the ELIT array(s) to further process ion(s) exiting the ELIT array(s). In this regard, the ion source 12 is illustrated in FIG. 5A as including a number, Q. of ion source stages IS.sub.1-IS.sub.Q which may be or form part of the ion source 12. Alternatively or additionally, an ion processing instrument 70 is illustrated in FIG. 5A as being coupled to the ion outlet of the ELIT array 14, 205, 302, wherein the ion processing instrument 70 may include any number of ion processing stages OS.sub.1-OS.sub.R, where R may be any positive integer.

(55) Focusing on the ion source 12, it will be understood that the source 12 of ions entering the ELIT 10 may be or include, in the form of one or more of the ion source stages IS.sub.1-IS.sub.Q, any conventional source of ions as described above, and may further include one or more conventional instruments for separating ions according to one or more molecular characteristics (e.g., according to ion mass, ion mass-to-charge, ion mobility, ion retention time, or the like) and/or one or more conventional ion processing instruments for collecting and/or storing ions (e.g., one or more quadrupole, hexapole and/or other ion traps), for filtering ions (e.g., according to one or more molecular characteristics such as ion mass, ion mass-to-charge, ion mobility, ion retention time and the like), for fragmenting or otherwise dissociating ions, for normalizing ion charge states, and the like. It will be understood that the ion source 12 may include one or any combination, in any order, of any such conventional ion sources, ion separation instruments and/or ion processing instruments, and that some embodiments may include multiple adjacent or spaced-apart ones of any such conventional ion sources, ion separation instruments and/or ion processing instruments.

(56) Turning now to the ion processing instrument 70, it will be understood that the instrument 70 may be or include, in the form of one or more of the ion processing stages OS.sub.1-OS.sub.R, one or more conventional instruments for separating ions according to one or more molecular characteristics (e.g., according to ion mass, ion mass-to-charge, ion mobility, ion retention time, or the like) and/or one or more conventional ion processing instruments for collecting and/or storing ions (e.g., one or more quadrupole, hexapole and/or other ion traps), for filtering ions (e.g., according to one or more molecular characteristics such as ion mass, ion mass-to-charge, ion mobility, ion retention time and the like), for fragmenting or otherwise dissociating ions, for normalizing ion charge states, and the like. It will be understood that the ion processing instrument 70 may include one or any combination, in any order, of any such conventional ion separation instruments and/or ion processing instruments, and that some embodiments may include multiple adjacent or spaced-apart ones of any such conventional ion separation instruments and/or ion processing instruments. In any implementation which includes one or more mass spectrometers, any one or more such mass spectrometers may be implemented in any of the forms described above with respect to FIG. 1.

(57) As one specific implementation of the ion separation instrument 60 illustrated in FIG. 5A, which should not be considered to be limiting in any way, the ion source 12 illustratively includes 3 stages, and the ion processing instrument 70 is omitted. In this example implementation, the ion source stage IS.sub.1 is a conventional source of ions, e.g., electrospray, MALDI or the like, the ion source stage IS.sub.2 is a conventional mass filter, e.g., a quadrupole or hexapole ion guide operated as a high-pass or band-pass filter, and the ion source stage IS.sub.3 is a mass spectrometer of any of the types described above. In this embodiment, the ion source stage IS.sub.2 is controlled in a conventional manner to preselect ions having desired molecular characteristics for analysis by the downstream mass spectrometer, and to pass only such preselected ions to the mass spectrometer, wherein the ions analyzed by the ELIT array 14, 205, 302 will be the preselected ions separated by the mass spectrometer according to mass-to-charge ratio. The preselected ions exiting the ion filter may, for example, be ions having a specified ion mass or mass-to-charge ratio, ions having ion masses or ion mass-to-charge ratios above and/or below a specified ion mass or ion mass-to-charge ratio, ions having ion masses or ion mass-to-charge ratios within a specified range of ion mass or ion mass-to-charge ratio, or the like. In some alternate implementations of this example, the ion source stage IS.sub.2 may be the mass spectrometer and the ion source stage IS.sub.3 may be the ion filter, and the ion filter may be otherwise operable as just described to preselect ions exiting the mass spectrometer which have desired molecular characteristics for analysis by the downstream ELIT array 14, 205, 302. In other alternate implementations of this example, the ion source stage IS.sub.2 may be the ion filter, and the ion source stage IS.sub.3 may include a mass spectrometer followed by another ion filter, wherein the ion filters each operate as just described.

(58) As another specific implementation of the ion separation instrument 60 illustrated in FIG. 5A, which should not be considered to be limiting in any way, the ion source 12 illustratively includes 2 stages, and the ion processing instrument 70 is omitted. In this example implementation, the ion source stage IS.sub.1 is a conventional source of ions, e.g., electrospray, MALDI or the like, the ion source stage IS.sub.2 is a conventional mass spectrometer of any of the types described above. This is the CDMS implementation described above with respect to FIG. 1 in which the ELIT array 14, 205, 302 is operable to analyze ions exiting the mass spectrometer.

(59) As yet another specific implementation of the ion separation instrument 60 illustrated in FIG. 5A, which should not be considered to be limiting in any way, the ion source 12 illustratively includes 2 stages, and the ion processing instrument 70 is omitted. In this example implementation, the ion source stage IS.sub.1 is a conventional source of ions, e.g., electrospray, MALDI or the like, and the ion processing stage OS.sub.2 is a conventional single or multiple-stage ion mobility spectrometer. In this implementation, the ion mobility spectrometer is operable to separate ions, generated by the ion source stage IS.sub.1, over time according to one or more functions of ion mobility, and the ELIT array 14, 205, 302 is operable to analyze ions exiting the ion mobility spectrometer. In an alternate implementation of this example, the ion source 12 may include only a single stage IS.sub.1 in the form of a conventional source of ions, and the ion processing instrument 70 may include a conventional single or multiple-stage ion mobility spectrometer as a sole stage OS.sub.1 (or as stage OS.sub.1 of a multiple-stage instrument 70). In this alternate implementation, the ELIT array 14, 205, 302 is operable to analyze ions generated by the ion source stage IS.sub.1, and the ion mobility spectrometer OS.sub.1 is operable to separate ions exiting the ELIT array 14, 205, 302 over time according to one or more functions of ion mobility. As another alternate implementation of this example, single or multiple-stage ion mobility spectrometers may follow both the ion source stage IS.sub.1 and the ELIT array 14, 205, 302. In this alternate implementation, the ion mobility spectrometer following the ion source stage IS.sub.1 is operable to separate ions, generated by the ion source stage IS.sub.1, over time according to one or more functions of ion mobility, the ELIT array 14, 205, 302 is operable to analyze ions exiting the ion source stage ion mobility spectrometer, and the ion mobility spectrometer of the ion processing stage OS.sub.1 following the ELIT array 14, 205, 302 is operable to separate ions exiting the ELIT array 14, 205, 302 over time according to one or more functions of ion mobility. In any implementations of the embodiment described in this paragraph, additional variants may include a mass spectrometer operatively positioned upstream and/or downstream of the single or multiple-stage ion mobility spectrometer in the ion source 12 and/or in the ion processing instrument 210.

(60) As still another specific implementation of the ion separation instrument 60 illustrated in FIG. 5A, which should not be considered to be limiting in any way, the ion source 12 illustratively includes 2 stages, and the ion processing instrument 70 is omitted. In this example implementation, the ion source stage IS.sub.1 is a conventional liquid chromatograph, e.g., HPLC or the like configured to separate molecules in solution according to molecule retention time, and the ion source stage IS.sub.2 is a conventional source of ions, e.g., electrospray or the like. In this implementation, the liquid chromatograph is operable to separate molecular components in solution, the ion source stage IS.sub.2 is operable to generate ions from the solution flow exiting the liquid chromatograph, and the ELIT array 14, 205, 302 is operable to analyze ions generated by the ion source stage IS.sub.2. In an alternate implementation of this example, the ion source stage IS.sub.1 may instead be a conventional size-exclusion chromatograph (SEC) operable to separate molecules in solution by size. In another alternate implementation, the ion source stage IS.sub.1 may include a conventional liquid chromatograph followed by a conventional SEC or vice versa. In this implementation, ions are generated by the ion source stage IS.sub.2 from a twice separated solution; once according to molecule retention time followed by a second according to molecule size, or vice versa. In any implementations of the embodiment described in this paragraph, additional variants may include a mass spectrometer operatively positioned between the ion source stage IS.sub.2 and the ELIT 14, 205, 302.

(61) Referring now to FIG. 5B, a simplified block diagram is shown of another embodiment of an ion separation instrument 80 which illustratively includes a multi-stage mass spectrometer instrument 82 and which also includes any of the CDMS instruments 10, 200, 300 illustrated and described herein implemented as a high ion mass analysis component. In the illustrated embodiment, the multi-stage mass spectrometer instrument 82 includes an ion source (IS) 12, as illustrated and described herein, followed by and coupled to a first conventional mass spectrometer (MS1) 84, followed by and coupled to a conventional ion dissociation stage (ID) 86 operable to dissociate ions exiting the mass spectrometer 84, e.g., by one or more of collision-induced dissociation (CID), surface-induced dissociation (SID), electron capture dissociation (ECD) and/or photo-induced dissociation (PID) or the like, followed by an coupled to a second conventional mass spectrometer (MS2) 88, followed by a conventional ion detector (D) 90, e.g., such as a microchannel plate detector or other conventional ion detector. The CDMS 10, 200, 300 is coupled in parallel with and to the ion dissociation stage 86 such that the CDMS 10, 200, 300 may selectively receive ions from the mass spectrometer 84 and/or from the ion dissociation stage 86.

(62) MS/MS, e.g., using only the ion separation instrument 82, is a well-established approach where precursor ions of a particular molecular weight are selected by the first mass spectrometer 84 (MS1) based on their m/z value. The mass selected precursor ions are fragmented, e.g., by collision-induced dissociation, surface-induced dissociation, electron capture dissociation or photo-induced dissociation, in the ion dissociation stage 86. The fragment ions are then analyzed by the second mass spectrometer 86 (MS2). Only the m/z values of the precursor and fragment ions are measured in both MS1 and MS2. For high mass ions, the charge states are not resolved and so it is not possible to select precursor ions with a specific molecular weight based on the m/z value alone. However, by coupling the instrument 82 to the CDMS 10, 200, 300 illustrated and described herein, it is possible to select a narrow range of m/z values and then use the CDMS 10, 200, 300 to determine the masses of the m/z selected precursor ions. The mass spectrometers 84, 88 may be, for example, one or any combination of a magnetic sector mass spectrometer, time-of-flight mass spectrometer or quadrupole mass spectrometer, although in alternate embodiments other mass spectrometer types may be used. In any case, the m/z selected precursor ions with known masses exiting MS1 can be fragmented in the ion dissociation stage 86, and the resulting fragment ions can then be analyzed by MS2 (where only the m/z ratio is measured) and/or by the CDMS instrument 10, 200, 300 (where the m/z ratio and charge are measured simultaneously). Low mass fragments, i.e., dissociated ions of precursor ions having mass values below a threshold mass value, e.g., 10,000 Da (or other mass value), can thus be analyzed by conventional MS, using MS2, while high mass fragments (where the charge states are not resolved), i.e., dissociated ions of precursor ions having mass values at or above the threshold mass value, can be analyzed by the CDMS 10, 200, 300.

(63) Referring now to FIG. 6, another CDMS 200 is shown including another embodiment of an electrostatic linear ion trap (ELIT) array 205 with control and measurement components coupled thereto. In the illustrated embodiment, the ELIT array 205 includes three separate ELITs 202, 204, 206 each configured identically to the ELIT or ELIT region E3 of the ELIT array 14 illustrated in FIG. 1. For example, the ELIT 202 includes a charge detection cylinder CD1 surrounded by a ground chamber GC1, wherein one end of the ground chamber GC1 defines one of the mirror electrodes of one ion mirror M1 and an opposite end of the ground chamber GC1 defines one of the mirror electrodes of another ion mirror M2, and wherein the ion mirrors M1, M2 are disposed at opposite ends of the charge detection cylinder 202. The ion mirror M1 is illustratively identical in structure and function to each of the ion mirrors M1-M3 illustrated in FIGS. 1-2B, and the ion mirror M2 is illustratively identical in structure and function to the ion mirror M4 illustrated in FIGS. 1-2B. A voltage source V1, illustratively identical in structure and function to the voltage source V1 illustrated in FIGS. 1-2B, is operatively coupled to the ion mirror M1, and another voltage source V2, illustratively identical in structure and function to the voltage source V4 illustrated in FIGS. 1-2B, is operatively coupled to the ion mirror M2. The ion mirror M1 defines an ion inlet aperture AI.sub.1, illustratively identical in structure and function to the aperture A1 of the ion Mirror MX illustrated in FIG. 2A, and the ion mirror M2 defines an outlet aperture AO.sub.1, illustratively identical in structure and operation to the aperture CA of the ion mirror M4 described above with respect to FIGS. 1 and 2B. A longitudinal axis 24.sub.1 extends centrally through the ELIT 202 and illustratively bisects the apertures AI.sub.1 and AO.sub.1. A charge preamplifier CP1 is electrically coupled to the charge detection cylinder CD1, and is illustratively identical in structure and function to the charge preamplifier CP1 illustrated in FIG. 1 and described above.

(64) The ELIT 204 is illustratively identical to the ELIT 202 just described with ion mirrors M3, M4 corresponding to the ion mirrors M1, M2 of the ELIT 202, with the voltage sources V3, V4 corresponding to the voltage sources V1, V2 of the ELIT 202 and with inlet/outlet apertures AI.sub.2/AO.sub.2 defining a longitudinal axis 24.sub.2 extending through the ELIT 204 and illustratively bisecting the apertures AI.sub.2, AO.sub.2. A charge amplifier CP2 is electrically coupled to the charge detection cylinder CD2 of the ELIT 204, and is illustratively identical in structure and function to the charge preamplifier CP2 illustrated in FIG. 1 and described above.

(65) The ELIT 206 is likewise illustratively identical to the ELIT 202 just described with ion mirrors M5, M6 corresponding to the ion mirrors M1, M2 of the ELIT 202, with the voltage sources V5, V6 corresponding to the voltage sources V1, V2 of the ELIT 202 and with inlet/outlet apertures AI.sub.3/AO.sub.3 defining a longitudinal axis 24.sub.3 extending through the ELIT 206 and illustratively bisecting the apertures AI.sub.3, AO.sub.3. A charge amplifier CP3 is electrically coupled to the charge detection cylinder CD3 of the ELIT 206, and is illustratively identical in structure and function to the charge preamplifier CP3 illustrated in FIG. 1 and described above.

(66) The voltage sources V1-V6, as well as the charge preamplifier CP1-CP3, are operatively coupled to a processor 210 including a memory 212 as described with respect to FIG. 1, wherein the memory 212 illustratively has instructions stored therein which, when executed by the processor 210, cause the processor 210 to control operation of the voltage sources V1-V6 to control the ion mirrors M1-M6 between ion transmission and ion reflection operating modes as described above. Alternatively, one or more of the voltage sources V1-V6 may be programmable to operate as described. In any case, the instructions stored in the memory 212 further illustratively include instructions which, when executed by the processor 210, cause the processor to receive, process and record (store) the charge signals detected by the charge preamplifiers CP1-CP3, and to process the recorded charge signal information to compute the masses of ions captured within each of the ELITs 202, 204, 206 as described above. Illustratively, the processor 210 is coupled to one or more peripheral devices 214 which may be identical to the one or more peripheral devices 20 described above with respect to FIG. 1.

(67) In the embodiment illustrated in FIG. 6, an embodiment of an ion steering array 208 is shown operatively coupled between an ion source 12 and the ion inlet apertures AI.sub.1-AI.sub.3 of each ELIT 202, 204, 206 in the ELIT array 205. The ion source 12 is illustratively as described with respect to FIGS. 1 and/or 5A, and is configured to generate and supply ions to the ion steering array 208 via an ion aperture IA. An ion steering voltage source V.sub.ST is operatively coupled to and between the processor 210 and the ion steering array 208. As will be described in detail below, the processor 210 is illustratively configured, i.e., programmed, to control the ion steering voltage source V.sub.ST to cause the ion steering array 208 to selectively steer and guide ions exiting the ion aperture IA of the ion source 12 into the ELITs 202, 204 and 206 via the respective inlet apertures AI.sub.1-AI.sub.3 thereof. The processor 210 is further configured, i.e., programmed, to control the voltage sources V1-V6 to cause the ion mirrors M1-M6 of the ELITs 202, 204, 206 to selectively switch between the ion transmission and ion reflection modes to thereby trap an ion in each of the ELITs 202, 204, 206, and to then cause such ions to oscillate back and forth between the respective ion mirrors M1/M2, M3/M4 and M5/M6 and through the respective charge detection cylinders CD1-CD3 of the ELITs 202, 204, 206 in order to measure and record ion charge detection events detected by the respective charge preamplifiers CP1-CP3 as described above.

(68) While the ELITs 202, 204 and 206 are illustrated in FIG. 6 as being arranged such that their respective longitudinal axes 24.sub.1-24.sub.3 are parallel with one another, it will be understood that this arrangement is provided only by way of example and that other arrangements are contemplated. In alternate embodiments, for example, the longitudinal axis of one or more of the ELITs may be non-parallel with the longitudinal axis of one or others of the ELITs, and/or the longitudinal axes of two or more, but not all, of the ELITs may be coaxial. It is sufficient for purposes of implementing the ion steering array 208 that the longitudinal axis of at least one of the ELITs is not coaxial with the longitudinal axis of one or more of the remaining ELITs.

(69) In the illustrated embodiment, the ion steering array 208 illustratively includes 3 sets of four electrically conductive pads P1-P4, P5-P8 and P9-P12 arranged on each of two spaced-apart planar substrates such that each of the electrically conductive pads P1-P12 on one of the planar substrates is aligned with and faces a respective one of the electrically conductive pads on the other substrate. In the embodiment illustrated in FIG. 6, only one of the substrates 220 is shown.

(70) Referring now to FIGS. 7A-7C, a portion of the ion steering array 208 is shown which illustrates control and operation thereof to selectively steer ions to desired locations. As shown by example in FIGS. 7B and 7C, the voltage sources DC1-DC4 of the illustrated portion of the ion steering 208 are controlled to cause ions exiting the ion aperture IA of the ion source 12 along the direction indicated by the arrow A to change direction by approximately 90 degrees so as to be directed along a path which is aligned, i.e., collinear, with the ion inlet aperture A.sub.1 of the ELIT 202. Although not illustrated in the drawings, any number of conventional planar ion carpets and/or other conventional ion focusing structures may be used to focus the ion trajectories exiting the ion aperture IA of the ion source and/or to and align the ion trajectories selectively altered by the ion steering array 208 with the ion inlet apertures AI.sub.1-AI.sub.3 of the respective ELITs 202, 204, 206.

(71) Referring specifically to FIG. 7A, a pattern of 4 substantially identical and spaced apart electrically conductive pads P1.sub.1-P4.sub.1 is formed on an inner major surface 220A of one substrate 220 having an opposite outer major surface 220B, and an identical pattern of 4 substantially identical and spaced apart electrically conductive pads P1.sub.2-P4.sub.2 is formed on an inner major surface 222A of another substrate 222 having an opposite outer surface 222B. The inner surfaces 220A, 222A of the substrates 220, 222 are spaced apart in a generally parallel relationship, and the electrically conductive pads P1.sub.1-P4.sub.1 are juxtaposed over respective ones of the electrically conductive pads P1.sub.2-P4.sub.2. The spaced-apart, inner major surfaces 220A and 222A of the substrates 220, 222 illustratively define a channel or space 225 therebetween of width a distance DP. In one embodiment, the width, DP, of the channel 225 is approximately 5 cm, although in other embodiments the distance DP may be greater or lesser than 5 cm. In any case, the substrates 220, 222 together make up the illustrated portion of the ion steering array 208.

(72) The opposed pad pairs P3.sub.1, P3.sub.2 and P4.sub.1, P4.sub.2 are upstream of the opposed pad pairs P1.sub.1, P1.sub.2 and P2.sub.1, P2.sub.2, and the opposed pad pairs P1.sub.1, P1.sub.2 and P2.sub.1, P2.sub.2 are conversely downstream of the opposed pad pairs P4.sub.1, P4.sub.2 and P3.sub.1, P3.sub.2. In this regard, the “unaltered direction of ion travel” through the channel 225, as this term is used herein, is “upstream,” and generally parallel with the direction A of ions exiting the ion source 12. Transverse edges 220C, 222C of the substrates 220, 222 are aligned, as are opposite transverse edges 220D, 222D, and the “altered direction of ion travel” through the channel 225, as this term is used herein, is from the aligned edges 220C, 222C toward the aligned edges 220D, 222D, and generally perpendicular to both such aligned edges 220C, 222C and 220D, 222D.

(73) In the embodiment illustrated in FIG. 6, the ion steering voltage source V.sub.ST is illustratively configured to produce at least 12 switchable DC voltages each operatively connected to respective opposed pairs of the electrically conductive pads P1-P12. Four of the 12 DC voltages DC1-D4 are illustrated in FIG. 7A. The first DC voltage DC1 is electrically connected to each of the juxtaposed electrically conductive pads P1.sub.1, P1.sub.2, the second DC voltage DC2 is electrically connected to each of the juxtaposed electrically conductive pads P2.sub.1, P2.sub.2, the third DC voltage DC3 is electrically connected to each of the juxtaposed electrically conductive pads P3.sub.1, P3.sub.2 and the fourth DC voltage DC4 is electrically connected to each of the juxtaposed electrically conductive pads P4.sub.1, P4.sub.2. In the illustrated embodiment, each of the DC voltages DC1-DC12 is independently controlled, e.g., via the processor 210 and/or via programming of the voltage source V.sub.ST, although in alternate embodiments two or more of the DC voltages DC1-DC12 may be controlled together as a group. In any case, it will be understood that although the voltages DC1-DC12 are illustrated and disclosed as being DC voltages, this disclosure contemplates other embodiments in which the voltage source V.sub.ST is alternatively or additionally configured to produce any number of AC voltages such as, for example, one or more RF voltages, and to supply any one or more such AC voltages to corresponding ones or pairs of the electrically conductive pads and/or to one or more ion carpets or other ion focusing structures in embodiments which include them.

(74) Referring now to FIGS. 7B and 7C, operation of the ion steering channel array 208 illustrated in FIG. 6 will be described using the four opposed pairs of electrically conductive pads P1.sub.1/P1.sub.2, P2.sub.1/P2.sub.2, P3.sub.1/P3.sub.2 and P4.sub.1/P4.sub.2 of FIGS. 7A and 7B as an illustrative example. It will be understood that the four electrically conductive pads P5-P8 and the four electrically conductive pads P9-P12 illustrated on the substrate 220 in FIG. 6 likewise each comprise opposed, aligned and juxtaposed electrically conductive pad pairs disposed on the inner surfaces 220A, 222A of the respective substrates 220, 222, and that each such set of four opposed pairs of electrically conductive pads are controllable by respective switchable DC (and/or AC) voltages DC5-DC12 produced by the voltage source V.sub.ST. In any case, the DC voltages DC1-DC4 are omitted in FIGS. 7B and 7C for clarity of illustration, and instead the DC voltages DC1-DC4 produced by the voltage source V.sub.ST and applied to the connected pairs of electrically conductive pads P1.sub.1/P1.sub.2, P2.sub.1/P2.sub.2, P3.sub.1/P3.sub.2 and P4.sub.1/P4.sub.2 of are represented graphically. Referring specifically to FIG. 7B, the illustrated portion of the ion steering array 208 is shown in a state in which a reference potential, V.sub.REF, is applied to each of the electrically conductive pad pairs P1.sub.1/P1.sub.2, P2.sub.1/P2.sub.2, and a potential −XV, less than V.sub.REF, is applied to each of the electrically conductive pad pairs P3.sub.1/P3.sub.2 and P4.sub.1/P4.sub.2. Illustratively, V.sub.REF may be any positive or negative voltage, or may be zero volts, e.g., ground potential, and −XV may be any voltage, positive, negative or zero voltage that is less than V.sub.REF so as to establish an electric field E1 which is parallel with the sides 220C/222C and 220D/222D of the substrates 220, 222 and which extends in the unaltered direction of ion travel, i.e., from the downstream electrically conductive pad pairs P1.sub.1/P1.sub.2, P2.sub.1/P2.sub.2 toward the upstream electrically conductive pad pairs P3.sub.1/P3.sub.2 and P4.sub.1/P4.sub.2, as depicted in FIG. 7B. With the electric field, E1, established as illustrated in FIG. 7B, ions A exiting the ion source 12 via the ion aperture IA enter the channel 225 between the downstream electrically conductive pad pairs P1.sub.1/P1.sub.2, P2.sub.1/P2.sub.2 and are steered or guided (or directed) by the electric field, E1, along the unaltered direction of ion travel 230 which is in the same direction as the electric field E1 and which is aligned, i.e., collinear, with the ion aperture IA of the ion source 12. Such ions A are illustratively guided through the channel 225 along the unaltered direction of travel as illustrated in FIG. 7B.

(75) Referring now specifically to FIG. 7C, when it is desired to change directions of the ions A from the unaltered direction of ion travel illustrated in FIG. 7B to the altered direction of ion travel, the DC voltages DC1, DC3 produced by the voltage source V.sub.ST are switched such that the reference potential, V.sub.REF, is applied to each of the electrically conductive pad pairs P2.sub.1/P2.sub.2, P3.sub.1/P3.sub.2, and a potential −XV, less than V.sub.REF, is applied to each of the electrically conductive pad pairs P1.sub.1/P1.sub.2, P4.sub.1/P4.sub.2, so as to establish an electric field E2 which is perpendicular to the sides 220C/222C and 220D/222D of the substrates 220, 222 and which extends in the unaltered direction of ion travel, i.e., from the sides 220C/222C of the substrates 220, 222 toward the sides 220D/222D of the substrates 220, 222, as depicted in FIG. 7C. With the electric field, E2, established as illustrated in FIG. 7C, ions A exiting the ion source 12 via the ion aperture IA and entering the channel 225 are steered or guided (or directed) by the electric field, E2, along the altered direction of ion travel 240, which is in the same direction as the electric field E2 and which is aligned, i.e., collinear, with the ion aperture IA of the ion source 12. Such ions A are illustratively guided through the channel 225 along the unaltered direction of travel between the electrically conductive pad pairs P1.sub.1/P1.sub.2, P4.sub.1/P4.sub.2, as illustrated in FIG. 7C. In some embodiments, one or more conventional ion carpets and/or other conventional ion focusing structures may be used to confine the ions along the ion trajectory 240 illustrated in FIG. 7C.

(76) Referring again to FIG. 6, the instructions stored in the memory 212 illustratively include instructions which, when executed by the processor 210, cause the processor 210 to control the ion steering voltage source V.sub.ST to selectively produce and switch the voltages DC1-DC12 in a manner which guides ions along the ion steering array 208 and sequentially directs an ion into the ion inlet aperture AI.sub.1-AI.sub.3 of each respective ELIT 202, 204, 206, and to also control the voltage sources V1-V6 to selectively produce and switch the DC voltages produced thereby in a manner which controls the respective ion mirrors M1-M6 between their ion transmission and ion reflection modes to trap an ion guided into each ELIT 202, 204, 206 by the ion steering array 208 and to then cause each trapped ion to oscillate back and forth between the respective ion mirrors M1-M6 of each ELIT 202, 204, 206 as the processor 210 records the respective ion charge detection information in the memory 214 as described above with respect to FIGS. 1-4B. With the aid of FIGS. 8A-8F, one example of such a process will be described as operating on one or more positively charged ions, although it will be understood that the process 100 may alternatively operate on one or more negatively charges particles. In the following description, references to any specific one or ones of the electrically conductive pads P1-P12 will be understood as referring to opposed, juxtaposed, spaced-apart pairs of electrically conductive pads disposed on the inner surfaces 220A, 222A of the substrates 220, 222 respectively as illustrated by example with respect to FIG. 7A, and references to voltages applied to any specific one or ones of the electrically conductive pads P1-P12 will be understood as being applied to both such opposed, juxtaposed, spaced-apart pairs of electrically conductive pads as illustrated by example with respect to FIGS. 7B and 7C. It will be further understood that the DC voltage V.sub.REF illustrated in FIGS. 8A-8F may be any positive or negative voltage, or may be zero volts, e.g., ground potential, and that the DC voltage −XV also illustrated in FIGS. 8A-8F may be any voltage, positive, negative or zero voltage that is less than V.sub.REF so as to establish a corresponding electric field within the channel 225 which extends in a direction from electrically conductive pads controlled to V.sub.REF toward electrically conductive pads controlled to −XV as illustrated by example in FIGS. 7B and 7C.

(77) With reference to FIG. 8A, the processor 210 is operable to control the voltage source V.sub.ST to apply −XV to each of the pads P5-P7, and the apply V.sub.REF to each of the pads P1-P4. In some implementation, V.sub.ST applies V.sub.REF to each of the pads P9-P12 as depicted in FIG. 8A, although in other implementations V.sub.ST may be controlled to apply −XV to each of the pads P9-P12. In any case, the electric field resulting within the channel 225 of the ion steering array 208 from such voltage applications guides ions exiting the ion aperture IA of the ion source 12 through the channel 225 in the unaltered direction of ion travel along the illustrated ion trajectory 250.

(78) With reference to FIG. 8B, the processor 210 is subsequently operable to control the voltage source V.sub.ST to switch the voltages applied to pads P2 and P4 to −XV, and to otherwise maintain the previously applied voltages at P1, P3 and P5-P12. The electric field established in the channel 225 of the ion steering array 208 resulting from such switched voltage applications steers ions previously traveling from the ion source 12 in the unaltered direction of ion travel along the ion trajectory 250 illustrated in FIG. 8A along the altered direction of ion travel along the ion trajectory 252 toward the ion inlet aperture AI.sub.1 of M1 of the ELIT 202. At the same time, prior to or after this switch, the processor 210 is operable to control the voltage sources V1 and V2 to produce voltages which cause both ion mirrors M1 and M2 to operate in their ion transmission modes, e.g., as described with respect to FIGS. 1-2B. As a result, ions traveling through the channel 225 of the ion steering array 208 along the ion trajectory 252 are directed into the inlet aperture AI.sub.1 of the ELIT 202 through M1, and are guided by the ion transmission fields established in each of the ion mirrors M1 and M2 through M1, through the charge detection cylinder CD1 and through M2, as also illustrated by the ion trajectory 252 depicted in FIG. 8B. In some embodiments, one or more conventional ion carpets and/or other conventional ion focusing structures may be operatively positioned between the ion steering array 208 and the ion mirror M1 of the ELIT 202 to direct ions traveling along the ion trajectory 252 into the ion inlet aperture AI.sub.1 of the ELIT 202. In any case, the processor 210 is operable at some point thereafter to control V2 to produce voltages which cause the ion mirror M2 to switch from the ion transmission mode of operation to the ion reflection mode of operation, e.g., as also described with respect to FIGS. 1-2B, so as to reflect ions back toward M1. The timing of this switch of M2 illustratively depends on whether the operation of the ELIT 202 is being controlled by the processor 210 in random trapping mode or in trigger trapping mode as described with respect to FIG. 3.

(79) With reference to FIG. 8C, the processor 210 is subsequently operable to control the voltage source V1 to produce voltages which cause the ion mirror M1 to switch from ion transmission mode to ion reflection mode of operation. The timing of this switch of M1 illustratively depends on whether the operation of the ELIT 202 is being controlled by the processor 210 in random trapping mode or in trigger trapping mode as described with respect to FIG. 3, but in any case the switch of M1 to its ion reflection mode traps an ion within the ELIT 202 as illustrated by the ion trajectory 252 depicted in FIG. 8C. With an ion trapped within the ELIT 202 and with both M1 and M2 controlled by the voltage sources V1 and V2 respectively to operate in their ion reflection modes, the ion trapped within the ELIT 202 oscillates back and forth between the ion mirrors M1 and M2, each time passing through the charge detection cylinder CD1 and inducing a corresponding charge thereon which is detected by the charge preamplifier CP1 and recorded by the processor 210 in the memory 212 as described above with respect to FIG. 3.

(80) At the same time or following control of the ELIT 202 as just described, and with the ion oscillating within the ELIT 202 back and forth between the ion mirrors M1, M2, the processor 210 is operable to control V.sub.ST to switch the voltages applied to pads P2 and P4 back to V.sub.REF, to switch the voltages applied to pads P5-P8 from −XV to V.sub.REF and to switch the voltages applied to pads P9-P12 from V.sub.REF to −XV, as also illustrated in FIG. 8C. The electric field resulting in the channel 225 of the ion steering array 208 from such voltage applications again guides ions exiting the ion aperture IA of the ion source 12 through the channel 225 in the unaltered direction of ion travel along the illustrated ion trajectory 250.

(81) With reference now to FIG. 8D, the processor 210 is subsequently operable to control the voltage source V.sub.ST to switch the voltages applied to pads P6 and P8 to −XV, and to otherwise maintain the previously applied voltages at P1-P4, P5, P7 and P9-P12. The electric field established within the channel 225 of the ion steering array 208 resulting from such switched voltage applications steers ions previously traveling from the ion source 12 in the unaltered direction of ion travel along the ion trajectory 250 illustrated in FIG. 8C along the altered direction of ion travel along the ion trajectory 254 toward the ion inlet aperture AI.sub.2 of M2 of the ELIT 204. At the same time, prior to or after this switch, the processor 210 is operable to control the voltage sources V3 and V4 to produce voltages which cause both ion mirrors M3 and M4 to operate in their ion transmission modes. As a result, ions traveling through the channel 225 of the ion steering array 208 along the ion trajectory 254 are directed into the inlet aperture AI.sub.2 of the ELIT 204 through M3, and are guided by the ion transmission fields established in each of the ion mirrors M3 and M4 through M3, through the charge detection cylinder CD2 and through M4, as also illustrated by the ion trajectory 254 depicted in FIG. 8D. In some embodiments, one or more conventional ion carpets and/or other conventional ion focusing structures may be operatively positioned between the ion steering array 208 and the ion mirror M3 of the ELIT 204 to direct ions traveling along the ion trajectory 254 into the ion inlet aperture AI.sub.2 of the ELIT 204. In any case, the processor 210 is operable at some point thereafter to control V4 to produce voltages which cause the ion mirror M4 to switch from the ion transmission mode of operation to the ion reflection mode of operation so as to reflect ions back toward M3. The timing of this switch of M4 illustratively depends on whether the operation of the ELIT 204 is being controlled by the processor 210 in random trapping mode or in trigger trapping mode as described with respect to FIG. 3.

(82) Following the operating state illustrated in FIG. 8D, the processor 210 is operable, similarly as described with respect to FIG. 8C, to control the voltage source V3 to produce voltages which cause the ion mirror M3 to switch from ion transmission mode to ion reflection mode of operation. The timing of this switch of M3 illustratively depends on whether the operation of the ELIT 204 is being controlled by the processor 210 in random trapping mode or in trigger trapping mode as described with respect to FIG. 3, but in any case the switch of M3 to its ion reflection mode traps an ion within the ELIT 204 as illustrated by the ion trajectory 254 depicted in FIG. 8E. With an ion trapped within the ELIT 204 and with both M3 and M4 controlled by the voltage sources V3 and V4 respectively to operate in their ion reflection modes, the ion trapped within the ELIT 204 oscillates back and forth between the ion mirrors M3 and M4, each time passing through the charge detection cylinder CD2 and inducing a corresponding charge thereon which is detected by the charge preamplifier CP2 and recorded by the processor 210 in the memory 212 as described above with respect to FIG. 3. In the operating state illustrated in FIG. 8E, ions are simultaneously oscillating back and forth within each of the ELITs 202 and 204, and ion charge/timing measurements taken from each of the charge preamplifiers CP1 and CP2 are therefore simultaneously collected and stored by the processor 210.

(83) At the same time or following control of the ELIT 204 as just described with respect to FIG. 8E, and with an ion oscillating simultaneously within each of the ELITs 202 and 204, the processor 210 is operable to control V.sub.ST to switch the voltages applied to pads P6 and P8 back to V.sub.REF, so that the pads P1-P12 are controlled to the voltages illustrated in FIG. 8C. The electric field resulting in the channel 225 of the ion steering array 208 from such voltage applications again guides ions exiting the ion aperture IA of the ion source 12 through the channel 225 in the unaltered direction of ion travel along the illustrated ion trajectory 250 as illustrated in FIG. 8C. Thereafter, the processor 210 is operable to control the voltage source V.sub.ST to switch the voltages applied to pads P9 and P11 to V.sub.REF, and to otherwise maintain the previously applied voltages at P1-P8, P5 and P11-P12. The electric field established within the channel 225 of the ion steering array 208 resulting from such switched voltage applications steers ions previously traveling from the ion source 12 in the unaltered direction of ion travel along the ion trajectory 250 illustrated in FIG. 8C along the altered direction of ion travel along the ion trajectory 256 toward the ion inlet aperture AI.sub.3 of the ion mirror M5 of the ELIT 206. At the same time, prior to or after this switch, the processor 210 is operable to control the voltage sources V5 and V6 to produce voltages which cause both ion mirrors M5 and M6 to operate in their ion transmission modes. As a result, ions traveling through the channel 225 of the ion steering array 208 along the ion trajectory 253 are directed into the inlet aperture AI.sub.3 of the ELIT 206 through M5, and are guided by the ion transmission fields established in each of the ion mirrors M5 and M6 through M5, through the charge detection cylinder CD3 and through M6, as illustrated by the ion trajectory 256 depicted in FIG. 8E. In some embodiments, one or more conventional ion carpets and/or other conventional ion focusing structures may be operatively positioned between the ion steering array 208 and the ion mirror M5 of the ELIT 206 to direct ions traveling along the ion trajectory 256 into the ion inlet aperture AI.sub.3 of the ELIT 206.

(84) In any case, the processor 210 is operable at some point thereafter to control V6 to produce voltages which cause the ion mirror M6 to switch from the ion transmission mode of operation to the ion reflection mode of operation so as to reflect ions back toward M5. The timing of this switch of M6 illustratively depends on whether the operation of the ELIT 206 is being controlled by the processor 210 in random trapping mode or in trigger trapping mode as described with respect to FIG. 3. Thereafter, the processor 210 is operable, similarly as described with respect to FIG. 8C, to control the voltage source V5 to produce voltages which cause the ion mirror M5 to switch from ion transmission mode to ion reflection mode of operation. The timing of this switch of M5 illustratively depends on whether the operation of the ELIT 206 is being controlled by the processor 210 in random trapping mode or in trigger trapping mode as described with respect to FIG. 3, but in any case the switch of M5 to its ion reflection mode traps an ion within the ELIT 206 as illustrated by the ion trajectory 256 depicted in FIG. 8F. With an ion trapped within the ELIT 206 and with both M5 and M6 controlled by the voltage sources V5 and V6 respectively to operate in their ion reflection modes, the ion trapped within the ELIT 206 oscillates back and forth between the ion mirrors M5 and M6, each time passing through the charge detection cylinder CD3 and inducing a corresponding charge thereon which is detected by the charge preamplifier CP3 and recorded by the processor 210 in the memory 212 as described above with respect to FIG. 3. In the operating state illustrated in FIG. 8F, an ion is simultaneously oscillating back and forth within each of the ELITs 202, 204 and 206, and ion charge/timing measurements taken from each of the charge preamplifiers CP1, CP2 and CP3 are therefore simultaneously collected and stored by the processor 210.

(85) As also illustrated in FIG. 8F, at the same time or following control of the ELIT 206 as just described, and with the ions oscillating simultaneously within each of the ELITs 202, 204 and 206, the processor 210 is operable to control V.sub.ST to switch the voltages applied to pads P5-P8 to −XV and to switch the voltages applied to P10 and P12 to V.sub.REF (or to switch the voltages applied to P9 and P11 to −XV), so that the pads P1-P12 are controlled to the voltages illustrated in (or as described with respect to) FIG. 8A. The electric field resulting in the channel 225 of the ion steering array 208 from such voltage applications again guides ions exiting the ion aperture IA of the ion source 12 through the channel 225 in the unaltered direction of ion travel along the illustrated ion trajectory 250 as illustrated in FIG. 8A.

(86) After the ions have oscillated back and forth within each of the ELITs 202, 204 and 206 for a total ion cycle measurement time or a total number of measurement cycles, e.g., as described above with respect to step 126 of the process 100 illustrated in FIG. 3, the processor 210 is operable to control the voltage sources V1-V6 to switch each of the ion mirrors M1-M6 to their ion transmission operating modes, thereby causing the ions trapped therein to exit the ELITs 202, 204, 206 via the ion outlet apertures AO.sub.1-AO.sub.3 respectively. Operation of the CDMS 200 then illustratively returns to that described above with respect to FIG. 8B. At the same time, or at another convenient time, the collections of recorded ion charge/timing measurements are processed by the processor 210, e.g., as described with respect step 140 of the process 100 illustrated in FIG. 3, to determine the charge, mass-to-charge ratio and mass value of each ion processed by a respective one of the ELITs 202, 204, 206.

(87) Depending upon a number of factors including, but not limited to, the dimensions of the ELITS 202, 204, 206, the frequency or frequencies of oscillation of ions through each ELIT 202, 204, 206 and the total number of measurement cycles/total ion cycle measurement time in each ELIT 202, 204, 206, ions may simultaneously oscillate back and forth within at least two of the ELITs 202, 204 and 206, and ion charge/timing measurements taken from respective ones of the charge preamplifiers CP1, CP2 and CP3 may therefore be simultaneously collected and stored by the processor 210. In the embodiment illustrated in FIG. 8F, for example, ions simultaneously oscillate back and forth within at least two of the ELITs 202, 204 and 206, and ion charge/timing measurements taken from each of the charge preamplifiers CP1, CP2 and CP3 are thus simultaneously collected and stored by the processor 210. In other embodiments, the total number of measurement cycles or total ion cycle measurement time of ELIT 202 may expire before at least one ion is trapped within the ELIT 206 as described above. In such cases the processor 210 may control the voltage sources V1 and V2 to switch the ion mirrors M1 and M2 to their transmission operating modes, thereby causing the ion(s) oscillating therein to exit through the ion mirror M2 before an ion is made to oscillate within the ELIT 206. In such embodiments, ions may not simultaneously oscillate back and forth within all of the ELITs 202, 204 and 206, but may rather simultaneously oscillation back and for within at least two of the ELITs 202, 204 and 206 at any one time.

(88) Referring now to FIG. 9, another CDMS 300 is shown including yet another embodiment of an electrostatic linear ion trap (ELIT) array 302 with control and measurement components coupled thereto. In the illustrated embodiment, the ELIT array 302 includes three separate ELITs E1-E3 each configured identically to the ELITs 202, 204, 206 illustrated in FIG. 6. In the embodiment illustrated in FIG. 9, a voltage source V1, illustratively identical in structure and function to the voltage source V1 illustrated in FIGS. 1-2B, is operatively coupled to the ion mirror M1 of each ELIT E1-E3 and another voltage source V2, illustratively identical in structure and function to the voltage source V4 illustrated in FIGS. 1-2B, is operatively coupled to the ion mirror M2 of each ELIT E1-E3. In alternate embodiments, the ion mirrors M1 of two or more of the ELITs E1-E3 may be merged into a single ion mirror and/or the ion mirrors M2 of two or more of the ELITs E1-E3 may be merged into a single ion mirror. In any case, the voltage sources V1, V2 are electrically coupled to a processor 304, and the three charge preamplifiers CP1-CP3 are electrically coupled between the processor 304 and a respective charge detection cylinder CD1-CD3 of a respective one of the ELITs E1-E3. A memory 306 illustratively includes instructions which, when executed by the processor 304, cause the processor 304 to control the voltage sources V1 and V2 to control operation of the ELITs E1-E3 as described below. Illustratively, the processor 304 is operatively coupled to one or more peripheral devices 308 which may be identical to the one or more peripheral devices 20 described above with respect to FIG. 1.

(89) The CDMS 300 is identical in some respects to the CDMS 200 in that the CDMS 300 includes an ion source 12 operatively coupled to an ion steering array 208, the structures and operation of which are as described above. The instructions store in the memory 306 further illustratively include instructions which, when executed by the processor 304, cause the processor 304 to control the ion steering array voltage source V.sub.ST as described below.

(90) In the embodiment illustrated in FIG. 9, the CDMS 300 further illustratively includes three conventional ion traps IT1-IT3 each having a respective ion inlet TI.sub.1-TI.sub.3 and an opposite ion outlet TO.sub.1-TO.sub.3. The ion trap IT1 is illustratively positioned between the set of electrically conductive pads P1-P4 and the ion mirror M1 of the ELIT E1 such that the longitudinal axis 24.sub.1 extending centrally through the ELIT E1 bisects the ion inlet T.sub.1 and the ion outlet TO.sub.1 of IT1 and also passes centrally between the pad pairs P1/P2 and P3/P4 as illustrated in FIG. 9. The ion trap IT2 is similarly positioned between the set of electrically conductive pads P5-P8 and the ion mirror M1 of the ELIT E2 such that the longitudinal axis 24.sub.2 extending centrally through the ELIT E2 bisects the ion inlet TI.sub.2 and the ion outlet TO.sub.2 of IT2 and also passes centrally between the pad pairs P5/P6 and P7/P8, and the ion trap IT3 is likewise positioned between the set of electrically conductive pads P9-P12 and the ion mirror M1 of the ELIT E3 such that the longitudinal axis 24.sub.3 extending centrally through the ELIT E3 bisects the ion inlet TI.sub.3 and the ion outlet TO.sub.3 of IT3 and also passes centrally between the pad pairs P9/P10 and P11/P12. The ion traps IT1-IT3 may each be any conventional ion trap, examples of which may include, but are not limited to, a conventional quadrupole ion trap, a conventional hexapole ion trap, or the like.

(91) An ion trap voltage source V.sub.IT is operatively coupled between the processor 304 and each of the ion traps IT1-IT3. The voltage source V.sub.IT is illustratively configured to produce suitable DC and AC, e.g., RF, voltages for separately and individually controlling operation of each of the ion traps IT1-IT3 in a conventional manner.

(92) The processor 304 is illustratively configured, e.g. programmed, to control the ion steering array voltage source V.sub.ST to sequentially steer one or more ions exiting the ion aperture IA of the ion source 12, as described with respect to FIGS. 8A-8F, into the ion inlets TI.sub.1-TI.sub.3 of the each of the respective ion traps IT1-IT3. In some embodiments, one or more conventional ion carpets and/or other ion focusing structures may be positioned between the ion steering array 208 and one or more of the ion traps IT1-IT3 to direct ions from the ion steering array 208 into the ion inlets T.sub.1-TI.sub.3 of the respective ion traps IT1-IT3. The processor 304 is further configured, e.g., programmed, to control the ion trap voltage source V.sub.IT to produce corresponding control voltages for controlling the ion inlets TI.sub.1-TI.sub.3 of the ion traps IT1-IT3 to accept ions therein, and for controlling the ion traps IT1-IT3 in a conventional manner to trap and confine such ions therein.

(93) As the ion traps IT1-IT3 are being filled with ions, the processor 304 is configured, i.e., programmed, to control V1 and V2 to produce suitable DC voltages which control the ion mirrors M1 and M2 of the ELIT E1-E2 to operate in their ion transmission operating modes so that any ions moving therein exit via the ion outlet apertures AO.sub.1-AO.sub.3 respectively. When, via control of the ion steering array 208 and the ion traps IT1-IT3 as just described, at least one ion is trapped within each of the ion traps IT1-IT3, the processor 304 is configured, i.e., programmed, to control V2 to produce suitable DC voltages which control the ion mirrors M2 of the ELITs E1-E3 to operate in their ion reflection operating modes. Thereafter, the processor 304 is configured to control the ion trap voltage source V.sub.IT to produce suitable voltages which cause the ion outlets TO.sub.1-TO.sub.3 of the respective ion traps IT1-IT3 to simultaneously open to direct an ion trapped therein into a respective one of the ELITs E1-E3 via a respective ion inlet aperture AI.sub.1-AI.sub.3 of a respective ion mirror M1. When the processor 304 determines that an ion has entered each ELIT E1-E3, e.g., after passage of some time period following simultaneous opening of the ion traps IT1-IT3 or following charge detection by each of the charge preamplifiers CP1-CP3, the processor 304 is operable to control the voltage source V1 to produce suitable DC voltages which control the ion mirrors M1 of the ELTs E1-E3 to operate in their ion reflection operating modes, thereby trapping an ion within each of the ELITs E1-E3.

(94) With the ion mirrors M1 and M2 of each ELIT E1-E3 operating in the ion reflection operating mode, the ion in each ELIT E1-E3 simultaneously oscillates back and forth between M1 and M2, each time passing through a respective one of the charge detection cylinders CD1-CD3. Corresponding charges induced on the charge detection cylinders CD1-CD3 are detected by the respective charge preamplifiers CP1-CP3, and the charge detection signals produced by the charge preamplifiers CP1-CP3 are stored by the processor 304 in the memory 306 and subsequently processed by the processor 304, e.g., as described with respect step 140 of the process 100 illustrated in FIG. 3, to determine the charge, mass-to-charge ratio and mass value of each ion processed by a respective one of the ELITs E1-E3.

(95) Although the embodiments of the CDMS 200 and 300 are illustrated in FIGS. 6-8F and 9 respectively as each including three ELITs, it will be understood that either or both such systems 200, 300 may alternatively include fewer, e.g., 2, or more, e.g., 4 or more, ELITs. Control and operation of the various components in any such alternate embodiments will generally follow the concepts described above, and those skilled in the art will recognize that any modifications to the system 200 and/or to the system 300 required to realize any such alternate embodiment(s) will involve only mechanical steps. Additionally, although the embodiments of the CDMS systems 200 and 300 are illustrated in FIGS. 6-8F and 9 respectively as each including an example ion steering array 208, it will be understood that one or more other ion guiding structures may be alternatively or additionally used to steer or guide ions as described above, and that any such alternate ion guiding structure(s) is/are intended to fall within the scope of this disclosure. As one non-limiting example, an array of DC quadrupole beam deflectors may be used with either or both of the systems 200, 300 to steer or guide ions as described. In such embodiments, one or more focusing lenses and/or ion carpets may also be used to focus ions into the various ion traps as described above.

(96) It will be understood that the dimensions of the various components of any of the ELIT arrays 14, 205, 302 and the magnitudes of the electric fields established therein in any of the systems 10, 60, 80, 200, 300 illustrated in the attached figures and described above may illustratively be selected to establish a desired duty cycle of ion oscillation within one or more of the ELITs or ELIT regions E1-E3, corresponding to a ratio of time spent by an ion in the respective charge detection cylinder CD1-CD3 and a total time spent by the ion traversing the combination of the corresponding ion mirrors and the respective charge detection cylinder CD1-CD3 during one complete oscillation cycle. For example, a duty cycle of approximately 50% may be desirable in one or more of the ELITs or ELIT regions for the purpose of reducing noise in fundamental frequency magnitude determinations resulting from harmonic frequency components of the measure signals. Details relating to such dimensional and operational considerations for achieving a desired duty cycle, e.g., such as 50%, are illustrated and described in U.S. Patent Application Ser. No. 62/616,860, filed Jan. 12, 2018, U.S. Patent Application Ser. No. 62/680,343, filed Jun. 4, 2018 and co-pending International Patent Application No. PCT/US2019/013251, filed Jan. 11, 2019, all entitled ELECTROSTATIC LINEAR ION TRAP DESIGN FOR CHARGE DETECTION MASS SPECTROMETRY, the disclosures of which are all expressly incorporated herein by reference in their entireties.

(97) It will be further understood that one or more charge calibration or resetting apparatuses may be used with the charge detection cylinder(s) of any one or more of the ELIT arrays 14, 205, 302 and/or in any one or more of the regions E1-E3 of the ELIT array 14 in any of the systems 10, 60, 80, 200, 300 illustrated in the attached figures and described herein. An example of one such charge calibration or resetting apparatus is illustrated and described in U.S. Patent Application Ser. No. 62/680,272, filed Jun. 4, 2018 and in International Patent Application No. PCT/US2019/013284, filed Jan. 11, 2019, both entitled APPARATUS AND METHOD FOR CALIBRATING OR RESETTING A CHARGE DETECTOR, the disclosures of which are both expressly incorporated herein by reference in their entireties.

(98) It will be further understood that one or more charge detection optimization techniques may be used with any one or more of the ELIT arrays 14, 205, 302 and/or with one or more regions E1-E3 of the ELIT array 14 in any of the systems 10, 60, 80, 200, 300 illustrated in the attached figures and described herein, e.g., for trigger trapping or other charge detection events. Examples of some such charge detection optimization techniques are illustrated and described in U.S. Patent Application Ser. No. 62/680,296, filed Jun. 4, 2018 and in co-pending International Patent Application No. PCT/US2019/13280, filed Jan. 11, 2019, both entitled APPARATUS AND METHOD FOR CAPTURING IONS IN AN ELECTROSTATIC LINEAR ION TRAP, the disclosures of which are both expressly incorporated herein by reference in their entireties.

(99) It will be further still understood that one or more ion source optimization apparatuses and/or techniques may be used with one or more embodiments of the ion source 12 in any of the systems 10, 60, 80, 200, 300 illustrated in the attached figures and described herein, some examples of which are illustrated and described in U.S. Patent Application Ser. No. 62/680,223, filed Jun. 4, 2018 and entitled HYBRID ION FUNNEL-ION CARPET (FUNPET) ATMOSPHERIC PRESSURE INTERFACE FOR CHARGE DETECTION MASS SPECTROMETRY, and in International Patent Application No. PCT/US2019/013274, filed Jan. 11, 2019 and entitled INTERFACE FOR TRANSPORTING IONS FROM AN ATMOSPHERIC PRESSURE ENVIRONMENT TO A LOW PRESSURE ENVIRONMENT, the disclosures of which are both expressly incorporated herein by reference in their entireties.

(100) It will be still further understood that any of the systems 10, 60, 80, 200, 300 illustrated in the attached figures and described herein may be implemented in accordance with real-time analysis and/or real-time control techniques, some examples of which are illustrated and described in U.S. Patent Application Ser. No. 62/680,245, filed Jun. 4, 2018 and International Patent Application No. PCT/US2019/013277, filed Jan. 11, 2019, both entitled CHARGE DETECTION MASS SPECTROMETRY WITH REAL TIME ANALYSIS AND SIGNAL OPTIMIZATION, the disclosures of which are both expressly incorporated herein by reference in their entireties.

(101) It will be yet further understood that in any of the systems 10, 60, 80, 200, 300 illustrated in the attached figures and described herein, one or more ion inlet trajectory control apparatuses and/or techniques may be implemented to provide for simultaneous measurements of multiple individual ions within one or more of the ELITs or ELIT regions of any of the ELIT arrays illustrated in the attached figures and described herein. Examples of some such ion inlet trajectory control apparatuses and/or techniques are illustrated and described in U.S. Patent Application Ser. No. 62/774,703, filed Dec. 3, 2018 and in International Patent Application No. PCT/US2019/013285, filed Jan. 11, 2019, both entitled APPARATUS AND METHOD FOR SIMULTANEOUSLY ANALYZING MULTIPLE IONS WITH AN ELECTROSTATIC LINEAR ION TRAP, the disclosures of which are both expressly incorporated herein by reference in their entireties.

(102) While this disclosure has been illustrated and described in detail in the foregoing drawings and description, the same is to be considered as illustrative and not restrictive in character, it being understood that only illustrative embodiments thereof have been shown and described and that all changes and modifications that come within the spirit of this disclosure are desired to be protected.