ELECTRICAL POWER CONVERTER

Abstract

Electrical converters of the present disclosure feature a boost circuit that is fully integrated with a three phase bridge rectifier to allow for obtaining a pulsed voltage at the rectifier output. Actively switchable semiconductor switches of the boost circuit are controlled by pulse width modulation (PWM) control signals to obtain the pulsed voltage. PWM of this pulsed voltage allows control of two out of three currents at the three input terminals of the rectifier, i.e., the currents at the phase inputs having the highest and the lowest voltage levels of the three phase input voltage.

Claims

1. An electrical converter for converting a three-phase AC input into a DC output, the electrical converter comprising: three phase input terminals and two output terminals, a three phase bridge rectifier having an input connected to the phase input terminals and an output connected to an upper intermediate node and a lower intermediate node, the three phase bridge rectifier comprising first semiconductor switches, a boost circuit comprising boost inductors, at least one second semiconductor switch that is actively switchable and at least one third semiconductor switch, wherein the at least one second semiconductor switch and the at least one third semiconductor switch are connected in series across the output terminals, an output filter comprising a filter capacitor connected between the boost circuit and the output terminals, and a controller operably connected to the at least one second semiconductor switch, wherein the boost inductors are connected between the phase input terminals and the three phase bridge rectifier, wherein the at least one second semiconductor switch is connected across the upper intermediate node and the lower intermediate node, and wherein the controller is configured to control the at least one second semiconductor switch via pulse width modulation allowing for obtaining a pulsed intermediate voltage between the upper intermediate node and the lower intermediate node having a modulated pulse width, wherein the first semiconductor switches are actively switchable, and wherein the controller is operably connected to the first semiconductor switches to control switching of the first semiconductor switches according to a switching pattern wherein the phase input terminal having an intermediate voltage between a highest voltage and a lowest voltage is alternatingly connected to the upper intermediate output node and the lower intermediate output node.

2. The electrical converter of claim 1, wherein the electrical converter is free of energy storage elements between the three phase bridge rectifier and the output filter.

3. The electrical converter of claim 1, comprising a measurement processing unit configured to measure phase currents through the boost inductors, and wherein the controller comprises a current control loop coupled to the measurement processing unit configured to measure the phase currents and to the at least one second semiconductor switch, wherein the current control loop is configured to generate a second pulse width modulation control signal fed to the at least one second semiconductor switch based on the phase currents measured.

4. The electrical converter of claim 1, wherein the switching pattern is such that: the phase input terminal having a highest voltage is connected to the upper intermediate output node, and the phase input terminal having a lowest voltage is connected to the lower intermediate output node.

5. The electrical converter of claim 4, wherein the switching pattern comprises: the phase input terminal having a highest voltage is continuously connected to the upper intermediate output node, and the phase input terminal having a lowest voltage is continuously connected to the lower intermediate output node.

6. The electrical converter of claim 4, further comprising: a measurement processing unit configured to measure phase currents through the boost inductors, wherein the controller comprises a current control loop coupled to the measurement processing unit and to the at least one second semiconductor switch; wherein the current control loop is configured to generate a second pulse width modulation control signal fed to the at least one second semiconductor switch based on the phase currents measured; and wherein the current control loop is configured to generate a first pulse width modulation control signal fed to ones of the first semiconductor switches arranged to switch a phase connected to the phase input terminal having the intermediate voltage based on a respective one of the phase currents measured.

7. The electrical converter of claim 6, wherein the current control loop is configured to process the phase current measured in respect of the phase input terminal having the intermediate voltage to generate the first and second pulse width modulation control signals.

8. The electrical converter of claim 6, wherein the first and second pulse width modulation control signals are interleaved.

9. The electrical converter of claim 1, wherein the pulsed intermediate voltage is a square wave signal comprising at least two voltage levels, one of the at least two voltage levels being substantially 0 V.

10. The electrical converter of claim 1, comprising a neutral connection terminal for connecting a neutral conductor of the three-phase AC input, wherein the boost circuit comprises a common node, an upper boost bridge comprising a first one of the at least one second semiconductor switch connected across the upper intermediate output node and the common node, and a lower boost bridge comprising a second one of the at least one second semiconductor switch connected across the common node and the lower intermediate output node, wherein the common node is connected to the neutral connection terminal and to a midpoint of the output filter.

11. The electrical converter of claim 10, wherein the controller is configured to generate interleaved pulse width modulation control signals applied to the first one and to the second one of the at least one second semiconductor switch.

12. The electrical converter of claim 1, comprising a second measurement processing unit configured to measure voltages at the three phase input terminals and a third measurement processing unit configured to measure a voltage at the output terminals, both being coupled to the controller.

13. The electrical converter of claim 1, wherein the at least one third semiconductor switch, is actively switchable, wherein the at least one third semiconductor switch is arranged to allow for bidirectional power flow.

14. A wireless charging system for charging a battery of an electric vehicle, the wireless charging system comprising: a power supply unit, the power supply unit comprising the electrical converter of claim 1.

15. A magnetic resonance imaging apparatus comprising: a gradient amplifier, the gradient amplifier comprising the electrical converter of claim 1.

16. A method of converting a three phase AC input into a DC output in an electrical boost converter, the method comprising: rectifying the three phase AC input to obtain a rectified intermediate signal across an upper intermediate output node and a lower intermediate output node, wherein a phase of the three phase AC input having an intermediate voltage between a highest voltage and a lowest voltage of the three phase AC input is alternatingly applied to the upper intermediate output node and the lower intermediate output node, boosting the rectified intermediate voltage to obtain the DC output across an output filter comprising a filter capacitor, wherein boosting the rectified intermediate voltage comprises controlled switching of the rectified intermediate voltage signal by pulse width modulation to obtain a pulsed voltage signal, and applying the pulsed voltage signal across the output filter, wherein boost energy is stored in boost inductors connected to the three phase AC input prior to rectifying.

17. The method of claim 16, wherein rectifying the three phase AC input comprises measuring the three phase AC input and determining a first phase having a highest voltage, a second phase having a lowest voltage, and a third phase having the intermediate voltage between the highest voltage and the lowest voltage, continuously applying the first phase to the upper intermediate output node, and continuously applying the second phase to the lower intermediate output node.

18. The method of claim 16, wherein a current through the boost inductors is measured and controlled via adapting a pulse width modulation control signal applied in the controlled switching step.

19. The method of claim 16, wherein no energy is stored between the rectifying and controlled switching steps.

20. The method of claim 16, wherein the pulsed voltage is a square wave signal comprising at least two voltage levels, one of the at least two voltage levels being substantially 0 V.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Aspects of the present disclosure will now be described in more detail with reference to the appended drawings, wherein same reference numerals illustrate same features and wherein:

[0028] FIG. 1 schematically shows an electrical converter that has a neutral connection terminal and that is unidirectional according to an embodiment of the present disclosure.

[0029] FIG. 2A shows a diagram of voltages during a 360° period of the AC mains voltage, and illustrates the overall operating principle of the electrical converter according to an embodiment of the present disclosure.

[0030] FIG. 2B shows a diagram of currents during a 360° period of the AC mains voltage, and illustrates the overall operating principle of the electrical converter according to an embodiment of the present disclosure.

[0031] FIG. 2C shows a diagram of switching states of the rectifier switches during a 360° period of the AC mains voltage, and illustrates the overall operating principle of the electrical converter according to an embodiment of the present disclosure.

[0032] FIG. 2D shows a diagram of switching states of the boost circuit switches during a 360° period of the AC mains voltage, and illustrates the overall operating principle of the electrical converter according to an embodiment of the present disclosure.

[0033] FIG. 3 shows a block diagram of an advantageous implementation of a central control unit and control method according to an embodiment of the present disclosure.

[0034] FIG. 4A shows a first diagram with voltages, currents and switching states within five consecutive switching cycles of the bridge legs of the electrical converter, and illustrates the PWM modulation of the bridge legs of the electrical converter according to an embodiment of the present disclosure.

[0035] FIG. 4B shows a second diagram with voltages, currents and switching states within five consecutive switching cycles of the bridge legs of the electrical converter, and illustrates the PWM modulation of the bridge legs of the electrical converter according to an embodiment of the present disclosure.

[0036] FIG. 4C shows a third diagram with voltages, currents and switching states within five consecutive switching cycles of the bridge legs of the electrical converter, and illustrates the PWM modulation of the bridge legs of the electrical converter according to an embodiment of the present disclosure.

[0037] FIG. 5A shows a diagram with voltages of the electrical converter for a 360° period of the AC mains voltage and for five consecutive switching cycles of the bridge legs of the electrical converter, and illustrate the ‘switched’ nature of the voltage potential of the upper intermediate voltage node x and the lower intermediate voltage node y of the electrical converter according to an embodiment of the present disclosure.

[0038] FIG. 5B shows a diagram with currents of the electrical converter for a 360° period of the AC mains voltage and for five consecutive switching cycles of the bridge legs of the electrical converter, and illustrate the ‘switched’ nature of the voltage potential of the upper intermediate voltage node x and the lower intermediate voltage node y of the electrical converter according to an embodiment of the present disclosure.

[0039] FIG. 6 shows diagrams with voltages, currents and switching states during a 360° period of the AC mains voltage, and illustrates the overall operating principle of the electrical converter according to an embodiment of the present disclosure.

[0040] FIG. 7 schematically shows an electrical converter that has a neutral connection terminal and that is bidirectional according to an embodiment of the present disclosure.

[0041] FIG. 8 schematically shows an electrical converter that has no neutral connection terminal, that is unidirectional, and that has an output power stage comprising one single bridge leg according to an embodiment of the present disclosure.

[0042] FIG. 9 schematically shows an electrical converter that has no neutral connection terminal, that is bidirectional, and that has an output power stage comprising one single bridge leg according to an embodiment of the present disclosure.

[0043] FIG. 10A shows a first variant of the rectifier power stage of the electrical converter, comprising bridge legs that are three-level half-bridges according to an embodiment of the present disclosure.

[0044] FIG. 10B shows a second variant of the rectifier power stage of the electrical converter, comprising bridge legs that are three-level half-bridges according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

[0045] FIG. 1 shows an electrical converter 10, referred to as the BELGIAN RECTIFIER, comprising two power stages 11, 12 in the form of a three-phase active rectifier stage 11 and an output power stage 12. Electrical converter 10 further comprises an input filter 13, and an output filter 14.

[0046] The electrical converter 10 is an AC-to-DC converter that has three phase inputs a, b, c which are connected to a three-phase voltage of a three-phase AC grid 20, two DC outputs p, n which for example may be connected to a DC load 21 such as, for example, a high voltage (e.g. 800 V) battery of an electric car, and a terminal N for connecting the neutral conductor of the AC grid 20.

[0047] The two power stages 11, 12 may be seen as one ‘integrated’ conversion stage since no high-frequency filter capacitors are present between the two power stages and since both stages use common energy storage inductors (boost inductors). In particular, the phase inductors L.sub.a, L.sub.b, L.sub.c of the input filter 13 are used as boost inductors and are shared between both power stages 11, 12.

[0048] The rectifier stage 11 has three phase inputs ā, b, c that are connected to the three phase inputs a, b, c via the phase inductors L.sub.a, L.sub.b, L.sub.c of the input filter 13, and two outputs x, y. These outputs may be seen as an upper intermediate voltage node x, and a lower intermediate voltage node y, which show a ‘switched’ voltage potential caused by the switching of the output power stage 12.

[0049] The rectifier stage 11 consists of three bridge legs 15, 16, 17 which each comprise two actively switchable semiconductor devices (S.sub.xa, and S.sub.ay for leg 15, S.sub.xb and S.sub.by for leg 16, S.sub.xc and S.sub.cy, for leg 17) connected in the form of a half bridge configuration. Each switchable semiconductor device has an anti-parallel diode. In this example, Metal Oxide Field Effect Transistors (MOSFETs) are used for the actively switchable semiconductor devices, which each contain an internal anti-parallel body diode that may replace an external anti-parallel diode.

[0050] The output power stage consists of two stacked boost bridges 18, 19. Each boost bridge comprises a boost switch (S.sub.xm for the upper boost bridge 18 and S.sub.my for the lower boost bridge 19) and boost diode (D.sub.xp for the upper boost bridge 18 and D.sub.ny for the lower boost bridge 19) connected in a half-bridge configuration. The middle node of the upper boost bridge 18 is connected to intermediate voltage node x and the middle node of the lower boost bridge 19 is connected to intermediate voltage node y. The common node m of both boost stages 18, 19 is connected to the midpoint of the output filter 14 which comprises two output filter capacitors C.sub.pm, C.sub.mn that are connected in series between the upper output node p and the lower output node n.

[0051] The upper boost bridge 18 is connected between the upper output node p and the middle output node m (i.e. in parallel with the upper output filter capacitor C.sub.pm), and is arranged in a way that the intermediate voltage node x can be alternately connected to the middle output node m and the upper output node p by controlling switch S.sub.xm, wherein current can flow from the intermediate voltage node x to the upper output node p via the diode D.sub.xp when the switch S.sub.xm is opened (not conducting), and current can flow from the intermediate voltage node x to the middle output node m (or vice versa) via the switch S.sub.xm when the switch S.sub.xm is closed (conducting).

[0052] The lower boost bridge 19 is connected between the middle output node m and the lower output node n (i.e. in parallel with the lower output filter capacitor C.sub.mn), and is arranged in a way that the intermediate voltage node y can be alternately connected to the middle output node m and the lower output node n by controlling switch S.sub.my, wherein current can flow from the lower output node n to the intermediate voltage node y via the diode D.sub.ny when the switch S.sub.my is opened (not conducting), and current can flow from the middle output node m to the intermediate voltage node y (or vice versa) via the switch S.sub.my when the switch S.sub.my is closed (conducting).

[0053] The boost switches (S.sub.xm, S.sub.my) of the boost bridges 18, 19 are actively switchable semiconductor devices. In the example of FIG. 1, MOSFETs are used.

[0054] Three AC capacitors C.sub.a, C.sub.b, C.sub.c, which are part of the input filter 13, are interconnecting the phase inputs a, b, c in the form of a star-connection. Generally, it is advantageous that the three capacitors C.sub.a, C.sub.b, C.sub.c have substantially equal value in order to symmetrically load the AC grid.

[0055] The neutral conductor of the three-phase AC grid is connected to the neutral connection terminal N of the converter 10. This neutral connection terminal N is further connected to the star-point of the AC capacitors C.sub.a, C.sub.b, C.sub.c and to the common node m of the stacked boost bridges 18, 19 (and thus also to the midpoint of the output filter 14). This results in a fully symmetrical converter structure.

[0056] The bridge leg of the rectifier stage 11 that is connected with the phase input a, b, or c that has the highest voltage of the three-phase AC input voltage is switched in a way that the corresponding phase input a, b, or c is connected to the upper intermediate voltage node x via the corresponding phase inductor (L.sub.a, L.sub.b, or L.sub.c). To achieve this, the bridge leg connects the corresponding phase input ā, b, or c with the node x. As a result, a conventional DC/DC boost converter (upper boost converter) is formed by the AC capacitor (C.sub.a, C.sub.b, or C.sub.c) of the phase that has the highest voltage, the phase inductor (L.sub.a, L.sub.b, or L.sub.c) of the phase that has the highest voltage, the upper boost bridge 18, and the upper output capacitor C.sub.pm. The input voltage of this upper boost converter is the voltage v.sub.a, v.sub.b, or v.sub.c of the phase input a, b, or c that has the highest voltage level, and the output voltage of this upper boost converter is the voltage V.sub.pm across the upper output capacitor C.sub.pm, having a voltage value that is substantially equal to half the total DC bus voltage (V.sub.pm≈V.sub.DC/2). The formed upper boost converter might be operated by PWM modulation of the switch S.sub.xm, at a certain, possibly variable, switching frequency f.sub.s in order to control the current in the phase inductor (L.sub.a, L.sub.b, or L.sub.c) of the phase that has the highest voltage.

[0057] The bridge leg of the rectifier stage 11 that is connected with the phase input a, b, or c that has the lowest voltage of the three-phase AC input voltage is switched in a way that the corresponding phase input a, b, or c is connected to the lower intermediate voltage node y via the corresponding phase inductor (L.sub.a, L.sub.b, or L.sub.c). To achieve this, the bridge leg connects the corresponding phase input ā, b, or c with the node y. As a result, a conventional ‘inversed’ (negative input voltage and negative output voltage) DC/DC boost converter (lower boost converter) is formed by the AC capacitor (C.sub.a, C.sub.b, or C.sub.c) of the phase that has the lowest voltage, the phase inductor (L.sub.a, L.sub.b, or L.sub.c) of the phase that has the lowest voltage, the lower boost bridge 19, and the lower output capacitor C.sub.mn. The input voltage of this lower boost converter is the voltage v.sub.a, v.sub.b, or v.sub.c of the phase input a, b, or c that has the lowest voltage level, and the output voltage of this lower boost converter is the voltage V.sub.nm across the lower output capacitor C.sub.mn, having a voltage value that is substantially equal to minus half the total DC bus voltage (V.sub.nm≈−V.sub.DC/2). The formed lower boost converter might be operated by PWM modulation of the switch S.sub.my, at a certain, possibly variable, switching frequency f.sub.s in order to control the current in the phase inductor (L.sub.a, L.sub.b, or L.sub.c) of the phase that has the lowest voltage.

[0058] The bridge leg of the rectifier stage 11 that is connected with the phase input a, b, or c that has a voltage between the highest voltage and the lowest voltage of the three-phase AC input voltage is switched in a way that the corresponding phase input a, b, or c is alternately connected to the upper intermediate voltage node x and the lower intermediate voltage node y via the corresponding phase inductor (L.sub.a, L.sub.b, or L.sub.c). To achieve this, the bridge leg alternately connects the corresponding phase input ā, b, or c with the nodes x and y. The bridge leg of the rectifier stage 11 connected with the phase input a, b, or c that has a voltage between the highest voltage and the lowest voltage of the three-phase AC input voltage may be switched in a similar fashion as a single-phase half-bridge voltage-source converter (VSC), and is operated by PWM modulation of the switches of the bridge leg at a certain, possibly variable, switching frequency f.sub.s in order to control the current in the phase inductor (L.sub.a, L.sub.b, or L.sub.c) of the phase that has a voltage between the highest voltage and the lowest voltage of the three-phase AC input voltage.

[0059] In summary is can be said that two out of three bridge legs of the rectifier stage 11 are in a ‘selection state’, selecting which AC capacitor (C.sub.a, C.sub.b, or C.sub.c) and phase inductor (L.sub.a, L.sub.b, or L.sub.c) are part of the upper boost converter that contains upper boost bridge 18 and upper output capacitor C.sub.pm, and that is used to control the current in the phase inductor (L.sub.a, L.sub.b, or L.sub.c) of the phase input a, b, or c that has the highest voltage of the three-phase AC input voltage, and which AC capacitor (C.sub.a, C.sub.b, or C.sub.c) and phase inductor (L.sub.a, L.sub.b, or L.sub.c) are part of the lower boost converter that contains lower boost bridge 19 and lower output capacitor C.sub.mn, and that is used to control the current in the phase inductor (L.sub.a, L.sub.b, or L.sub.c) of the phase input a, b, or c that has the lowest voltage of the three-phase AC input voltage. The remaining bridge leg of the rectifier stage 11 is in an ‘active switching state’ and may be operated in a similar fashion as a single-phase half-bridge voltage-source converter (VSC). It forms a remaining switching circuit containing the remaining phase inductor (L.sub.a, L.sub.b, or L.sub.c) and the remaining phase capacitor (C.sub.a, C.sub.b, or C.sub.c) of the phase input a, b, or c that has a voltage between the highest voltage and the lowest voltage of the three-phase AC input voltage. The remaining switching circuit also contains the series connection of the two output capacitors C.sub.pm, C.sub.mn, and is used to control the current in the phase inductor (L.sub.a, L.sub.b, or L.sub.c) of the phase that has a voltage between the highest voltage and the lowest voltage of the three-phase AC input voltage.

[0060] In a three-phase AC grid with substantially balanced phase voltages, for example as shown in FIG. 2A, the assignment of the state of the bridge legs of the rectifier stage 11 (‘selection state’ and ‘active switching state’), as well as the assignment of the AC capacitors C.sub.a, C.sub.b, C.sub.c and phase inductors L.sub.a, L.sub.b, L.sub.c to the formed upper boost converter, the formed lower boost converter, and the formed remaining switching circuit changes every 60° sector of the three-phase AC input voltage depending on the voltage value of the phase inputs (a, b, c). This results in 6 unique assignments. The sequence of these assignments repeats itself every period (360°) of the AC mains voltage.

[0061] TABLE 1 summarizes the states (‘selection state’ and ‘active switching state’) of the bridge legs of the rectifier stage 11 during every 60° sector of the period (360°) of the AC mains voltage shown in FIG. 2A. Note that the switches of the bridge leg that is in the ‘active switching state’ are PMW modulated, as also indicated in TABLE 1 (switch ‘PWM modulated’.fwdarw.S=PWM). The switches of the bridge legs that are in the ‘selection state’ are either ‘on’ or ‘off’ during the particular sector, as also indicated in TABLE 1 (switch ‘on’.fwdarw.S=1, switch ‘off’:.fwdarw.S=0). The states of the switches of the rectifier stage 11 during every 60° sector of the period (360°) of the AC mains voltage are visualized in FIG. 2C, wherein only the states of the upper switches (S.sub.xa, S.sub.xb, S.sub.xc) of the rectifier stage 11 are shown whereas the states of the lower switches (S.sub.ay, S.sub.by, S.sub.cy) are complementary to those of the upper switches. Note that, in FIG. 2C, black-colored bars indicates PWM modulation of the corresponding switch. FIG. 2D shows the state of the switch S.sub.xm of the upper boost bridge 18 and the state of the switch S.sub.my of the lower boost bridge 19, which are both PWM modulated, as can be seen from the black-colored bars. An example of the currents i.sub.a, i.sub.b, i.sub.c in the phase inductors L.sub.a, L.sub.b, L.sub.c and the return current i.sub.N is shown in FIG. 2B. In this example the amplitudes of the phase inductor currents i.sub.a, i.sub.b, i.sub.c are equal and, as a result, the average return current i.sub.N is zero.

[0062] In correspondence with TABLE 1, for every 60° sector of the period (360°) of the AC mains voltage shown in FIG. 2A, TABLES 2-4 summarize, inter alia, the assignment of the phase capacitor (C.sub.a, C.sub.b, or C.sub.c) and phase inductors (L.sub.a, L.sub.b, or L.sub.c) to respectively the formed upper boost converter (containing upper boost bridge 18), the formed lower boost converter (containing lower boost bridge 19), and to the formed remaining switching circuit (containing the bridge leg of the rectifier that is in the ‘active switching state’).

TABLE-US-00001 TABLE 1 States of the bridge legs of the rectifier stage 11 and their switches. Sector Bridge leg 15 Bridge leg 16 Bridge leg 17  0°-60° Active switching state Selection state Selection state S.sub.x.sub.a & S.sub.a.sub.y = PWM S.sub.x.sub.b = 0, S.sub.b.sub.y = 1 S.sub.x.sub.c = 1, S.sub.c.sub.y = 0  60°-120° Selection state Selection state Active switching state (PWM) S.sub.x.sub.a = 1, S.sub.a.sub.y = 0 S.sub.x.sub.b = 0, S.sub.b.sub.y = 1 S.sub.x.sub.c & S.sub.c.sub.y = PWM 120°-180° Selection state Active switching state (PWM) Selection state S.sub.x.sub.a = 1, S.sub.a.sub.y = 0 S.sub.x.sub.b & S.sub.b.sub.y = PWM S.sub.x.sub.c = 0, S.sub.c.sub.y = 1 180°-240° Active switching state (PWM) Selection state Selection state S.sub.x.sub.a & S.sub.a.sub.y = PWM S.sub.x.sub.b = 1, S.sub.b.sub.y = 0 S.sub.x.sub.c = 0, S.sub.c.sub.y = 1 240°-300° Selection state Selection state Active switching state (PWM) S.sub.x.sub.a = 0, S.sub.a.sub.y = 1 S.sub.x.sub.b = 1, S.sub.b.sub.y = 0 S.sub.x.sub.c & S.sub.c.sub.y = PWM 300°-360° Selection state Active switching state (PWM) Selection state S.sub.x.sub.a = 0, S.sub.a.sub.y = 1 S.sub.x.sub.b & S.sub.b.sub.y = PWM S.sub.x.sub.c = 1, S.sub.c.sub.y = 0

TABLE-US-00002 TABLE 2 Assignment of circuit elements to the formed upper boost converter for every 60° sector of the period (360°) of the AC mains voltage. Involved input Involved AC Involved output Involved Sector inductor capacitor capacitor bridge leg  0°-60° L.sub.c C.sub.c C.sub.pm 18  60°-120° L.sub.a C.sub.a C.sub.pm 18 120°-180° L.sub.a C.sub.a C.sub.pm 18 180°-240° L.sub.b C.sub.b C.sub.pm 18 240°-300° L.sub.b C.sub.b C.sub.pm 18 300°-360° L.sub.c C.sub.c C.sub.pm 18

TABLE-US-00003 TABLE 3 Assignment of circuit elements to the formed lower boost converter for every 60° sector of the period (360°) of the AC mains voltage. Involved input Involved AC Involved output Involved Sector inductor capacitor capacitor bridge leg  0°-60° L.sub.b C.sub.b C.sub.mn 19  60°-120° L.sub.b C.sub.b C.sub.mn 19 120°-180° L.sub.c C.sub.c C.sub.mn 19 180°-240° L.sub.c C.sub.c C.sub.mn 19 240°-300° L.sub.a C.sub.a C.sub.mn 19 300°-360° L.sub.a C.sub.a C.sub.mn 19

TABLE-US-00004 TABLE 4 Assignment of circuit elements to the formed ‘remaining switching circuit’ for every 60° sector of the period (360°) of the AC mains voltage. Involved input Involved AC Involved output Involved Sector inductor capacitor capacitor bridge leg  0°-60° L.sub.a C.sub.a C.sub.pm & C.sub.mn 15  60°-120° L.sub.c C.sub.c C.sub.pm & C.sub.mn 17 120°-180° L.sub.b C.sub.b C.sub.pm & C.sub.mn 16 180°-240° L.sub.a C.sub.a C.sub.pm & C.sub.mn 15 240°-300° L.sub.c C.sub.c C.sub.pm & C.sub.mn 17 300°-360° L.sub.b C.sub.b C.sub.pm & C.sub.mn 16

[0063] As shown in FIG. 1, a central control unit 40 may be used to control all the controllable semiconductor switches of the electrical converter 10, sending control signals to each switch via a communication interface 50. Furthermore, the control unit has measurement input ports (43, 44, 45, 46), for receiving measurements of: [0064] 43: the AC-grid phase voltages v.sub.a, v.sub.b, v.sub.c; [0065] 44: the AC inductor currents i.sub.a, i.sub.b, i.sub.c; [0066] 45: the DC bus voltage V.sub.DC; [0067] 46: the DC bus mid-point voltage V.sub.mn=−V.sub.nm,
and an input port 41 to receive a set-value, which may be a requested DC output voltage V*.sub.DC, and a input port 42 to receive set-values for phase-imbalance current control. For example, the set-values for phase-imbalance current control may be values percentages defining for each phase a requested reduction of the maximum amplitude of the phase current, in order to for example unload a particular phase.

[0068] FIG. 3 shows a block diagram of an advantageous implementation of the central control unit 40 which is shown in a schematically way in FIG. 1. The electrical converter 10 is in FIG. 3 represented as a ‘single-wire’ equivalent circuit, wherein the annotations of the elements correspond with those given in FIG. 1. Three slashes in a signal line indicate the bundling of three phase signals, and may represent the transition to a vector representation.

[0069] The goal of the control unit 40 is to control the output voltage V.sub.DC to a requested set-value V*.sub.DC that is received from an external unit via input port 41, and to balance the voltage across the two output capacitors C.sub.pm and C.sub.mn, for example by controlling the voltage across the lower output capacitor C.sub.mn to be substantially equal to half the DC bus voltage. Additionally, the current drawn from the phase inputs (a,b,c) needs to be shaped substantially sinusoidal and controlled substantially in phase with the corresponding phase voltage. Note that the currents drawn from the phase inputs (a,b,c) is equal to the filtered (low-passed) currents i.sub.a, i.sub.b, i.sub.c in the phase inductors L.sub.a, L.sub.b, L.sub.c, since the high-frequency ripple of the phase-inductor currents i.sub.a, i.sub.b, i.sub.c is filtered by the AC capacitors (C.sub.a, C.sub.b, or C.sub.c). Therefore, controlling the currents drawn from the phase inputs (a,b,c) can be done by controlling the, for example low-pass filtered, phase-inductor currents i.sub.a, i.sub.b, i.sub.c.

[0070] The control of the output voltage V.sub.DC is done using a cascaded control structure, comprising an outer voltage control loop 60 and inner current control loop 70. The set-value of the output voltage is input to a comparator 61 via input port 41, and is compared with the measured output voltage obtained from a measurement processing unit 95 (for example comprising a low-pass filter). The output of comparator 61 is the control-error signal of the output voltage, which is further input to a control element 62 (for example comprising a proportional-integral control block) that outputs the instantaneous set-values of the amplitudes of the phase-inductor currents. These amplitudes are input to multiplier 63, and multiplied with the set-values for phase-imbalance current control which are received via input port 42, in order to unload a particular phase if this would be required. The output of the multiplier 63 are updated instantaneous set-values of the amplitudes of the phase-inductor currents, which are input to multiplier 64, and multiplied with signals that are obtained from calculation element 65 that outputs normalized instantaneous values of the phase voltages. The input of calculation element 65 are the measured phase voltages obtained from a measurement processing unit 93 (for example comprising a low-pass filter). The output of the multiplier 64 are set-values i*.sub.a, i*.sub.b, i*.sub.c for the instantaneous, for example low-pass filtered, phase-inductor currents i.sub.a, i.sub.b, i.sub.c, and are shaped substantially sinusoidal and positioned substantially in phase with the corresponding phase voltages. The set-values i*.sub.a, i*.sub.b, i*.sub.c are input to the current controller 70 after passing an addition element 68 and a selection element 81 whose functions are further detailed in the following text.

[0071] The current controller 70 is split into three individual current controllers 71, 74, 77, wherein: [0072] individual current controller 71 is used for controlling the current in the phase-inductor of the phase input a,b,c, that has the highest voltage of the three-phase AC voltage. This control is done by PWM modulation of the switch S.sub.xm of the upper boost converter containing upper boost bridge 18, as explained in the foregoing text; [0073] individual current controller 74 is used for controlling the current in the phase-inductor of the phase input a,b,c, that has the lowest voltage of the three-phase AC voltage. This control is done by PWM modulation of the switch S.sub.my of the lower boost converter containing lower boost bridge 19, as explained in the foregoing text; [0074] individual current controller 77 is used for controlling the current in the phase-inductor of the phase input a,b,c, that has a voltage between the highest voltage and the lowest voltage of the three-phase AC voltage. This control is done by the PWM modulation of the switches of the bridge leg of the remaining switching circuit containing the bridge leg of the rectifier that is in the ‘active switching state’, as explained in the foregoing text.

[0075] Selector element 81 is used to send the set-values i*.sub.a, i*.sub.b, i*.sub.c for the instantaneous phase-inductor currents to the correct individual current controller (71, 74, 77) depending on the voltage value of the phase inputs (a, b, c), wherein: [0076] the set-value of the phase current of the phase input a,b,c, that has the highest voltage of the three-phase AC voltage is sent to individual current controller 71; [0077] the set-value of the phase current of the phase input a,b,c, that has the lowest voltage of the three-phase AC voltage is sent to individual current controller 74; [0078] the set-value of the phase current of the phase input a,b,c, that a voltage between the highest voltage and the lowest voltage of the three-phase AC voltage is sent to individual current controller 77.

[0079] In each individual current controller the received set-value for the instantaneous phase-inductor current is input to a comparator, for example comparator 72 of individual current controller 71, and compared with the measured phase-inductor current obtained from a measurement processing unit 94 (for example comprising a low-pass filter) and sent to the comparator of the correct individual current controller by selector element 82 which operates in a similar fashion as selector element 81. The output of the comparator is the control-error signal of the current, which is further input to a control element, for example control element 73 of individual current controller 71, whose output is input to a PWM generation element, for example PWM generation element 53 of individual current controller 71. The PWM generation element of the individual current controllers generate the PWM-modulated control signals for the controllable semiconductor switches of the PWM-controlled bridge legs, i.e. the upper boost bridge 18 of the upper boost converter, the lower boost bridge 19 of the lower boost converter, and the bridge leg of the rectifier 11 that is in the active switching state (‘remaining bridge leg’). These PWM-modulated control signals are sent to the appropriate bridges via communication interface 50, wherein: [0080] the PWM-modulated control signal for the switch of the upper boost bridge 18 of the upper boost converter is sent directly from the PWM generation element of the individual current controller 71; [0081] the PWM-modulated control signal for the switch of the lower boost bridge 19 of the lower boost converter is sent directly from the PWM generation element of the individual current controller 74; [0082] the PWM-modulated control signals for the switches of the bridge leg of the rectifier 11 that is in the active switching state (‘remaining bridge leg’) is sent by selector element 83 which determines which bridge leg of the rectifier 11 is in the active switching state depending on the voltage value of the phase inputs (a, b, c), in a similar fashion as selector elements 81, 82.

[0083] The control signals for the switches of the bridge legs of the rectifier stage 11 that are in the ‘selection state’ are either ‘on’ or ‘off’. These control signals are generated by switch-signal generators 51, 52. The output of both switch-signal generators are complementary, for example switch-signal generator 51 generates control signals that put the top switch of a bridge leg in the on state and the bottom switch of the bridge leg in the off state while switch-signal generator 52 generates control signals that put the bottom switch of a bridge leg in the on state and the top switch of the bridge leg in the off state. Selector element 83 determines to which bridge legs of the rectifier 11 the control signals output by switch-signal generators 51, 52 are sent depending on the voltage value of the phase inputs (a, b, c), in a similar fashion as selector elements 81, 82.

[0084] DC bus mid-point balancing is done by adding an offset value to the set-values i*.sub.a, i*.sub.b, i*.sub.c for the instantaneous, for example low-pass filtered, phase-inductor currents i.sub.a, i.sub.b, i.sub.c, which are output by multiplier 64. The offset value is obtained by comparing the measured DC bus midpoint voltage obtained from a measurement processing unit 96 (for example comprising a low-pass filter) with a set-value (for example V.sub.DC/2) using comparator 66 and feeding the error signal output by the comparator 66 into a control element 67.

[0085] The phase-inductor currents i.sub.a, i.sub.b, i.sub.c shown in FIG. 2B are obtained by controlling the electrical converter 10 using such control unit 40 and control method detailed in the foregoing text. Also shown in FIG. 2B are the set-values i*.sub.a, i*.sub.b, i*.sub.c for the instantaneous, for example low-pass filtered, phase-inductor currents i.sub.a, i.sub.b, i.sub.c, as input to selector element 81 shown in FIG. 3.

[0086] FIGS. 4A-4C show diagrams within five consecutive switching cycles (i.e., each having a switching period Ts equal to 1/fs, with fs the switching frequency) of the bridge legs of the electrical converter 10, for a time interval around ωt=45° which lies within the sector of the three-phase AC input voltage where 0≤ωt<60° (see FIG. 2). Within this sector, the bridge legs of the rectifier stage 11 are in the following switching states: [0087] bridge leg 15: active switching state; S.sub.xa & S.sub.ay=PWM; [0088] bridge leg 16: selection state; S.sub.xb=0, S.sub.by=1, connecting phase input b with node y; [0089] bridge leg 17: selection state; S.sub.xc=1, S.sub.cy=0, connecting phase input c with node x.

Accordingly:

[0090] An upper boost converter is formed by the upper boost bridge 18, AC capacitor C.sub.c, phase inductor L.sub.c, and upper output capacitor C.sub.pm. [0091] A lower boost converter is formed by the lower boost bridge 19, AC capacitor C.sub.b, phase inductor L.sub.b, and lower output capacitor C.sub.mn. [0092] A remaining switching circuit (similar to single-phase half-bridge voltage-source converter (VSC) is formed by PWM-modulated bridge leg 15 of the rectifier stage 11, AC capacitor C.sub.a, phase inductor L.sub.a, and both output capacitors C.sub.pm, C.sub.ma.

[0093] The diagrams of FIGS. 4A-4C show voltages, currents, and switching signals on a milliseconds time axis. FIG. 4A corresponds with the operation of the formed upper boost converter, showing the corresponding inductor current i.sub.c (and the set-value i*.sub.c of this current), the inductor voltage v.sub.Lc, and the control signal S.sub.xm, of the switch of the PWM-modulated upper boost bridge 18. FIG. 4B corresponds with the operation of the formed lower boost converter, showing the corresponding inductor current i.sub.b (and the set-value i*.sub.b of this current), the inductor voltage v.sub.Lb, and the control signal S.sub.my of the switch of the PWM-modulated lower boost bridge 19. FIG. 4C corresponds with the operation of the formed remaining switching circuit, showing the corresponding inductor current i.sub.a (and the set-value is of this current), the inductor voltage v.sub.La, and the control signal S.sub.xa of the upper switch of the PWM-modulated bridge leg 15. Note that the control signal S.sub.ay of the lower switch of the PWM-modulated bridge leg 15 is the complement of the control signal S.sub.xa. FIG. 4C also shows the control signals S.sub.xb, S.sub.xc of the upper switches of the bridge legs 16, 17 of the rectifier stage 11 which are in the selection state. Also here, the control signals S.sub.by, S.sub.cy of the lower switches are the complement of the control signals S.sub.xb, S.sub.xc of the upper switches.

[0094] A property of the electrical converter 10 is that the upper intermediate voltage node x and the lower intermediate voltage node y show a ‘switched’ voltage potential caused by the switching of the output power stage 12. Therefore, the voltage v.sub.xy between these two nodes is also a switched voltage, particularly a three-level voltage, as can be seen from FIG. 5A, showing a period (360°) of the AC mains voltage, and from FIG. 5B, showing five consecutive switching cycles for a time interval around ωt=45°. The average value v.sub.xy of voltage v.sub.xy, is also shown in FIG. 5A, FIG. 5B and is equal to the full-wave rectified AC voltage.

[0095] In order to minimize the Total Harmonic Distortion (THD) of the AC input current of the electrical converter, the high-frequency ripple of inductor currents i.sub.a, i.sub.b, i.sub.c is advantageously minimized. Particularly, the high-frequency ripple of the current drawn from the phase input (a, b, c) having a voltage between the highest voltage and the lowest voltage may be minimized by proper phase-shifting or interleaving of the PWM switching signals of the controllable semiconductor switches of the upper boost leg, the lower boost leg, and the bridge leg connected to the phase input (a,b,c) having a voltage between the highest voltage and the lowest voltage. Note that the PWM switching signals (S.sub.xm, S.sub.my, S.sub.xa) shown in respectively FIG. 4A, FIG. 4B, FIG. 4C are interleaved in an exemplary way.

[0096] An advantage of the electrical converter 10 is that the ripple of inductor currents i.sub.a, i.sub.b, i.sub.c is smaller than for a conventional six-switch boost-type PFC rectifier which means that, for the same ripple current, smaller phase inductors can be used. This is the result of the lower voltage integral (i.e. over half a switching cycle) of the inductor voltages and the possibility to interleave the PWM control signals of the controllable semiconductor switches of the upper boost leg 18, the lower boost leg 19, and the bridge leg of the rectifier 11 that is connected to the phase input (a,b,c) having a voltage between the highest voltage and the lowest voltage in order to reduce the high-frequency ripple of the current drawn from the phase input (a, b, c) having a voltage between the highest voltage and the lowest voltage.

[0097] FIG. 6 shows another example, similar to FIG. 2, in which the amplitudes of the phase-inductor currents i.sub.a, i.sub.b, i.sub.c are unequal, resulting in a non-zero average return current i.sub.N the is injected into the neutral conductor of the three-phase AC grid 20. This illustrated the ability of the electrical converter 10 and control unit 40 to independently control the amplitudes of the currents drawn from the phase inputs a,b,c of the three-phase AC grid 20.

[0098] The electrical converter shown in FIG. 1 is unidirectional since the output power stage 12 contains diodes, only allowing power to be drawn from the electrical AC grid 20 and provide this power at its output to a load 21. FIG. 7, on the other hand, shows an electrical converter 10 that is bidirectional, since the diodes of the output power stage 12 of the converter shown in FIG. 1 have been supplemented with controllable semiconductor switches S.sub.px, S.sub.yn connected between a respective upper or lower intermediate node x,y and a respective output terminal p, n.

[0099] In FIG. 8, an electrical converter 10 without neutral connection terminal N is shown wherein the stacked boost bridges 18, 19 of the output power stage 12 are replaced by a single boost bridge 22. Boost bridge 22 comprises a controllable semiconductor switch S.sub.xy connected between the upper and lower intermediate node x,y. This converter does not provide a path for a return current equal to the sum of the three phase currents to flow back to the neutral conductor of the grid, and might be advantageous in case no neutral conductor of the electrical grid is present and/or in case the amplitudes of the three phase currents drawn from the three-phase AC grid do not need to be controlled fully independently, for example when it is sufficient to draw currents with substantially equal amplitudes.

[0100] The electrical converter shown in FIG. 8 is unidirectional. The diode D.sub.xp blocks bidirectional power flow. FIG. 9, on the other hand, shows an electrical converter that is bidirectional, since the diode D.sub.xp of the output power stage 22 of the converter shown in FIG. 8 has been supplemented by a controllable semiconductor switch S.sub.px.

[0101] Note that in FIG. 8 the AC capacitors C.sub.a, C.sub.b, C.sub.c of the electrical converter 10 are connected in a star configuration, while in FIG. 9 the AC capacitors C.sub.a, C.sub.b, C.sub.c are delta-connected. However, a delta connection is also possible in FIG. 8 or a star connection in FIG. 9.

[0102] FIG. 10A, 10B show different variants of the three-phase active rectifier 11, which may be used in either FIG. 1, FIG. 7. In FIG. 10A and FIG. 10B the bridge legs are three-level half-bridges instead of two-level half bridges for FIG. 1 and FIG. 7. In the three-phase active rectifier 11 of FIG. 10A the half-bridges are NPC based (NPC stands for ‘Neutral Point Clamped’) while in the three-phase active rectifier 11 of FIG. 10B the half-bridges are T-type based. Note that in both FIG. 10A, 10B the three-level bridge legs comprise a connection to the middle output node m of the electrical converter 10.

[0103] The bridge leg of the rectifier stage in FIG. 10A, 10B that is connected with the phase input a, b, or c that has a voltage between the highest voltage and the lowest voltage of the three-phase AC input voltage may be switched in a way that the corresponding phase input a, b, or c is alternately connected to the upper intermediate voltage node x, the lower intermediate voltage node y, and the middle output node m via the corresponding phase inductor, wherein an additional voltage potential is applied to the phase inductor which may allow to further reduce the high-frequency ripple of the inductor current.