Marking method
11227969 ยท 2022-01-18
Assignee
Inventors
Cpc classification
H01L31/0336
ELECTRICITY
H01L31/02245
ELECTRICITY
H01L2223/54413
ELECTRICITY
H01L31/078
ELECTRICITY
Y02P70/50
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y02E10/544
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
H01L31/186
ELECTRICITY
H01L23/544
ELECTRICITY
H01L31/1876
ELECTRICITY
International classification
H01L31/18
ELECTRICITY
Abstract
A marking method for applying a unique identification to each individual solar cell stack of a semiconductor wafer, at least comprising the steps: Providing a semiconductor wafer having an upper side and an underside, which comprises a Ge substrate forming the underside; and generating an identification with a unique topography by means of laser ablation, using a first laser, on a surface area of the underside of each solar cell stack of the semiconductor wafer, the surface area being formed in each case by the Ge substrate or by an insulating layer covering the Ge substrate.
Claims
1. A marking method for applying a unique identification to each individual solar cell stack of a semiconductor wafer comprising at least two solar cell stacks, the method comprising: providing a semiconductor wafer, which has an upper side and an underside, the underside comprising a Ge substrate; and generating an identification with a unique topography by laser ablation using a first laser on a surface area of the underside of the at least two solar cell stacks of the semiconductor wafer, wherein the surface area is formed by the Ge substrate or by an insulating layer covering the Ge substrate.
2. The method according to claim 1, wherein an etching process, using a first etching solution, is carried out after generating the unique identification for cleaning and deepening the topography of the identifications.
3. The method according to claim 1, wherein the surface area formed by the Ge substrate is metal-plated together with the underside of the Ge substrate after the unique identifications are applied.
4. The method according to claim 1, wherein the solar cell stacks of the semiconductor wafer are separated after the unique identification is applied.
5. The method according to claim 1, wherein the unique identification is carried out prior to a growth of layers on the Ge substrate.
6. The method according to claim 1, wherein the unique identification is carried out after a growth of layers on the Ge substrate.
7. The method according to claim 1, wherein the semiconductor wafer comprises multiple solar cell stacks, each solar cell stack having the Ge substrate forming the underside, a Ge subcell and at least two III-V subcells in the specified order in each case.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:
(2)
(3)
DETAILED DESCRIPTION
(4) The illustration in
(5) Underside 10.2 has a dielectric insulating layer 22 formed in regions in each case on the Ge substrate in the area of each solar cell stack 12. Each solar cell stack 12 has a surface with a unique identification K on underside 10.2, identification K or the surface area being formed on Ge substrate 14. Alternatively, identification K or the surface area is formed on dielectric insulating layer 22 (illustrated by the dashed line).
(6) Another example is shown in the illustration in
(7) A detail of semiconductor wafer 10 illustrated in cross section has a Ge subcell 16 on Ge substrate 14 forming underside 10.2, a first III-V subcell 18 and second III-V subcell 20 forming an upper side 10.1 of semiconductor wafer 10 in the specified order as well as a through-opening 24 extending from upper side 10.1 to underside 10.2.
(8) Identification K is generated by means of laser ablation, using a first laser L. The identification comprises a unique topography on the surface area of underside 10.2 of semiconductor wafer 10.
(9) The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.