CIRCUIT BOARD LAYOUT METHOD AND WIRING METHOD FOR CRYSTAL OSCILLATION CIRCUIT, AND CRYSTAL OSCILLATION CIRCUIT

Abstract

A crystal oscillation circuit includes: two resistors; two capacitors; and an inverter. A crystal oscillation circuit for the crystal oscillation circuit includes: arranging the two resistors in parallel with the two capacitors such that an area of a wiring feedback path from an output terminal to an input terminal of the inverter is minimized, and arranging terminals of the two capacitors to be connected to ground close to each other.

Claims

1. A circuit board layout method for a crystal oscillation circuit, the crystal oscillation circuit comprising a crystal resonator, a first resistor, a second resistor, a first capacitor, a second capacitor, and an inverter, wherein one end of the crystal resonator, an input end of the inverter, one end of the first resistor, and one end of the first capacitor are commonly connected, an output end of the inverter, another end of the first resistor, and one end of the second resistor are commonly connected, another end of the crystal resonator, another end of the second resistor, and one end of the second capacitor are commonly connected, and another end of the first capacitor and another end of the second capacitor are grounded, the circuit board layout method comprising: arranging the first resistor and the second resistor in parallel with the first capacitor and the second capacitor such that an area of a wiring feedback path from an output terminal to an input terminal of the inverter is minimized; and arranging terminals of the first capacitor and the second capacitor to be connected to ground close to each other.

2. The circuit board layout method according to claim 1, comprising: arranging the first resistor between parallel wirings comprising an input wiring and an output wiring of the inverter.

3. The circuit board layout method according to claim 1, comprising: arranging the first resistor and the second resistor linearly.

4. The circuit board layout method according to claim 1, comprising: arranging the first capacitor and the second capacitor linearly.

5. The circuit board layout method according to claim 4, comprising: arranging the another end of the first resistor and the another end of the second resistor to face a common ground terminal portion.

6. The circuit board layout method according to claim 1, comprising arranging the crystal resonator in parallel with the first capacitor and the second capacitor on a side opposite to the first resistor and the second resistor across the first capacitor and the second capacitor.

7. A wiring method for a crystal oscillation circuit, the crystal oscillation circuit having a layout by the circuit board layout method according to claim 1, wherein the first resistor and the second resistor are arranged in parallel with the first capacitor and the second capacitor such that the area of the wiring feedback path from the output terminal to the input terminal of the inverter is minimized, and the terminals of the first capacitor and the second capacitor to be connected to ground are arranged close to each other, the wiring method comprising: mounting components comprising the crystal resonator, the first resistor, the second resistor, the first capacitor, and the second capacitor on a surface layer of a multilayer circuit board; and wiring all inter-component-terminal wirings in an inner layer of the multilayer circuit board.

8. The wiring method according to claim 7, wherein a component size of each of the first resistor, the second resistor, the first capacitor, and the second capacitor is equal to or smaller than a component size of the crystal resonator.

9. A crystal oscillation circuit comprising: a crystal resonator; a first resistor; a second resistor; a first capacitor; a second capacitor; and an inverter, wherein one end of the crystal resonator, an input end of the inverter, one end of the first resistor, and one end of the first capacitor are commonly connected, wherein an output end of the inverter, another end of the first resistor, and one end of the second resistor are commonly connected, wherein another end of the crystal resonator, another end of the second resistor, and one end of the second capacitor are commonly connected, and another end of the first capacitor and another end of the second capacitor are grounded, wherein the first resistor and the second resistor are arranged in parallel with the first capacitor and the second capacitor such that an area of a wiring feedback path from an output terminal to an input terminal of the inverter is minimized, and wherein terminals of the first capacitor and the second capacitor to be connected to ground are arranged close to each other.

10. The crystal oscillation circuit according to claim 9, wherein an input wiring and an output wiring of the inverter are parallel wirings.

11. The crystal oscillation circuit according to claim 9, wherein the first resistor is arranged between the parallel wirings of the inverter.

12. The crystal oscillation circuit according to claim 9, wherein the first resistor and the second resistor are linearly arranged.

13. The crystal oscillation circuit according to claim 9, wherein the first capacitor and the second capacitor are linearly arranged.

14. The crystal oscillation circuit according to claim 13, wherein the another end of the first resistor and the another end of the second resistor are arranged to face a common ground terminal portion.

15. The crystal oscillation circuit according to claim 14, wherein the another end of the first resistor and the another end of the second resistor are connected to the common ground terminal portion.

16. The crystal oscillation circuit according to claim 9, wherein the crystal resonator is arranged in parallel with the first capacitor and the second capacitor on a side opposite to the first resistor and the second resistor across the first capacitor and the second capacitor.

17. The crystal oscillation circuit according to claim 9, further comprising: a multilayer circuit board, wherein components comprising the crystal resonator, the first resistor, the second resistor, the first capacitor, and the second capacitor are mounted on a surface layer of the multilayer circuit board; and wherein all inter-component-terminal wirings are wired in an inner layer of the multilayer circuit board.

18. The crystal oscillation circuit according to claim 9, wherein a component size of each of the first resistor, the second resistor, the first capacitor, and the second capacitor is equal to or smaller than a component size of the crystal resonator.

19. The crystal oscillation circuit according to claim 18, wherein a length of a long side of each of the first resistor and the second resistor is equal to or smaller than a half of a length of a long side of the crystal resonator.

20. The crystal oscillation circuit according to claim 18, wherein a length of a long side of each of the first capacitor and the second capacitor is equal to or smaller than a half of a length of a long side of the crystal resonator.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0014] FIG. 1 is a circuit diagram showing a crystal oscillation circuit according to an embodiment of the present disclosure.

[0015] FIG. 2 is an illustrative diagram showing a circuit board layout of the crystal oscillation circuit of FIG. 1.

[0016] FIG. 3 is a diagram showing a relationship among sizes of a crystal resonator, two resistors, and two capacitors of the crystal oscillation circuit of FIG. 1.

[0017] FIG. 4 is an illustrative diagram showing a circuit board layout of a crystal oscillation circuit that leads to the embodiment of the present disclosure.

[0018] FIG. 5 is an illustrative diagram showing a circuit board layout of a crystal oscillation circuit that leads to the embodiment of the present disclosure.

DETAILED DESCRIPTION

[0019] First, circumstances that lead to an embodiment of the present disclosure will be described.

[0020] FIGS. 4 and 5 are illustrative diagrams of circuit board layouts of crystal oscillation circuits that lead to the embodiment of the present disclosure. A crystal oscillation circuit 100A shown in FIG. 4 and a crystal oscillation circuit 100B shown in FIG. 5 both include a crystal resonator 101, an inverter 102, a resistor (a first resistor) 103, a resistor (a second resistor) 104, a capacitor (a first capacitor) 105, and a capacitor (a second capacitor) 106. One end of the crystal resonator 101, an input end of the inverter 102, one end of the resistor 103, and one end of the capacitor 105 are commonly connected. An output end of the inverter 102, the other end of the resistor 103, and one end of the resistor 104 are commonly connected. The other end of the crystal resonator 101, the other end of the resistor 104, and one end of the capacitor 106 are commonly connected. The other ends of the two capacitors 105 and 106 are grounded.

[0021] Here, the resistor 103 interposed between input and output ends of the inverter 102 is referred to as a feedback resistor. Further, when the inverter 102 is configured with a complementary metal oxide semiconductor (CMOS), the resistor 104 is referred to as a drain resistor, the capacitor 105 is referred to as a drain capacitance, and the capacitor 106 is referred to as a gate capacitance.

[0022] In a layout of a circuit board of components that constitute the crystal oscillation circuit 100A, the resistors 103 and 104 are linearly arranged and arranged in parallel with the crystal resonator 101. The inverter 102 is disposed in parallel with the resistor 103. The capacitors 105 and 106 are arranged linearly with the crystal resonator 101. On the other hand, in a layout of a circuit board of components that constitute a crystal oscillation circuit 100B, the resistors 103 and 104 are linearly arranged and arranged in parallel with the crystal resonator 101, the inverter 102 is disposed in parallel with the resistor 103, and the capacitors 105 and 106 are arranged in a direction perpendicular to a longitudinal direction of the crystal resonator 101.

[0023] In the crystal oscillation circuits 100A and 100B, in a current feedback path of the capacitors where a minute current change (a Δi change) occurs with respect to ground, polarities of minute currents −Δi and +Δi that flow through the capacitors 105 and 106 are in an inverted relationship with each other. The minute current −Δi that flows through the capacitor 105 flows in a direction from a ground side to a crystal resonator 101 side, and the minute current +Δi that flows through the capacitor 106 flows in a direction from the crystal resonator 101 side to the ground side. When the minute currents +Δi and −Δi flow, an electromagnetic noise NS is generated. If these minute currents +Δi and −Δi can be suppressed, the electromagnetic noise NS can be reduced. The present disclosure can cancel the minute currents +Δi and −Δi, so that the electromagnetic noise NS can be reduced.

[0024] Hereinafter, a preferred embodiment for carrying out the present disclosure will be described in detail with reference to the drawings.

[0025] FIG. 1 is a circuit diagram showing a crystal oscillation circuit 1 according to an embodiment of the present disclosure. FIG. 2 is an illustrative diagram showing a layout of components that constitute the crystal oscillation circuit 1 of FIG. 1. First, in FIG. 1, the crystal oscillation circuit 1 includes the crystal resonator 101, the inverter 102, the two resistors 103 and 104, and the two capacitors 105 and 106. Regarding connection of the components, one end of the crystal resonator 101, an input end of the inverter 102, one end of the resistor 103, and one end of the capacitor 105 are commonly connected; an output end of the inverter 102, the other end of the resistor 103, and one end of the resistor 104 are commonly connected; the other end of the crystal resonator 101, the other end of the resistor 104, and one end of the capacitor 106 are commonly connected; and the other ends of the capacitors 105 and 106 are grounded.

[0026] In a circuit board layout of the components that constitute the crystal oscillation circuit 1, input and output wirings of the inverter 102 are parallel wirings, the resistors 103 and 104 and the capacitors 105 and 106 are linearly arranged, and the resistors 103 and 104 are arranged in parallel with the capacitors 105 and 106. The resistor 103 is positioned between parallel wirings of the input and output wirings of the inverter 102. The crystal resonator 101 is disposed in parallel with the capacitors 105 and 106 on a side opposite to the resistors 103 and 104 across the capacitors 105 and 106.

[0027] The crystal oscillation circuit 1 according to the present embodiment has the same circuit configuration as those of the crystal oscillation circuits 100A and 100B that lead to the embodiment of the present disclosure, but there is a difference in the layout of the components. That is, in the crystal oscillation circuit 1 according to the present embodiment, the input and output wirings of the inverter 102 are the parallel wirings, the two resistors 103 and 104 are arranged in parallel with the two capacitors 105 and 106 so that an area of a wiring feedback path from an output terminal to an input terminal of the inverter 102 is minimized, and terminals of the two capacitors 105 and 106 to be connected to the ground are arranged close to each other.

[0028] In this way, the layout minimizes the area of the wiring feedback path from the output terminal to the input terminal of the inverter 102, and the terminals of the two capacitors 105 and 106 to be connected to the ground are arranged close to each other, so that in a capacitor current feedback path where the minute current change (the Δi change) occurs with respect to the ground, polarities of minute currents that flow through the two capacitors 105 and 106 are in an inverted relationship with each other, and the minute currents flow in opposite directions. Therefore, the currents can be canceled by a common ground terminal portion 110. That is, since the minute currents +Δi and −Δi can be canceled, the electromagnetic noise NS can be reduced.

[0029] The two resistors 103 and 104 are arranged in parallel with the two capacitors 105 and 106 so as to have the layout in which the area of the wiring feedback path from the output terminal to the input terminal of the inverter 102 is minimized, so that a feedback current in an oscillation operation can be reduced.

[0030] Components of the crystal resonator 101, the two resistors 103 and 104, and the two capacitors 105 and 106 that constitute the crystal oscillation circuit 1 according to the present embodiment are mounted on a surface layer of a multilayer circuit board (not shown), and all inter-component-terminal wirings are wired in an inner layer of the multilayer circuit board.

[0031] With such a component layout and wiring, radiation of the electromagnetic noise to an outside of the circuit board due to the Δi change and the Av change generated in the inter-component-terminal wiring can be suppressed inside the circuit board. That is, the electromagnetic noise can be effectively absorbed by a ground potential.

[0032] In the crystal oscillation circuit 1 according to the present embodiment, it is desirable that component sizes of the two resistors 103 and 104 and the two capacitors 105 and 106 are equal to or smaller than a component size of the crystal resonator 101. For example, as shown in FIG. 3, a length L2 of a long side of each of the two resistors 103 and 104 and a length L3 of a long side of each of the two capacitors 105 and 106 are set to be equal to or smaller than ½ of a length L1 of a long side of the crystal resonator 101.

[0033] As described above, according to the crystal oscillation circuit 1 of the present embodiment, in the layout when the components that constitute the crystal oscillation circuit 1 are mounted on the circuit board, the two resistors 103 and 104 are arranged in parallel with the two capacitors 105 and 106 so that the area of the wiring feedback path from the output terminal to the input terminal of the inverter 102 is minimized, and the terminals of the two capacitors 105 and 106 to be connected to the ground are arranged close to each other, so that the minute currents −Δi and +Δi that flow through the two capacitors 105 and 106 can be canceled. Therefore, the electromagnetic noise NS can be reduced. Further, the two resistors 103 and 104 are arranged in parallel with the two capacitors 105 and 106 so as to have the layout in which the area of the wiring feedback path from the output terminal to the input terminal of the inverter 102 is minimized, so that a feedback current loop in an oscillation operation can be reduced.

[0034] According to the crystal oscillation circuit 1 of the present embodiment, the components of the crystal resonator 101, the two resistors 103 and 104, and the two capacitors 105 and 106 are mounted on the surface layer of the multilayer circuit board, and all inter-component-terminal wirings are wired in the inner layer of the multilayer circuit board. Therefore, radiation of the electromagnetic noise to an outside of the circuit board due to the Δi change and the Av change generated in the inter-component-terminal wiring can be suppressed inside the circuit board. That is, the electromagnetic noise can be effectively absorbed by the ground potential.

[0035] In this way, in the crystal oscillation circuit 1 according to the present embodiment, the electromagnetic noise is minimized. Therefore, it is possible to implement, for example, a small camera that is free to be installed in a vehicle and has excellent low noise and noise resistance performance.

[0036] The present disclosure provides a wiring method for a crystal oscillation circuit, the crystal oscillation circuit having a layout by the circuit board layout method, wherein the first resistor and the second resistor are arranged in parallel with the first capacitor and the second capacitor such that the area of the wiring feedback path from the output terminal to the input terminal of the inverter is minimized, and the terminals of the first capacitor and the second capacitor to be connected to ground are arranged close to each other, the wiring method including: mounting components including the crystal resonator, the first resistor, the second resistor, the first capacitor, and the second capacitor on a surface layer of a multilayer circuit board; and wiring all inter-component-terminal wirings in an inner layer of the multilayer circuit board.

[0037] According to the above method, the layout minimizes the area of the wiring feedback path from the output terminal to the input terminal of the inverter, and the terminals of the two capacitors to be connected to the ground are arranged close to each other, so that in a capacitor current feedback path where a minute current change (a Δi change) occurs with respect to the ground, polarities of minute currents that flow through the two capacitors are in an inverted relationship with each other, and the minute currents flow in opposite directions. Therefore, the currents can be canceled by a common ground terminal portion.

[0038] The two resistors are arranged in parallel with the two capacitors so as to have the layout in which the area of the wiring feedback path from the output terminal to the input terminal of the inverter is minimized, so that a feedback current in an oscillation operation can be reduced.

[0039] The present disclosure provides a crystal oscillation circuit including: a crystal resonator; a first resistor; a second resistor; a first capacitor; a second capacitor; and an inverter, wherein one end of the crystal resonator, an input end of the inverter, one end of the first resistor, and one end of the first capacitor are commonly connected, wherein an output end of the inverter, another end of the first resistor, and one end of the second resistor are commonly connected, wherein another end of the crystal resonator, another end of the second resistor, and one end of the second capacitor are commonly connected, and another end of the first capacitor and another end of the second capacitor are grounded, wherein the first resistor and the second resistor are arranged in parallel with the first capacitor and the second capacitor such that an area of a wiring feedback path from an output terminal to an input terminal of the inverter is minimized, and wherein terminals of the first capacitor and the second capacitor to be connected to ground are arranged close to each other.

[0040] According to the above method, radiation of an electromagnetic noise to an outside of the circuit board due to a Δi change and a Δv change generated in an inter-component-terminal wiring can be suppressed inside the circuit board. That is, the electromagnetic noise can be effectively absorbed by a ground potential.

[0041] Although the present disclosure has been described in detail with reference to a specific embodiment, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and the scope of the present disclosure.

[0042] The present application is based on Japanese Patent Application (Japanese Patent Application No. 2019-013373) filed on Jan. 29, 2019, and the contents of which are incorporated herein by reference.

[0043] The present disclosure is useful for a small camera that is free to be installed in a vehicle and has excellent low noise and noise resistance performance.