CHARGE SENSING DEVICE WITH READOUT OF SIGNAL BY DETECTING A CHANGE OF CAPACITANCE OF COMBINED GATE AND QUANTUM CAPACITANCE COMPARED TO A REFERENCE CAPACITANCE

Abstract

The present invention relates to a system comprising an electronic apparatus which comprises: —an electronic device comprising: —a gate electrode structure (G, BE); —a dielectric (D) arranged over the gate electrode (G, BE); and —a charge sensing structure (CE) with a 2-dimensional charge sensing layer to provide a gate capacitance (C.sub.g) between the charge sensing structure (CE) and the gate electrode structure (G, BE) and a quantum capacitance (C.sub.q) resulting in a total capacitance (C.sub.tot); —a read-out circuit configured so that when the total capacitance (C.sub.tot) changes due to a change in the quantum capacitance (C.sub.q), an imbalance between the total capacitance (C.sub.tot) and the reference capacitance (C.sub.f) results in a change on the output voltage (V.sub.o) that is amplified to provide the read-out signal (S.sub.o). The present invention also relates to an electronic apparatus like the one of the system of the present invention.

Claims

1. A system comprising an electronic apparatus, wherein the electronic apparatus comprises: an electronic device comprising: a gate electrode structure; a dielectric structure arranged over said gate electrode structure; and a charge sensing structure comprising at least one 2-dimensional charge sensing layer configured to sense electrical charges and/or electrical charge density changes induced by an external physical quantity, and that is configured and arranged over said dielectric structure to provide a gate capacitance between the charge sensing structure and the gate electrode structure; wherein said charge sensing structure shows a quantum capacitance in series with said gate capacitance resulting in a total capacitance between the charge sensing structure and the gate electrode structure; and a read-out circuit electrically connected to the charge sensing structure or to the gate electrode structure, to detect an output voltage that is representative of said sensed electrical charges stored in said total capacitance and provide a read-out signal based on the detected output voltage; wherein said read-out circuit comprises: an amplifier with a first input electrically connected to the charge sensing structure or to the gate electrode structure to detect said output voltage and provide, at an output of the amplifier, said read-out signal; a reference capacitor that has a magnitude equal to or differing at maximum a 50% with respect to said total capacitance when there is no induced electrical charge or electrical charge carrier density on the charge sensing structure, wherein said reference capacitor has a first plate electrically connected to said first input of the amplifier; and a mechanism configured and arranged to select and apply a control voltage to the one of said gate electrode structure and said charge sensing structure which is not electrically connected to the first input of the amplifier; wherein said control voltage is selected such that the fermi level of the charge sensing structure is tuned to the most sensitive point; so that when said total capacitance changes due to a change in the quantum capacitance caused by an electrical charge or electrical charge carrier density induced on the charge sensing structure, an imbalance between the total capacitance and the reference capacitance results in a change on the output voltage on the first input of the amplifier that is amplified to provide the read-out signal.

2. The system of claim 1, wherein the read-out circuit further comprises a first offset correction mechanism comprising said mechanism, which are configured and arranged to select and apply a first reference voltage to a second plate of the reference capacitor, so that the output voltage on the first input of the amplifier is zero when there is no induced electrical charge or electrical charge carrier density on the charge sensing structure.

3. The system of claim 1, wherein said mechanism comprises at least one voltage source that generates at least said control voltage.

4. The system of claim 1, wherein said mechanism comprises a control unit configured and arranged to select and apply at least said control voltage.

5. The system of claim 4, wherein said control voltage is a DC voltage, an AC voltage, or a combination of DC and AC voltages, and wherein the control unit is configured to select the properties of said control voltage, at least regarding its magnitude.

6. The system of claim 1, wherein said read-out circuit further comprises a second offset correction mechanism comprising said mechanism, which is configured and arranged to select and apply to a second input of the amplifier a second reference voltage with a magnitude equal or substantially equal to the output voltage when the charge sensitivity structure is set to its most sensitivity point and there is no electrical charge or electrical charge carrier density induced by the external physical quantity.

7. The system of claim 4, wherein said read-out circuit further comprises a second offset correction mechanism comprising said mechanism, which are configured and arranged to select and apply to a second input of the amplifier a second reference voltage with a magnitude equal or substantially equal to the output voltage when the charge sensitivity structure is set to its most sensitivity point and there is no electrical charge or electrical charge carrier density induced by the external physical quantity, and wherein said control unit is also configured and arranged to select and apply said second reference voltage.

8. The system of claim 1, wherein said read-out circuitry further comprises a reset circuit to discharge the total capacitance.

9. The system according to claim 1, wherein the electronic device further comprises a sensitizing or functionalizing structure arranged over said charge sensing structure, wherein said sensitizing or functionalizing structure is configured to induce said electrical charges and/or modify the electrical charge carrier density therein induced by said external physical quantity, wherein the sensitizing or functionalizing structure only sensitive to said external physical quantity.

10. The system of claim 1, wherein said reference capacitor is a separate component, with respect to the electronic device.

11. The system of claim 9, wherein said reference capacitor is implemented by the electronic device, with said first plate constituted by said charge sensing structure, a dielectric structure constituted by said sensitizing or functionalizing structure, and said second plate constituted by a top electrode structure arranged over said sensitizing or functionalizing structure.

12. The system of claim 1, wherein the electronic device and at least part of the read-out circuitry are CMOS-implemented.

13. The system of claim 9, wherein said sensitizing or functionalizing structure is a photoactive structure configured and arranged to, upon illumination, generate electron-hole pairs which, due to a field created by either a Schottky junction between the charge sensing structure and the photoactive structure or a top electrode structure on top of the photoactive structure or an interlayer between the charge sensing structure and the photoactive structure, are separated and either the electrons or holes gets transported, as said induced electrical charge carriers, to the charge sensing structure.

14. The system according to claim 13, implementing an image sensor comprising an array of pixels, wherein the electronic apparatus comprises a plurality of said electronic devices each constituting one pixel of said array of pixels.

15. An electronic apparatus, comprising: an electronic device comprising: a gate electrode structure; a dielectric structure arranged over said gate electrode structure; and a charge sensing structure comprising at least one 2-dimensional charge sensing layer configured to sense electrical charges and/or electrical charge density changes induced by an external physical quantity, and that is configured and arranged over said dielectric structure to provide a gate capacitance between the charge sensing structure and the gate electrode structure; wherein said charge sensing structure shows a quantum capacitance in series with said gate capacitance between the charge sensing structure and the gate electrode structure; and a read-out circuit electrically connected to the charge sensing structure or to the gate electrode structure, to detect an output voltage that is representative of said sensed electrical charges stored in said total capacitance and provide a read-out signal based on the detected output voltage; wherein said read-out circuit comprises: an amplifier with a first input electrically connected to the charge sensing structure or to the gate electrode structure, to detect said output voltage and provide, at an output of the amplifier, said read-out signal; and a reference capacitor that has a magnitude equal to or differing at maximum a 50% with respect to said total capacitance when there is no induced electrical charge or electrical charge carrier density on the charge sensing structure, wherein said reference capacitor has a first plate electrically connected to said first input of the amplifier; and in that further wherein the electronic apparatus further comprises at least a first input terminal electrically connected to the one of said gate electrode structure and said charge sensing structure which is not electrically connected to the first input of the amplifier; wherein said first input terminal is accessible to apply thereto a control voltage which is selected such that the fermi level of the charge sensing structure is tuned to the most sensitive point; so that when said total capacitance changes due to a change in the quantum capacitance caused by an electrical charge or electrical charge carrier density induced on the charge sensing structure, an imbalance between the total capacitance and the reference capacitance results in a change on the output voltage on the first input of the amplifier that is amplified to provide the read-out signal.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0060] In the following some preferred embodiments of the invention will be described with reference to the enclosed figures. They are provided only for illustration purposes without however limiting the scope of the invention.

[0061] FIG. 1 schematically shows the system of the first aspect of the present invention, for a first embodiment;

[0062] FIG. 2 schematically shows the system of the first aspect of the present invention, for a second embodiment;

[0063] FIG. 3 schematically shows a Si-CMOS implementation of the electronic device and part of the readout-circuitry of the electronic apparatus of the system of the first aspect of the present invention, for the arrangement of the second embodiment;

[0064] FIG. 4 schematically shows the system of the first aspect of the present invention, for a third embodiment;

[0065] FIG. 5 is a schematic side view of the structure of the electronic device of the electronic apparatus of the second aspect of the invention and of the electronic apparatus of the system of the first aspect, for an embodiment, with electrical connections indicated as round circles: CE=charge sensing layer electrode and BE=bottom electrode.

[0066] FIG. 6 is a schematic side view of the of the electronic device of the electronic apparatus of the second aspect of the invention and of the electronic apparatus of the system, for an embodiment for which the electronic device comprises a photoactive structure for, upon illumination, generate electron-hole pairs which are separated and one of them gets transported to the charge sensing structure (CE), as indicated by the charge flow illustrated.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0067] FIGS. 1, 2, and 4 show respective first, second and third embodiments of the system of the present invention, for which the electronic apparatus thereof comprises: [0068] an electronic device forming a capacitive sensing device (CSD), comprising: [0069] a gate electrode structure G; [0070] a dielectric structure D arranged over the gate electrode structure G; and [0071] a charge sensing structure CE comprising at least one 2-dimensional charge sensing layer configured to sense electrical charges and/or electrical charge density changes induced by an external physical quantity, and that is configured and arranged over said dielectric structure D to provide a gate capacitance C.sub.g between the charge sensing structure CE and the gate electrode structure G; wherein said charge sensing structure CE shows a quantum capacitance C.sub.g in series with said gate capacitance C.sub.g resulting in a total capacitance C.sub.tot between the charge sensing structure CE and the gate electrode structure G; [0072] a read-out circuit electrically connected to the charge sensing structure CE (for FIGS. 1 and 4) or to the gate electrode structure G (for FIG. 2), to detect an output voltage V.sub.o that is representative of the sensed electrical charges stored in the total capacitance C.sub.tot and provide a read-out signal S.sub.o based on the detected output voltage V.sub.o.

[0073] As shown in those figures, the read-out circuit comprises: [0074] an amplifier A with a first input electrically connected to the charge sensing structure CE (for FIGS. 1 and 4) or to the gate electrode structure G (for FIG. 2) to detect the output voltage V.sub.o and provide, at an output of the amplifier A, the read-out signal S.sub.0; [0075] a reference capacitor C.sub.ref that has a magnitude equal to or differing at maximum a 50% with respect to said total capacitance C.sub.tot when there is no induced electrical charge or electrical charge carrier density on the charge sensing structure CE, wherein the reference capacitor C.sub.ref has a first plate electrically connected to the first input of the amplifier A; and [0076] means comprising a control unit CU configured and arranged to select and apply a control voltage V.sub.g to the one of the gate electrode structure G (for FIGS. 1 and 4) and the charge sensing structure CE (for FIG. 2) which is not electrically connected to the first input of the amplifier A; wherein the control voltage V.sub.g is selected such that the fermi level of the charge sensing structure CE is tuned to the most sensitive point,

[0077] so that when said total capacitance C.sub.tot changes due to a change in the quantum capacitance C.sub.g caused by an electrical charge or electrical charge carrier density induced on the charge sensing structure CE, an imbalance between the total capacitance C.sub.tot and the reference capacitance C.sub.ref results in a change on the output voltage V.sub.o on the first input of the amplifier A that is amplified to provide the read-out signal S.sub.o.

[0078] As shown FIGS. 1, 2 and 4, the read-out circuit further comprises a first offset correction mechanism comprising the control unit CU which is configured and arranged to select and apply a first reference voltage V.sub.ref1 to a second plate of the reference capacitor C.sub.ref, so that the output voltage V.sub.o on the first input of the amplifier A is zero when there is no induced electrical charge or electrical charge carrier density on the charge sensing structure CE.

[0079] Also, for the embodiments illustrated in FIGS. 1, 2 and 4, the read-out circuit further comprises a second offset correction mechanism comprising the control unit CU which is configured and arranged to select and apply to a second input of the amplifier A a second reference voltage V.sub.ref2 with a magnitude equal or substantially equal to the output voltage V.sub.o when the charge sensitivity structure CE is set to its most sensitive point and there is no electrical charge or electrical charge carrier density induced by the external physical quantity.

[0080] As shown in FIGS. 1, 2 and 4, the read-out circuit comprises a reset circuit, formed by a transistor F, to discharge the total capacitance C.sub.tot under the control of the control unit CU (by closing the transistor F so as to connect CE or G to V.sub.ref2), when the illustrated Reset signal is applied thereto.

[0081] The classical capacitance of the CSD is given by the following formula:

C.sub.g=ε.sub.rε.sub.0A/d

[0082] Where ε.sub.r is the relative permittivity of the dielectric material, ε.sub.0 is the vacuum permittivity, A the area of the capacitor and d the thickness of the dielectric material.

[0083] For 2-dimensional materials there is another capacitance that needs to be taken into account due to their finite density of states. This is the quantum capacitance C.sub.q. C.sub.q is in series with the classical capacitance and thus reduces the total capacitance C.sub.tot of the system (1/C.sub.tot=1/C.sub.g+1/C.sub.q). The quantum capacitance is in general a function of the fermi level in the system, so it can be tuned by an external electric field, or a charge induced in the system by an external physical quantity.

[0084] When the 2-dimensional material is graphene, the quantum capacitance per unit area C.sub.q/A is described as follows:

[00001]$C_Q=\frac{2e^2}{\hslash v_F\sqrt{\pi }}{\left(.Math.n_G.Math.+.Math.n^{*}.Math.\right)}^{1/2}$

[0085] Where e is the electron charge, h the planck constant, v.sub.F the Fermi velocity of graphene, n.sub.G the induced carrier density in the graphene and n* the residual impurity density.

[0086] When C.sub.tot changes due to the charge or charge carrier density induced on the charge sensing electrode, an imbalance in the capacitor system results in a voltage change V.sub.o on the input of the amplifier A.

V.sub.o=C.sub.tot/(C.sub.ref+C.sub.tot)*(V.sub.g−V.sub.ref1)+V.sub.ref1

[0087] Amplifier A then amplifies the output voltage V.sub.o to output signal S.sub.o.

[0088] In case the sensing electrode is made up of (few layer) graphene, this is at the charge neutrality point or dirac point. The output voltage V.sub.o of the structure is measured by the amplifier A with respect to V.sub.ref2. V.sub.ref2 needs to be set such that it is equal (or substantially equal) to the output voltage V.sub.o when the charge sensing electrode CE is set to its most sensitive point and there is no charge or charge carrier density induced by the external physical quantity.

[0089] For the third embodiment, i.e. that illustrated in FIG. 4, the electronic device further comprises a sensitizing or functionalizing structure PS arranged over the charge sensing structure CE, wherein said sensitizing or functionalizing structure PS is configured to induce said electrical charges and/or modify the electrical charge carrier density therein induced by said external physical quantity, wherein the sensitizing or functionalizing structure PS is only sensitive to said external physical quantity.

[0090] The stacked up structure of the electronic device of said third embodiment is shown in FIGS. 5 and 6, for an implementation for which the electronic device is a photodetector which comprises a substrate S, a bottom electrode structure BE (as the above mentioned gate electrode structure), and a sensitizing or functionalizing structure PS constituted by a photoactive structure PS (formed by colloidal quantum dots, III-V semiconductor, perovskites, 2D material, etc.) arranged over the charge sensing structure CE (for example, formed by a single layer or few layer graphene, black phosphorus, MoS.sub.2, WS.sub.2, WSe.sub.2 etc.) configured and arranged to, upon illumination, generate electron-hole pairs which, due to a built-in field created by a Schottky junction between the charge sensing structure CE and the photoactive structure PS, are separated and either the electrons or holes (depending on the type of Schottky junction) gets transported to the charge sensing structure CE. A voltage now builds up on the gate capacitor C.sub.g. In case of a photosensitive layer it is the total photogenerated charge: Q.sub.ph=EQE*q.sub.e*τ.sub.tr A/E.sub.p I, (EQE is the external quantum efficiency, q.sub.e the electron charge, τ.sub.tr the trapping time of the photogenerated charges and I the irradiance, A the area of the device and E.sub.p the photon energy). This process is illustrated in FIG. 6.

[0091] Also for the third embodiment, as shown in FIG. 4, the reference capacitor C.sub.ref is implemented by the electronic device, with its first plate constituted by the charge sensing structure CE, a dielectric structure constituted by the sensitizing or functionalizing structure PS, and its second plate constituted by a top electrode structure TE arranged over the sensitizing or functionalizing structure PS.

[0092] The layout of the second embodiment, illustrated in FIG. 2, can have advantages for integration in complementary metal oxide semiconductor devices. Hence, FIG. 3 shows a possible CMOS implementation of the electronic device and part of the readout-circuit (particularly, an input transistor Fi of the amplifier A) of the electronic apparatus of the system of the first aspect of the present invention, for the arrangement of the second embodiment. The rest of the read-out circuit is depicted by means of block RU.

[0093] In FIG. 3 is shown how on a silicon wafer (SW) field effect transistors Fr (the reset transistor F) and Fi (the input transistor of the amplifier A) are implemented. In a layer above, the reference capacitor C.sub.ref is implemented with two metal layers, namely C.sub.ref,m1 and C.sub.ref,m2, and a dielectric layer (D2). Above the reference capacitor C.sub.ref the capacitive sensing device (CSD) is implemented. C.sub.ref,m1, G and the gate electrode of Fi are connected via a vertical metal connection. The structures are embedded in a dielectric D3. A control unit CU provides the necessary signals described in embodiment 1 and moreover provides Vs to bias transistor Fi in the proper way. The drain of transistor Fi is connected to read-out unit RU that further amplifies and processes the signal to provide finally output signal S.sub.o that is proportional to the electrical charge or charge carrier density on CE induced by the external physical quantity.

[0094] FIGS. 1, 2 and 4 also show respective embodiments of the electronic apparatus of the second aspect of the present invention which comprises the components depicted within or in contact with the contour of the dotted-line squares (which can be embedded in an integrated circuit), i.e. the components of the electronic apparatus of the system of the first aspect of the present invention and further input pin terminals TV.sub.g, T.sub.vref1, T.sub.Reset and T.sub.vref1, and also an output pin connected to terminal TS.sub.o, so that a control unit CU can be connected to those input pin terminals to provide voltages V.sub.g, V.sub.ref1, V.sub.ref2 and Reset signal, while S.sub.o goes out through output terminal TS.sub.o. For some embodiments, the control unit CU is also integrated in the integrated circuit.

[0095] A person skilled in the art could introduce changes and modifications in the embodiments described without departing from the scope of the invention as it is defined in the attached claims.