Physically Unclonable Function Circuit Having Lower Gate-to-Source/Drain Breakdown Voltage

Abstract

A physically unclonable function (PUF) circuit includes a at least a PUF bit storage transistor. The at least a PUF bit storage transistor has a gate-to-source/drain breakdown voltage lower than a gate-to-channel breakdown voltage and a gated source/drain junction breakdown voltage.

Claims

1. A physically unclonable function (PUF) circuit comprising at least a PUF bit storage transistor having a gate-to-source/drain breakdown voltage lower than a gate-to-channel breakdown voltage and a gated source/drain junction breakdown voltage.

2. The PUF circuit of claim 1, further comprising: a substrate; at least a program control transistor comprising a gate coupled to a program control line, a drain region coupled to a bit line, and a source region coupled to a source line; at least a program select transistor comprising a gate coupled to a program select line, a drain region, and a source region coupled to a ground line; and at least a read select transistor comprising a gate coupled to a read select line, a drain region coupled to the bit line, and a source region; wherein the at least a PUF bit storage transistor comprises: a drain region formed on the substrate and coupled to the source region of the at least a read select transistor; a source region formed on the substrate and coupled to the source line; a channel region formed between the drain region and the source region; a gate dielectric layer having a first portion formed on the drain region of the at least a PUF bit storage transistor, a second portion formed on the source region of the at least a PUF bit storage transistor, and a main portion formed on the channel region and between the first portion and the second portion; and a gate electrode formed on the main portion of the gate dielectric layer and coupled to the source region of the at least a program select transistor; and wherein thicknesses of the first portion of the gate dielectric layer and the second portion of the gate dielectric layer are smaller than a thickness of the main portion of the gate dielectric layer.

3. The PUF circuit of claim 2, wherein the gate electrode comprises: a main gate portion disposed directly above the channel region; a first gate extension portion disposed beside the main gate electrode and on the first portion of the gate dielectric layer; and a second gate extension portion disposed beside the main gate electrode and on the second portion of the gate dielectric layer.

4. The PUF circuit of claim 3, wherein the main gate portion, the first gate extension portion, the second gate extension portion are composed of doped polysilicon, silicide, or metal.

5. The PUF circuit of claim 3, wherein the at least a PUF bit storage transistor further comprises: a first dielectric spacer formed beside the first gate extension portion; and a second dielectric spacer formed beside the second gate extension portion.

6. The PUF circuit of claim 5, wherein: the first dielectric spacer is in direct contact with the drain region of the at least a PUF bit storage transistor; and the second dielectric spacer is direct contact with the source region of the at least a PUF bit storage transistor.

7. The PUF circuit of claim 5, wherein: the first dielectric spacer is direct contact with the first portion of the gate dielectric layer; and the second dielectric spacer is direct contact with the second portion of the gate dielectric layer.

8. The PUF circuit of claim 3, wherein a first PN junction between the drain region and the channel region of the at least a PUF bit storage transistor has an end situated directly underneath the main gate portion of the gate electrode; and a second PN junction between the source region and the channel region of the at least a PUF bit storage transistor has an end situated directly underneath the main gate portion of the gate electrode.

9. The PUF circuit of claim 2 wherein the thicknesses of the first portion of the gate dielectric layer and the second portion of the gate dielectric layer are substantially equal.

10. A method of programming the PUF circuit in claim 2, comprising: applying a program select voltage to the program select line; and applying a read select voltage to the read select line, the read select voltage exceeding the gate-to-source/drain breakdown voltage. applying a high voltage to the bit line and the source line simultaneously.

10. method of claim 10, wherein simultaneously applying the high voltage to the bit line and the source line comprising: floating the source line; applying a program control voltage to the program control line, the program control voltage exceeding the gate-to-source/drain breakdown voltage; and applying the high voltage to the bit line.

12. The method of claim 10, wherein the high voltage exceeds the gate-to-source/drain breakdown voltage.

13. The method of claim 10, wherein the high voltage is a variable voltage ramping upwards until the gate-to-source/drain breakdown voltage is reached.

14. The method of claim 10, wherein the high voltage ranges from 3V to 10V, the program control voltage ranges from 3V to 10V, and the program select voltage ranges from 1V to 3V, and the read select voltage ranges from 3V to 10V.

15. The method of claim 10, wherein the at least a program control transistor is turned on by the program control voltage, the at least a program select transistor is turned on by the at least a program select voltage, and the at least a read select transistor is turned on by the read select voltage.

16. A method of reading the PUF circuit in claim 2, comprising: applying a bit line voltage to the bit line; applying a ground voltage to the program control line, the program select line and the source line; and applying a read select voltage to the read select line.

17. The method of claim 16, wherein the bit line voltage ranges from 0.5V to 2V, the ground voltage is substantially 0V, and the read select voltage ranges from 1V to 3V.

18. The method of claim 16, wherein the at least a program control transistor and the at least a program select transistor are turned off by the ground voltage, and the at least a read select transistor is turned on by the read select voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1 is a circuit schematic of a physically unclonable function (PUF) circuit according to an embodiment of the invention.

[0008] FIG. 2 is a cross section of an exemplary PUF bit storage transistor of the PUF circuit in FIG. 1.

[0009] FIG. 3 shows a PUF bit storage transistor T.sub.DS of the PUF circuit in FIG. 1 being selected for a programming operation.

[0010] FIG. 4 shows a cross section of the PUF bit storage transistor in FIG. 3.

[0011] FIG. 5 shows a cross section of a PUF bit storage transistor of the PUF circuit in FIG. 1 set in the state “1” and being selected for a read operation.

[0012] FIG. 6 shows a cross section of a PUF bit storage transistor T.sub.DS of the PUF circuit in FIG. 1 set in the state “0” and being selected for a read operation.

[0013] FIG. 7 to FIG. 13 are schematic diagrams showing an exemplary method for fabricating the PUF bit transistor having lower gate-to-source/drain breakdown voltage according to one embodiment of the invention.

DETAILED DESCRIPTION

[0014] Advantages and features of embodiments may be understood more readily by reference to the following detailed description of preferred embodiments and the accompanying drawings. Embodiments may, however, be embodied in many different forms and should not be construed as being limited to those set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey exemplary implementations of embodiments to those skilled in the art, so embodiments will only be defined by the appended claims. Like reference numerals refer to like elements throughout the specification.

[0015] Embodiments are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures). Thus, these embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the embodiments.

[0016] It will be appreciated that although some conductivity types have been used for illustrative purposes, the invention may be practiced with opposite conductivity types. For example, an NMOS transistor in one embodiment may be replaced with a PMOS transistor in another embodiment without departing from the spirit and scope of the invention.

[0017] The present invention pertains to a physically unclonable function (PUF) circuit adopting transistors having a lower gate-to-source/drain breakdown voltage to store PUF bits, and consequently, a lower program voltage is required to program the PUF circuit, enhancing programmability. The PUF bit may randomly be in a state “1” or a state “0”. The PUF circuit may utilize a channel current instead of a ruptured or unruptured dielectric leakage current during a read operation, the channel current of reading a PUF bit in the state “1” being equal to the transistor “on” current, while the channel current of reading a PUF bit in the state “0” being equal to the transistor “off” current, leading to an easy identification of the state of the PUF bit, and reducing complexity of a reading circuitry.

[0018] FIG. 1 is a circuit schematic of a physically unclonable function (PUF) circuit 1 according to an embodiment of the invention. The PUF circuit 1 may include a 2-by-3 cell array, program control transistors T.sub.PC0 to T.sub.PC2, bit lines BL.sub.0 to BL.sub.2, source lines SL.sub.0 to SL.sub.2, a program control line PC, a ground line GND, program select lines P.sub.sel0 to P.sub.sel1, and read select lines R.sub.sel0 to R.sub.sel1. The 2-by-3 cell array may include 6 PUF cells arranged into rows R.sub.0 to R.sub.1 and columns C.sub.0 to C.sub.2. While the 2-by-3 cell array and the 3 program control transistors T.sub.PC0 to T.sub.PC2 are employed in the embodiment, the PUF circuit 1 may adopt other sizes of cell arrays and the corresponding numbers of program control transistors, bit lines, source lines, program select lines and read select lines to meet design requirement. For example, the PUF circuit 1 may include an N-by-M cell array, M program control transistors, M bit lines, M source lines, N program select lines and N read select lines, the N-by-M cell array including N×M PUF cells arranged in N rows and M columns, M, N being positive integers.

[0019] Each of the program control transistor T.sub.PC0 to T.sub.PC2 may include a gate G.sub.4 coupled to the program control line PC, a drain region D.sub.4 coupled to a respective bit line, and a source region S.sub.4 coupled to a respective source line. For example, the program control transistor T.sub.PC0 may include a gate G.sub.4 coupled to the program control line PC, a drain region D.sub.4 coupled to the bit line BL.sub.0, and a source region S.sub.4 coupled to the source line SL.sub.0.

[0020] Each PUF cell may include 3 transistors. For example, the PUF cell MC.sub.00 at the row R.sub.0 and the column C.sub.0 may include a read select transistor T.sub.RS, a PUF bit storage transistor T.sub.DS and a program select transistor T.sub.PS. The program select transistor T.sub.PS of the PUF cell MC.sub.00 may include a gate G.sub.3 coupled to the program select line P.sub.sel0, a drain region D.sub.3, and a source region S.sub.3 coupled to the ground line GND. The read select transistor T.sub.RS of the PUF cell MC.sub.00 may include a gate G.sub.1 coupled to the read select line R.sub.sel0, a drain region D.sub.1 coupled to the bit line BL.sub.0, and a source region S.sub.1. The PUF bit storage transistor T.sub.DS of the PUF cell MC.sub.00 may include a gate G.sub.2 coupled to the drain region D.sub.3 of the program select transistor T.sub.PS of the PUF cell MC.sub.00, a drain region D.sub.2 coupled to the source region S.sub.1 of the read select transistor T.sub.RS of the PUF cell MC.sub.00, and a source region S.sub.2 coupled to the source line SL.sub.0. The PUF circuit 1 may further include a semiconductor substrate on which the program control transistors T.sub.PC0 to T.sub.PC2, the program select transistors T.sub.PS, the read select transistors T.sub.RS and the PUF bit storage transistors T.sub.DS of all the PUF cells are fabricated. The semiconductor substrate may be a silicon substrate or a silicon-on-insulator (SOI) substrate, but is not limited thereto.

[0021] Each program control transistor may control the program operation of respective column of PUF cells. For example, the program control transistor T.sub.PC0 may control the program operation of the PUF cells in the column C.sub.0. The program select transistor T.sub.PS may select a PUF cell from a column of PUF cells for programming. For example, the program select transistor T.sub.PS of the PUF cell MC.sub.00 may select the PUF cell MC.sub.00 from the column C.sub.0 for programming. The read select transistor T.sub.RS may select a PUF cell for reading. For example, the read select transistor T.sub.RS of the PUF cell MC.sub.00 may select the PUF cell MC.sub.00 for reading. The PUF bit storage transistor T.sub.DS may store a PUF bit.

[0022] The read select transistors T.sub.RS, the PUF bit storage transistors T.sub.DS and the program select transistors T.sub.PS of all the PUF cells and the program control transistors T.sub.PC0 to T.sub.PC2 may be NMOS transistors, the respective drain regions D.sub.1, D.sub.2, D.sub.3, D.sub.4 and the respective source regions S.sub.1, S.sub.2, S.sub.3, S.sub.4 may be N.sup.+ doping regions, and the respective gates G.sub.1, G.sub.2, G.sub.3, G.sub.4 may be a single polysilicon (or single poly) layer or a metal gate. The read select transistors T.sub.RS, the program select transistors T.sub.PS and the PUF bit storage transistors T.sub.DS of PUF cells in the adjacent rows, e.g., the row R0 and R1, may be arranged in a symmetrical fashion as shown in FIG. 1, but are not limited to.

[0023] FIG. 2 is a cross section of an exemplary PUF bit storage transistor T.sub.DS of the PUF circuit 1. The PUF bit storage transistor T.sub.DS has a lower gate-to-source/drain breakdown voltage than a gate-to-channel breakdown voltage and a gated source/drain junction breakdown voltage, thereby enhancing program reliability.

[0024] The PUF bit storage transistor T.sub.DS comprises a drain region 104 formed on the semiconductor substrate 100, a source region 106 formed on the semiconductor substrate 100, a channel region CH formed between the drain region 104 and the source region 106, a gate dielectric layer 200 having a portion 204 formed on the drain region 104, a portion 206 formed on the source region 106, and a main portion 202 formed on the channel region CH and between the portion 204 and the portion 206, and a gate electrode 210 formed on the portions 202, 204 and 206 of the gate dielectric layer 200. The drain region 104 may be coupled to the source region S.sub.1 of the read select transistor T.sub.RS. The source region 106 may be coupled to the source line SL. The gate electrode 210 may be coupled to the drain region D.sub.3 of the program select transistor T.sub.PS.

[0025] When programming the PUF bit storage transistor T.sub.DS, high voltages may be simultaneously applied across the drain region 104 and the gate electrode 210, and across the source region 106 and the gate electrode 210, so as to rupture the portion 204 or the portion 206 in a random manner. The high voltage sufficient for rupturing the portion 204 is referred to as a gate-to-drain breakdown voltage, and the high voltage sufficient for rupturing the portion 206 is referred to as a gate-to-source breakdown voltage. Further, the high voltage sufficient for rupturing the main portion 202 is referred to as a gate-to-channel breakdown voltage.

[0026] According to one embodiment of the invention, the portions 204 and 206 have thicknesses smaller than a thickness of the main portion 202, achieving a gate-to-source/drain breakdown voltage lower than gate-to-channel breakdown voltage of the PUF bit storage transistor T.sub.DS. According to one embodiment of the invention, the portion 204 and the portion 206 are substantially equal in thickness, resulting in substantially equal gate-to-drain breakdown voltage and gate-to-source breakdown voltage.

[0027] According to one embodiment of the invention, the gate electrode 210 comprises a main gate portion 212 disposed directly above the channel region CH and two gate extension portions 214 and 216 disposed next to two opposite sidewalls of the main gate portion 212. The extension gate portion 214 is situated directly on the portion 204, and the extension portion 216 is situated directly on the portion 206. The extension gate portion 214 is in direct contact with the portion 204 of the gate dielectric layer 200 and the extension portion 216 is in direct contact with the portion 206 of the gate dielectric layer 200. According to one embodiment of the invention, the main gate portion 212, the gate extension portion 214, and the gate extension portion 216 may be composed of doped polysilicon, silicide, or metal, but is not limited thereto.

[0028] According to one embodiment of the invention, the PUF bit storage transistor T.sub.DS may further comprise dielectric spacers 224 and 226. The dielectric spacer 224 is formed beside the gate extension portion 214, and the dielectric spacer 226 is formed beside the extension portion 216. According to one embodiment of the invention, for example, the dielectric spacers 224 and 226 may comprise silicon nitride, silicon oxynitride or silicon oxide, but is not limited thereto. According to one embodiment of the invention, an end surface 204a of the portion 204 is aligned with an outer surface of the dielectric spacer 224 and an end surface 206a of the portion 206 is aligned with an outer surface of the dielectric spacer 226. According to another embodiment of the invention, the dielectric spacers 224 and 226 are in direct contact with the top surfaces of the drain region 104 and source region 106 of the PUF bit storage transistor T.sub.DS, respectively.

[0029] According to one embodiment of the invention, the PUF bit storage transistor T.sub.DS further comprises a self-aligned silicide (or salicide) layer 232 on the gate electrode 210, a salicide layer 234 on the drain region 104, and a salicide layer 236 on the source region 106. According to one embodiment of the invention, salicide layers 232, 234 and 236 may comprise NiSi, CoSi, TiSi, or WSi, but is not limited thereto. According to one embodiment of the invention, the salicide layer 234 is contiguous with the end surface 204a, and the salicide layer 236 is contiguous with the end surface 206a.

[0030] According to one embodiment of the invention, the PN junction 104a, which is between the drain region 104 and the channel region CH and is proximate to the top surface of the semiconductor substrate 100, has an end directly underneath the main gate portion 212. According to one embodiment of the invention, the PN junction 106a, which is between the source region 106 and the channel region CH and is proximate to the top surface of the semiconductor substrate 100, has an end directly underneath the main gate portion 212. By providing such configuration, a higher gated source/drain junction breakdown voltage can be provided. According to one embodiment of the invention, PUF bit storage transistor T.sub.DS has a gate-to-source/drain breakdown voltage that is lower than a gate-to-channel breakdown voltage and the gated source/drain junction breakdown voltage.

[0031] In some embodiments, the semiconductor substrate 100 may be a P type semiconductor substrate (P Substrate). In other embodiments, the semiconductor substrate 100 may adopt a triple well structure comprising a P well, a deep N well and a P substrate from top to bottom, the deep N well being formed in the P Substrate and the P well being isolated from the P type semiconductor substrate by the deep N well. During program or read operations, the P well may be biased to a predetermined P well voltage through a P well pickup region (not shown in this figure). In some embodiments, the PUF circuit 1 may further comprise other elements such as spacers on sidewalls of the gates or lightly doped drain (LDD) regions merged with the heavily doped source/drain regions, which are not explicitly shown in the figures for the sake of simplicity.

[0032] The PUF circuit 1 adopts transistors having a lower gate-to-source/drain breakdown voltage to store PUF bits, requiring a lower program voltage and enhancing programmability.

[0033] The PUF bit storage transistor T.sub.DS of each PUF cell in the PUF circuit 1 may be programmed into the state “1” or the state “0” in a random manner. FIG. 3 shows the PUF bit storage transistor T.sub.DS being selected for programming. FIG. 4 shows a cross section of the PUF bit storage transistor T.sub.DS in FIG. 3. In the programming operation, a method of programming the PUF circuit 1 may include the following steps:

[0034] (i) grounding the semiconductor substrate 100 and the ground line GND;

[0035] (ii) electrically floating the selected source line SL;

[0036] (iii) turning on the program select transistor T.sub.PS by applying a program select voltage V.sub.Psel to the selected program select line P.sub.sel, thereby coupling the gate G.sub.2 of the PUF bit storage transistor T.sub.DS to ground;

[0037] (iv) turning on the read select transistor T.sub.RS by applying a read select voltage V.sub.Rsel to the selected read select line R.sub.sel, wherein the read select voltage V.sub.Rsel is higher than the gate-to-drain/source breakdown 200;

[0038] (v) turning on the program control transistor T.sub.PC by applying a program control voltage V.sub.PC higher than the gate-to-source breakdown voltage to the selected program control line PC, thereby coupling the selected source line SL to the selected bit line BL; and

[0039] (vi) ramping up a bit line voltage V.sub.BL applied to the selected bit line BL through a current limiter until one of the first portion 204 and the second portion 206 breaks down, causing V.sub.BL to drop and, thus, leaving the other intact.

[0040] Table 1 shows an exemplary bias condition for programming the selected PUF cell in FIG. 3.

TABLE-US-00001 TABLE 1 Program bias Condition Terminal Bias Voltage PC, V.sub.PC 3-10 V Selected P.sub.Sel, V.sub.Psel 1-3 V Selected R.sub.Sel, V.sub.Rsel 3-10 V Unselected P.sub.Sel, unselected R.sub.Sel 0 V Selected BL, V.sub.BL 3-10 V or Ramp up from 0 V till breakdown Unselected BL 0 V or Floating Selected SL, V.sub.SL Floating Unselected SL 0 V or Floating P-well, V.sub.PW 0 V or Floating V.sub.PSub/V.sub.DNW 0 V or Floating

[0041] According to one embodiment of the invention, to program the selected the PUF cell in the PUF circuit 1, the following bias conditions may be implemented:

[0042] (i) a high enough program control voltage V.sub.PC ranging between, for example, 3-10V is applied to the program control line PC;

[0043] (ii) a program select voltage V.sub.Psel of about 1-3V is applied to the selected program select line P.sub.sel (selected P.sub.sel) to turn on the program select transistor T.sub.PS;

[0044] (iii) a high enough read select voltage V.sub.Rsel ranging between, for example, 3-10V is applied to the selected read select line R.sub.sel (selected R.sub.sel);

[0045] (iv) all the unselected program select lines P.sub.sel (unselected P.sub.sel) and unselected read select lines R.sub.sel (unselected R.sub.sel) are connected to ground GND (or 0V);

[0046] (v) the semiconductor substrate 100 (e.g., P Substrate) is usually connected to ground (V.sub.PSub=0V), and for the triple well structures, the deep N well 110 is connected to ground (V.sub.DNW=0V) while the P well 120 may be floating or connected to ground (V.sub.PW=0V or floating);

[0047] (vi) the selected source lines SL are floating and all the unselected source lines SL and the unselected bit lines BL are floating or connected to ground (0V); and

[0048] (vii) the selected bit line voltage V.sub.BL is ramped up, preferred to be through a current limiter to prevent overloading the bit line voltage supply circuit, until a sudden drop in the bit line voltage V.sub.BL, indicating completion of the programming operation.

[0049] Alternatively, the dielectric breakdown may be caused by simply applying a pre-set bit line voltage V.sub.BL that is higher than the gate-to-source/drain breakdown voltage to the selected bit line BL, which is also preferred to be done through a current limiter to prevent overloading the bit line voltage supply circuit.

[0050] Any reasonable technological change or step adjustment made to the method of programming the PUF circuit 1 is within the scope of the disclosure.

[0051] The PUF bit storage transistor T.sub.DS may have a source junction breakdown voltage and a drain junction breakdown voltage, which are higher than the gate-to-source/drain breakdown voltage of the PUF bit storage transistor T.sub.DS. However, this is not necessary for the embodiments with triple well structures. Further, the gate-to-source/drain breakdown voltage and the source/drain junction breakdown voltage of the read select transistor T.sub.RS are both higher than the gate dielectric breakdown voltage of the PUF bit storage transistor T.sub.DS. This can be achieved by using thicker gate dielectric or cascoding two transistors for the read select transistor T.sub.RS.

[0052] The PUF bit may be read from each PUF cell. FIG. 5 shows a cross section of the PUF bit storage transistor T.sub.DS set in the state “1” and being selected for a read operation. FIG. 6 is a cross section of the PUF bit storage transistor T.sub.DS set in the state “0” and being selected for a read operation. In the read operation, a method of reading the PUF bit storage transistor T.sub.DS may include the following steps:

[0053] (i) the program control line PC is connected to ground (0V) to turn off all program control transistors T.sub.PC, disconnecting the source line SL from the bit line BL;

[0054] (ii) all the program select lines P.sub.sel are connected to ground (0V) to turn off all program select transistors T.sub.PS so that all the gates G.sub.2 of the PUF bit storage transistors T.sub.DS are isolated from the outside bias. Therefore, the voltage of the gate G.sub.2 of the PUF bit storage transistor T.sub.DS is the same as that of the drain region D.sub.2 if the dielectric breakdown B, caused during the programming operation, is on the drain side (as in FIG. 5), and the same as that of source region S.sub.2 if the dielectric breakdown B is on the source side (as in FIG. 6);

[0055] (iii) a read select voltage V.sub.RSel of about 1-3V is applied to the selected read select lines R.sub.sel so that drain of the selected PUF bit storage transistor T.sub.DS is connected to the selected bit line BL to which a bit line voltage V.sub.BL of 0.5-2V is applied; and

[0056] (vi) all the other terminals are connected to ground (0V).

[0057] Table 2 shows an exemplary bias condition for reading the PUF bit storage transistor T.sub.DS in FIGS. 5 and 6.

TABLE-US-00002 TABLE 2 Read Bias Condition Terminal Bias Voltage PC, V.sub.PC 0 V All P.sub.Sel 0 V Selected R.sub.Sel 1-3 V Unselected R.sub.Sel, 0 V Selected BL 0.5-2 V Unselected BL 0 V or Floating All SL 0 V Others 0 V

[0058] Under the aforesaid read bias conditions, the PUF bit storage transistor T.sub.DS has a high channel current CL if the dielectric breakdown B is on the drain side because the gate voltage is high and substantially equal to the voltage applied to the drain region D.sub.2, and the PUF bit storage transistor T.sub.DS (“1” state) is turned on. On the other hand, for the PUF bit storage transistor T.sub.DS in “0” state, there is no channel current (or only an insignificant amount of off-current) because the voltage coupled to the gate G.sub.2 is low, same as the voltage applied to the source region S.sub.2, and the PUF bit storage transistor T.sub.DS (“0” state) is turned off. Therefore, the read current path is not through the ruptured dielectric, but is through the channel region CH of the PUF bit storage transistor T.sub.DS.

[0059] According to some embodiments, all the isolated gates G.sub.2 of the PUF bit storage transistors T.sub.DS may be pre-charged by turning on all read select transistors T.sub.R simultaneously and applying 0.5-2V to all bit lines BL and 0V to all source line SL for a short period of time (e.g., 3 ms) prior to reading the entire PUF circuit 1. This can prevent those soft breakdown bits from errors due to slow charging.

[0060] To program and read the random code of the whole PUF array, conventional peripheral circuits including control circuits, multiplexer circuits, sensing circuit, etc., not shown, can be implemented. Since the cell current difference between “0” and “1” is very significant, a simple logic gate such as a NOT gate or an inverter sensing circuit, instead of complicate sensing amplifier or comparator circuit, may be used in some embodiments.

[0061] FIG. 7 to FIG. 13 are schematic diagrams showing an exemplary method for fabricating the PUF bit storage transistor having lower gate-to-source/drain breakdown voltage according to one embodiment of the invention, wherein like layers, elements or regions are designated by like numeral numbers or labels.

[0062] As shown in FIG. 7, a semiconductor substrate 100 such as a P type silicon substrate is provided. A gate dielectric layer 200 such as silicon dioxide (SiO2), silicon oxynitride (SiON) or hafnium dioxide (HfO2) is deposited on the semiconductor substrate 100. According to one embodiment, the gate dielectric layer 200 may have a thickness of about 2-20 nm, but is not limited thereto. A first conductive layer 210a such as N-doped polysilicon, silicide or metal is then deposited on the gate dielectric layer 200. According to one embodiment, the first conductive layer 210a may have a thickness of about 80-200 nm, but is not limited thereto. Optionally, a cap nitride layer 230 may be deposited on the first conductive layer 210a. For example, the cap nitride layer 230 may be a silicon nitride layer and may have a thickness of about 5-10 nm.

[0063] It will be appreciated that although some conductivity types have been used for illustrative purposes, the invention may be practiced with opposite conductivity types.

[0064] Subsequently, as shown in FIG. 8, a photoresist pattern PR is formed on the cap nitride layer 230 to define gate area. An anisotropic etching process 500 is then performed to remove the cap nitride layer 230 and the first conductive layer 210a not covered by the photoresist pattern PR, thereby forming a main gate portion 212. At this point, the gate dielectric layer 200 is substantially not etched.

[0065] As shown in FIG. 9, the remaining photoresist pattern PR is removed. An ion implantation process 600 is then performed to implant N type dopants into the semiconductor substrate 100, followed by an optional annealing step, thereby forming N+ drain region 104 and N+ source region 106. According to one embodiment, the N+ drain region 104 and N+ source region 106 may be formed with graded junction, which may be formed by using, for example, doubly diffused method, for higher junction breakdown voltage.

[0066] As shown in FIG. 10, an etching process is performed to remove an upper portion of the gate dielectric layer 200, thereby forming a thinner portions 204 and 206 on the N+ drain region 104 and the N+ source region 106, respectively. The portions 204 and 206 may be thinned down to thickness of 30-70% of the original thickness. According to one embodiment, the etching process may be a wet etching process, but is not limited thereto. It is understood that in some embodiments the ion implantation process 600 in FIG. 9 may be performed after gate dielectric thinning down.

[0067] As shown in FIG. 11, a second conductive layer 210b such as N-doped polysilicon, silicide or metal is deposited on the semiconductor substrate 100. The second conductive layer 210b conformally covers the main gate portion 212 and the thinner portions 204 and 206. The second conductive layer 210b is in direct contact with the sidewalls of the main gate portion 212. According to one embodiment, the second conductive layer 210b may have a thickness of about 20-100 nm,

[0068] As shown in FIG. 12, an anisotropic etching process 700 is then performed to etch the second conductive layer 210b, thereby forming extension gate portions 214 and 216 on the opposite sidewalls of the main gate portion 212. The extension gate portion 214 is situated directly on the portion 204 of the gate dielectric layer 200 and the extension portion 216 of the gate electrode 210 is situated directly on the portion 206 of the gate dielectric layer 200.

[0069] Optionally, the cap nitride layer 230 is removed. Subsequently, a dielectric spacer 224 and a dielectric spacer 226 are, as shown in FIG. 13. It is understood that the cap nitride layer 230 can also be removed at an etch step during formation of dielectric spacers 224 and 226.

[0070] The outer surface of the extension gate portion 214 is covered with the dielectric spacer 224 and the outer surface of the extension portion 216 is covered with the dielectric spacer 226. According to one embodiment of the invention, for example, the dielectric spacers 224 and 226 may comprise silicon nitride, silicon oxynitride or silicon oxide, but is not limited thereto. According to one embodiment of the invention, an end surface 204a of the portion 204 is aligned with an outer surface of the dielectric spacer 224 and an end surface 206a of the portion 206 is aligned with an outer surface of the dielectric spacer 226. Therefore, the dielectric spacer 224 is situated on the portion 204, and the dielectric spacer 226 is situated on the portion 206.

[0071] A self-aligned silicidation process is then performed to form a salicide layer 232 on the gate electrode 210, a salicide layer 234 on the drain region 104, and a salicide layer 236 on the source region 106. According to one embodiment of the invention, salicide layers 232, 234 and 236 may comprise NiSi, CoSi, TiSi, or WSi, but is not limited thereto. According to one embodiment of the invention, the salicide layer 234 is contiguous with the end surface 204a of the portion 204, and the salicide layer 236 is contiguous with the end surface 206a of the portion 206.

[0072] According to one embodiment of the invention, the vertical PN junction 104a proximate to the top surface of the semiconductor substrate 100 is situated directly underneath the main gate portion 212. According to one embodiment of the invention, the vertical PN junction 106a proximate to the top surface of the semiconductor substrate 100 is situated directly underneath the main gate portion 212. By providing such configuration, a higher gated source/drain junction breakdown voltage can be provided. According to one embodiment of the invention, the PUF bit storage transistor T.sub.DS has a gate-to-source/drain breakdown voltage that is lower than a gate-to-channel breakdown voltage and the gated source/drain junction breakdown voltage.

[0073] As shown in FIG. 13, an interlayer dielectric (ILD) layer 240 is then deposited on the semiconductor substrate 100. The ILD layer 240 covers the PUF bit storage transistor T.sub.DS. Subsequently, a contact plug 244 and a contact plug 246 may be formed in the ILD layer 240. An interconnect structure 254 and an interconnect structure 256 may be formed on the ILD layer 240. The interconnect structure 254 is electrically connected to the drain region 104 through the contact plug 244. The interconnect structure 256 is electrically connected to the source region 106 through the contact plug 246.

[0074] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.