Transimpedance amplifiers

Abstract

The application describes a transimpedance amplifier circuit having a first circuit branch extending between first and second supply nodes. An input NMOS transistor is located in the first circuit branch, with its drain terminal coupled to the first supply node via a load resistor, its source terminal coupled to the second supply node and its gate terminal coupled to an input node for receiving an input signal. The circuit includes a PMOS transistor having its source terminal coupled to a third supply node, its drain terminal coupled to the first circuit branch, at a node in a part of the first circuit branch extending from the drain terminal of the input transistor to the load resistor, and its gate terminal coupled to the input node. A drain current of the PMOS transistor contributes a proportion but not all of a drain current for input NMOS transistor.

Claims

1. A transimpedance amplifier comprising: a first circuit branch extending between first and second supply nodes; an input NMOS transistor located in the first circuit branch, the input transistor having a drain terminal coupled to the first supply node via a load resistor, a source terminal coupled to the second supply node and a gate terminal coupled to an input node for receiving an input signal; a PMOS transistor having a source terminal coupled to a third supply node, a drain terminal coupled to the first circuit branch at a node in a part of the first circuit branch extending from the drain terminal of the input transistor to the load resistor, and a gate terminal coupled to said input node; wherein, in use, a drain current of the PMOS transistor contributes a proportion but not all of a drain current for input NMOS transistor.

2. The transimpedance amplifier of claim 1 wherein the gate terminal of the PMOS transistor is coupled directly to said input node.

3. The transimpedance amplifier of claim 1 wherein the gate terminal of the PMOS transistor is coupled to said input node via a capacitor.

4. The transimpedance amplifier of claim 1 wherein the gate terminal of the PMOS transistor is coupled to said input node via a buffer.

5. The transimpedance amplifier of claim 1 wherein, in use, a voltage at the third supply node has a lower magnitude than a voltage at the first supply node.

6. The transimpedance amplifier of claim 1 wherein the second supply node is a ground node.

7. The transimpedance amplifier of claim 1 comprising a supply generator configured to provide a supply current to the third supply node, wherein the supply generator is configured such that at least part of the supply current for the third supply node also forms at least part of a supply current for powering another circuit block.

8. The transimpedance amplifier of claim 7 wherein the supply generator comprises a pass transistor for passing said supply current to the third supply node and a regulator for controlling the pass transistor to maintain a voltage of the third supply node equal to a reference voltage, wherein the pass transistor is coupled in series between said other circuit block and the third supply node.

9. The transimpedance amplifier of claim 7 wherein the supply generator comprises a current mirror having an input current branch for supplying a defined current to the third supply node and at least one output current branch for supplying a scaled current, where the at least one output current branch is between said other circuit block and the third supply node.

10. The transimpedance amplifier of any of claim 7 wherein said other circuit block comprises at least part of a stage of the transimpedance amplifier downstream of the first circuit branch.

11. The transimpedance amplifier of claim 1 wherein the first circuit branch further comprises at least one cascode NMOS transistor.

12. The transimpedance amplifier of claim 1 further comprising at least one supplemental current generator for supplying a fixed supplemental current to a node of the first circuit branch between the drain terminal of the input transistor and the load resistor.

13. The transimpedance amplifier of claim 1 wherein the first circuit branch is configured as at least part of an inverting amplifier of an input stage of the transimpedance amplifier.

14. The transimpedance amplifier of claim 13 further comprising a feedback path from an output of the inverting amplifier to said input node via a feedback resistor.

15. The transimpedance amplifier of claim 1 wherein the transimpedance amplifier is implemented as part of an optical receiver comprising a photodetector coupled to said input node.

16. An amplifier circuit for an input stage of a transimpedance amplifier, the amplifier circuit comprising: an input NMOS transistor having a gate terminal controlled based on an input signal to develop a drain current that varies with the input signal; and a PMOS transistor configured to generate a PMOS current which provides part of the drain current for the input NMOS transistor; wherein the PMOS transistor is configured so that the PMOS current varies with the input signal.

17. The amplifier circuit of claim 16 wherein at least part of supply current for the PMOS transistor also forms at least part of a supply current for powering at least one other circuit component.

18. A transimpedance amplifier circuit comprising: a first circuit branch comprising a load resistor and an input transistor configured as a common-source amplifier for an input signal; and a PMOS transistor configured to inject a PMOS current into the first circuit branch at a node between the input transistor and the load resistor, wherein the PMOS current varies with the input signal.

19. The transimpedance amplifier circuit of claim 18 wherein the first circuit branch further comprises at least one cascode transistor between the input transistor and the load resistor.

20. The transimpedance amplifier circuit of claim 18 wherein a gate of the PMOS transistor is coupled to an input node for the input signal via one of: a direct coupling; a capacitive coupling; or a buffer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) To better explain various embodiments and examples of the present disclosure and the principles, example implementation and operation thereof, reference will be made, by way of example only, to the accompanying drawings, of which:

(2) FIG. 1 illustrates the architecture of a conventional TIA input stage arranged as part of an optical receiver;

(3) FIGS. 2a and 2b illustrate examples of conventional amplifiers for an input stage of a TIA;

(4) FIG. 3 illustrates an example of an amplifier according to an embodiment suitable for use as an input stage of a TIA;

(5) FIG. 4 illustrates one example of circuitry for providing a supply to the PMOS of the input stage in which the supply current is also used for powering another circuit block;

(6) FIG. 5 illustrates another example of a supply generator that enables re-use of the supply current for the PMOS device; and

(7) FIG. 6 illustrates an example of a circuit block that could be powered by such a re-use supply current.

DETAILED DESCRIPTION

(8) As discussed above with respect to FIG. 1, the performance of a TIA (transimpedance amplifier) input stage may depend, relatively significantly, on that of the inverting amplifier.

(9) FIG. 2a shows one example of a conventional implementation of an inverting amplifier 101 that may be employed in a TIA input stage 100 such as described with reference to FIG. 1. The amplifier 101 has an input node 201 for receiving an input voltage V.sub.IN, and an output node 202 for outputting and output voltage V.sub.OUT. A transistor M.sub.N0 is configured as a common-source amplifier. The input transistor M.sub.N0 is thus configured in a first circuit branch with its source terminal coupled to a negative supply node or rail V.sub.SS, for example ground and its gate terminal coupled to the amplifier input node 201. The first circuit branch also includes a load resistor R.sub.L connected to a positive node or supply rail V.sub.DDL on the drain terminal side of the input transistor, and the amplifier output node couples to the first circuit branch between the load resistor R.sub.L and the input transistor M.sub.N0.

(10) Such a common-source amplifier would, to a simplistic first approximation, have a voltage gain given by A=−g.sub.m(M.sub.N0)*R.sub.L. However, this simplification neglects the effect of MOS output resistance (r.sub.ds), which reduces the gain of the amplifier. The conventional solution to this issue is to cascode the amplifier with the addition of transistor M.sub.N1 in series with the drain of M.sub.N0 in the first circuit branch, with the gate of the cascode transistor M.sub.N1 driven from voltage V.sub.C1. V.sub.C1 may be a constant voltage or may be variable; for example, a circuit may sense a voltage at V.sub.S1, and control V.sub.C1 in order to regulate the former. Typically the input transistor M.sub.N0 and the cascode transistor M.sub.N1 are implemented as NMOS devices due to their greater intrinsic performance, such as a higher transconductance for a given operating current and width/length ratio, compared to PMOS devices.

(11) For some small-geometry CMOS processes in which the r.sub.ds of MOS transistors is particularly low, it may be desirable to employ more than one cascode stage, as shown in FIG. 2b, in which the amplifier is illustrated as including 1 to n cascode stages, in order to achieve a desired magnitude of voltage gain A of the amplifier. Thus there may be a plurality of cascode transistors in series with the input transistor in the first circuit branch.

(12) It will be understood that magnitude of the voltage gain A could be increased simply by increasing R.sub.L. However, a larger value of R.sub.L reduces the open-loop bandwidth of the inverting amplifier, due to the various load capacitances on V.sub.OUT. A sufficient open-loop bandwidth is important to ensure the stability and favourable frequency response of the feedback loop, closed via R.sub.FB as discussed with reference to FIG. 1. For any chosen value of R.sub.L, constrained by the open-loop bandwidth requirement, it is beneficial to make the voltage of the supply rail V.sub.DDL as high as possible. This maximizes the DC component of current I.sub.L and therefore the drain current I.sub.D of M.sub.N0, in turn maximizing its achievable transconductance g.sub.m, which improves the voltage gain A of the amplifier.

(13) In the examples of FIGS. 2a and 2b, the DC component drain current I.sub.D, and therefore transconductance g.sub.m, of the input NMOS transistor M.sub.N0 is increased by the addition of a supplemental bias current, consisting of the sum of I.sub.SUP1 . . . I.sub.SUPn, which may be applied to the first circuit branch at any or all of the cascode source nodes V.sub.S1 . . . V.sub.Sn. In such an arrangement, I.sub.D is equal to the sum of I.sub.L plus the total of any supplemental bias current(s) I.sub.SUP1 . . . I.sub.SUPn. The supplemental bias current may be supplied via resistors R.sub.1 . . . R.sub.n from positive supply rail V.sub.DDS (which may be the same as V.sub.DDL).

(14) The resistors R.sub.1 . . . R.sub.n place an unwanted load on the AC signal present at cascode source nodes V.sub.S1 . . . V.sub.Sn, which degrades the voltage gain A of the amplifier to some extent, however, the benefits of increased I.sub.D due to the addition of I.sub.SUP1 . . . I.sub.SUPn can outweigh the detrimental loading effect of the resistors. In order to maximize the benefit, it is preferable to make V.sub.DDS as high as possible in order to maximize the value of resistors R.sub.1 . . . R.sub.n, minimizing their loading effect, for any chosen values of I.sub.SUP1 . . . I.sub.SUPn. It will be noted that the supplemental bias current could alternatively be supplied from a constant current source, although the output capacitance of a practical current source (for example using a PMOS current mirror) may make this option less desirable.

(15) The application of the supplemental bias current I.sub.SUP1 . . . I.sub.SUPn thus has benefits for the performance of the amplifier 101, but at the expense of increasing power consumption. In some implementations, the degree of improvement in performance achievable by the application of a supplemental bias current may be limited by constraints on power consumption, for example due to a supply current budget for the TIA input stage, in order to meet a particular specification for the maximum allowable total supply current, and therefore power consumption, of the TIA circuit or integrated circuit comprising the TIA.

(16) FIG. 3 illustrates an amplifier 300 according to an embodiment, suitable for use as the inverting amplifier of a TIA input stage. The amplifier 300 includes an input node 301 for receiving the input voltage V.sub.IN and an output node 302 for outputting an output voltage V.sub.OUT and includes, in this example, an input transistor M.sub.N0 and a cascode transistor M.sub.N1 in a first circuit branch in a similar fashion as described with respect to FIGS. 2a and 2b. As described above, the input transistor M.sub.N0 and cascode transistor M.sub.N1 may be NMOS devices.

(17) In the embodiment of FIG. 3, a PMOS transistor M.sub.P0 is configured to provide a current I.sub.P which provides a contribution to the drain current of input transistor M.sub.N0. However, unlike the supplementary currents I.sub.SUP1-I.sub.SUPn discussed with reference to FIGS. 2a and 2b, which are generated with fixed nominal current values, i.e. so as to be substantially constant, the current I.sub.P from the PMOS transistor M.sub.P0 is configured so as to vary with the input signal, i.e. to be modulated based on the PMOS transistor gate being coupled to V.sub.IN.

(18) Effectively, this enhances the gain of the amplifier, whose input transconductance becomes the sum of g.sub.m(M.sub.N0)+g.sub.m(M.sub.P0). This increase in g.sub.m results in an improvement in the open-loop gain A of the inverting amplifier 300, compared to the examples of FIG. 2a or 2b, for the same total supply current. This, in turn, enables a beneficial increase in the gain-bandwidth product of the TIA input stage.

(19) In the example of FIG. 3, the source of PMOS transistor M.sub.P0 is thus connected to a positive supply node V.sub.DDP and its drain is coupled to a node of the first circuit branch, in this example cascode source node V.sub.S1. In general, however, the drain of the PMOS transistor M.sub.P0 could be connected to any node of a part of the first circuit branch that extends from the drain terminal of the input transistor M.sub.N0 to the load resistor, which, for the avoidance of doubt, includes the drain terminal of the NMOS transistor M.sub.N0. To provide a current I.sub.P that varies with input signal, the gate of M.sub.P0 is coupled to the input node 301 so that the gate voltage of M.sub.P0 has a dependence on the input voltage V.sub.IN. The coupling 303 of the gate of M.sub.P0 to the input node 301 may be implemented in a variety of ways, and FIG. 3 illustrates some examples of different couplings. In some implementations the gate of M.sub.P0 could be directly coupled to the input node 301, e.g. via a suitable conductive path as illustrated by coupling 301a. In some implementations there may be a capacitive coupling, e.g. via a capacitor 303b, between the input node 301 and the gate of M.sub.P0, which would allow the DC bias voltage of the gate of M.sub.P0 to be freely defined, whilst allowing the gate voltage to vary with any variations in the input voltage. In some implementations there could be a coupling via a buffer 303c, which would alleviate the loading of the gate capacitance of M.sub.P0 from the amplifier input node 301.

(20) It should be noted that the current I.sub.P supplied to first circuit branch, in this case to the cascode source node V.sub.S1, may be in addition to, or instead of, any fixed magnitude supplementary bias current(s) I.sub.SUP1 . . . I.sub.SUPn, (not shown in FIG. 3) such as described with reference to FIGS. 2a and 2b, which may be injected at the same and/or different nodes of the first circuit branch. Also, whilst FIG. 3 illustrates an example with a single cascode stage, i.e. n=1, in other implementations there may be additional cascode stages, i.e. there may be additional cascode transistors as part of the first circuit branch.

(21) The DC drain current I.sub.D of M.sub.N0 in the embodiment of FIG. 3 is equal to the sum of I.sub.P plus I.sub.L, (plus, if applicable, any additional supplemental bias currents I.sub.SUP1 . . . I.sub.SUPn applied to nodes of the first circuit branch). The PMOS drain current I.sub.P is configured to contribute a significant proportion of the total M.sub.N0 drain current I.sub.D, although substantially less than 100% of this drain current. For example, in one implementation the current I.sub.P supplied from the PMOS device may contribute at least 10% or more, or in some cases, at least 20% or more, say at least 50% or more, of the drain current I.sub.D for the input transistor. In some implementations the current I.sub.P supplied from the PMOS device may contribute at most 90%, or at most 80%, or in some cases at most 75% of the DC component of the drain current. It will be understood however that the relevant contribution may vary in different implementations and/or use cases.

(22) As noted above, the use of an active PMOS device M.sub.P0 in this way, can improve the gain of the amplifier for a given supply current budget compared to the conventional approach, which thus provides advantages in performance and/or power consumption.

(23) Embodiments of the present disclosure thus relate to amplifiers suitable for use as the input stage for a TIA. Amplifiers according to embodiments comprise an input transistor, typically an NMOS device, connected in a first circuit branch, with the gate of input transistor driven by the input voltage and the drain of the input transistor coupled to a supply voltage via a load resistance. As noted the input transistor may be configured as at least part of a common-source amplifier. Amplifiers according to embodiments of the disclosure include a PMOS transistor configured to be driven with a gate voltage that varies in dependence on the input signal so as to provide a PMOS current which is injected to the first circuit branch so as to provide part of the drain current for the input transistor, and to contribute to the transconductance that substantially determines the amplifying ability of the circuit. As discussed above, conventional circuit designs tend to be architected to use predominantly or exclusively NMOS devices as the active gain elements along the critical high-speed signal path. Embodiments of the present disclosure incorporates a PMOS device in an active role, replacing or supplementing a bias current that would otherwise be supplied through a resistor or a constant current source. The addition of the PMOS device enables a higher total transconductance in the input stage of the TIA, fora given supply current, than would be possible with an NMOS device alone.

(24) The use of the PMOS device in this way also provides opportunity for the re-use of a portion of the TIA input stage supply current for powering a separate block of circuitry, enabling a reduction in power consumption of the IC comprising the TIA as a whole.

(25) In the embodiment of FIG. 3, there is no strong incentive to use a high voltage for the voltage V.sub.DDP of the supply node for the PMOS M.sub.P0. This is in contrast to the supply node or rail V.sub.DDL for the first circuit branch and the supply node or rail V.sub.DDS for generating any supplemental current(s) I.sub.SUP which, as described above can benefit from being set to be as high as possible. For example, in the simple case where the source of M.sub.N0 is grounded and the gate of M.sub.P0 is directly connected to V.sub.IN, the required voltage for the supply node V.sub.DDP for the PMOS M.sub.P0 is simply equal to V.sub.GS(M.sub.N0)+V.sub.GS(M.sub.P0). The supply node V.sub.DDP for the PMOS device M.sub.P0 may thus have a voltage with a magnitude lower than that of the supply node V.sub.DDL for the circuit branch comprising the input transistor M.sub.N0.

(26) In some implementations, a supply voltage for the TIA circuit, e.g. an external supply voltage provided to the integrated circuit comprising the TIA, may be higher than the minimum voltage required for this supply node V.sub.DDP, and in such cases the V.sub.DDP supply current may effectively be re-used by some other circuit block so as to avoid for the need for a separate supply current and hence provide power savings for the integrated circuit comprising the TIA.

(27) FIG. 4 shows an example of a circuit 400, e.g. a voltage regulator, for generating an appropriate voltage V.sub.DDP for the supply node for the PMOS M.sub.P0 whilst using the relevant supply current for some other separate circuit block 401 or module.

(28) FIG. 4 illustrates that a reference voltage V.sub.GSN+V.sub.GSP is generated by dropping a bias current I.sub.BIAS generated by current source 402 through a series-connected pair of NMOS and PMOS transistors 403. The reference voltage is thus equal to the sum of the gate source voltage V.sub.GSN of the NMOS device and the gate source voltage V.sub.GSP of the PMOS device of the pair. The transistor pair 403 may comprise scaled replicas of M.sub.N0 and M.sub.P0, for example, biased at similar current densities. The reference voltage thus defines a suitable voltage for the supply rail V.sub.DDP for the PMOS M.sub.P0.

(29) An op-amp 404 drives the gate of a pass transistor M.sub.REG, to regulate the voltage V.sub.DDP to be equal to the reference voltage. The AC components of the M.sub.P0 load current are decoupled by capacitance C.sub.D, so that the drain current I.sub.REUSE of the pass transistor M.sub.REG is nominally equal to the DC average of current I.sub.P. This drain current I.sub.REUSE of the pass transistor is used in the negative supply current terminal of the separate circuit block 401, and thus this current is effectively re-used by the circuit block 401. This avoids the need for a separate supply currents for the circuit block 401 and the active PMOS device M.sub.P0, which thus offers power savings for the circuit as a whole. Note that as used herein, the term ‘re-used’ in respect to a current means that that a particular current component can be identified as flowing through a first circuit block, to be used to provide power, and that that current component can also be identified as flowing through a second circuit block where it is re-used to provide power. In other words, a defined current path can be identified that passes through two or more circuit blocks in series such that a current flowing along that defined current paths provides power for both circuit blocks. It should be noted the term re-use does not imply anything about the relative order in which the circuit blocks are connected with respect to any supply voltage. If a current component can be identified as flowing to provide power in a first circuit block and that current component also flows through a second identified circuit block, the current can be said to be re-used by the second circuit block, whether or not the second circuit block is connected upstream or downstream of the first circuit block.

(30) It will be understood that reference voltages other than V.sub.GSN+V.sub.GSP could equally be generated and used in such a circuit, for example for configurations where the PMOS transistor M.sub.P0 requires different values of supply node voltage V.sub.DDP.

(31) FIG. 5 shows another example of a circuit 500, e.g. supply generator, for generating a suitable supply for the supply node V.sub.DDP for PMOS M.sub.P0 whilst also using the supply current for a separate circuit block 401. In this example circuit 500, V.sub.DDP is supplied from a current mirror 501 with a ratio of 1:k, biased with a reference current laws from current source 502. The current mirror 501 generates a current I.sub.REUSE with a value equal to k*I.sub.BIAS at the negative supply terminal of the circuit block 401. Again a decoupling capacitor C.sub.D may decouple the AC components of the M.sub.P0 load current, so the DC average of current I.sub.P becomes equal to (1+k)*I.sub.BIAS. Thus at least a proportion of the current I.sub.P for the PMOS M.sub.P0 is also as a supply current for the circuit block 401.

(32) Note that FIG. 5 illustrates a single circuit block 401 being supplied with a single current I.sub.REUSE. However the current mirror 501 could be arranged so that bias current I.sub.BIAS, input to an ‘input branch’ of the current mirror is used to generate multiple scaled currents in different output branches, i.e. a first scaled current I.sub.REUSE1 equal to k.sub.1*I.sub.BIAS and a second scaled current I.sub.REUSE2 equal to k.sub.2*I.sub.BIAS etc. as would be understood by one skilled in the art. Some scaling factors, e.g. k.sub.1 and k.sub.2, could be the same as one another and/or at least some scaling factors could be different to one another, to provide the desired total combined current. The individual scaled current, e.g. I.sub.REUSE1, I.sub.REUSE2 etc. from the different output branches of the current mirror may be used for separately powering different components within a circuit block 401 and/or for powering different circuit blocks.

(33) FIG. 6 illustrates one example of a circuit block 401 that, with minor adaptation, could be suitably powered by re-using the supply current for the V.sub.DDP supply rail for PMOS M.sub.P0, in this case a differential amplifier circuit, such as that which may be employed in the amplifier stages 105 that typically succeed the input stage 100 of a TIA.

(34) FIG. 6a, on the left hand side, illustrates a conventional differential amplifier circuit that may be implemented, with respective input transistors connected in parallel and in series with a common current source for providing a defined tail current I.sub.TAIL. FIG. 6b illustrates that the supply current I.sub.REUSE may be used to provide the tail current for the differential amplifier 401 and thus replace the conventional current source. In this case, the inputs to the differential amplifier may need to be AC-coupled and biased to a suitable DC reference voltage V.sub.BIAS, higher than V.sub.DDP by a sufficient margin to ensure the correct biasing of the circuit, e.g. so as to ensure a sufficient gate-source voltage V.sub.GSN for the input transistors.

(35) It should be noted that the circuit of FIG. 6 is just one example of a circuit block that could be configured (or slightly reconfigured) to make use of the current I.sub.REUSE and there are many other possible examples of circuit blocks that may be powered by I.sub.REUSE. The supply current for any such circuit block is re-used to supply V.sub.DDP and therefore to form the DC component of PMOS drain current I.sub.P. Since, as described above, I.sub.P is supplied to the first circuit branch of the amplifier of the TIA input stage, i.e. the NMOS device stack, in substitution for some or all of a supplementary current I.sub.SUP1 . . . I.sub.SUPn that would conventionally be supplied, embodiments that re-use the current in this way save the supply current that would otherwise have been drawn independently from V.sub.DDS, and ultimately from the IC power supply VDD. This aspect therefore enables a reduction in the total supply current of the IC comprising the TIA. In implementations where the power consumption is an important or limiting factor, constraining the design of a TIA IC, the supply current saved through such re-use of the current may be re-invested to improve other aspects of TIA performance, for example by increasing the total supplemental bias current in the TIA input stage.

(36) Embodiments of the present disclosure thus provide amplifiers suitable for use for the input stage of a TIA that offer improvements in performance and/or power consumption compared to conventional implementations, through the use of an active PMOS device to supply a current which forms part of the drain current for an input transistor, where the current varies with the amplifier input. In some embodiments, at least part of the current supplied by the PMOS device may also be re-used in another part of the TIA circuit so as to save power.

(37) Embodiments may be implemented as an integrated circuit. In some embodiments the TIA input stage may be implemented as part of an optical receiver. Embodiments may be incorporated in a host electronic device.

(38) It will be understood that the examples and embodiments described above are given by way of example only and those skilled in the art will understand that modifications, variations, additions or alterations may be made to specific embodiments described, or alternative embodiments may be implemented, without departing from the scope of the appended claims.

(39) It should be noted that as used herein, unless expressly stated otherwise, the word “comprising” does not exclude the presence of other elements or steps other than those listed, references to an element or feature in the singular does not exclude the possibility of a plurality of such elements or features, and that recitation of different features or elements in the appended claims does not necessarily imply separate components; a single component or unit may fulfil the function of several elements recited in a claim. Any reference signs in the appended claims shall not be construed so as to limit their scope.