Conductive bridge semiconductor component and manufacturing method therefor

Abstract

The present disclosure provides a conductive bridge semiconductor device and a method of manufacturing the same. The conductive bridge semiconductor device includes a lower electrode, a resistive switching functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with certain holes through which active conductive ions pass. Based on this structure, the precise designing of the holes on the barrier layer facilitates the modulation of the quantity, size and density of the conduction paths in the conductive bridge semiconductor device, which enables that the conductive bridge semiconductor device can be modulated to be a nonvolatile conductive bridge resistive random access memory or a volatile conductive bridge selector. Based on the above method, ultra-low power nonvolatile conductive bridge memory and high driving-current volatile conductive bridge selector with controllable polarity are completed.

Claims

1. A conductive bridge semiconductor device, comprising a lower electrode, a resistive switching functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with certain holes through which active conductive ions pass, and wherein the ion barrier layer is directly connected to the active upper electrode.

2. The conductive bridge semiconductor device according to claim 1, wherein the conductive bridge semiconductor device is a conductive bridge resistive random access memory, the number of holes in the ion barrier layer is one, and a radial size of the hole is between 5 nm and 200 nm.

3. The conductive bridge semiconductor device according to claim 2, wherein the hole is located at a central position of the ion barrier layer.

4. The conductive bridge semiconductor device according to claim 2, wherein the ion barrier layer is made of at least one of the following materials: graphene, MoS.sub.2, BN, Ti, TiW, Ta, TaSiN, TiN, TaN, CuSiN and the like, and the radial size of the hole is between 5 nm and 100 nm.

5. The conductive bridge semiconductor device according to claim 1, wherein the conductive bridge semiconductor device is a conductive bridge selector, the number of holes in the ion barrier layer is greater than one, and the radial size of the hole is atomic scale and less than 5 nm.

6. The conductive bridge semiconductor device according to claim 5, wherein the holes are randomly distributed in the ion barrier layer with an areal density between 10.sup.7/cm.sup.2 and 10.sup.14/cm.sup.2.

7. The conductive bridge semiconductor device according to claim 6, wherein the ion barrier layer is made of at least one of the following materials: graphene, MoS.sub.2, BN, Ti, TiW, Ta, TaSiN, TiN, TaN, CuSiN and the like, and the areal density of the holes is among 10.sup.7/cm.sup.2˜10.sup.14/cm.sup.2.

8. The conductive bridge semiconductor device according to claim 6, wherein an increase of the areal density of the holes on the ion barrier layer results in a unipolar to bipolar transition of the device.

9. The conductive bridge semiconductor device according to claim 1, wherein a shape of each of the holes is rectangular, elliptical, triangular, hexagonal, or irregular figure.

10. The conductive bridge semiconductor device according to claim 1, wherein the lower electrode is a layered structure prepared by one or more of following materials: TaN, TiN, W, Al, Ru, Ti, and Pt, and has a thickness between 10 nm and 200 nm; the resistive switching functional layer is a layered structure prepared by one or more of following materials: TaO.sub.x, MgO, HfO.sub.2, Al.sub.2O.sub.3, TiO.sub.2, SiO.sub.2 and ZrO.sub.2, and has a thickness between 3 nm and 100 nm; the ion barrier layer is made of at least one of the following materials: graphene, MoS.sub.2, BN, Ti, TiW, Ta, TaSiN, TiN, TaN, CuSiN and the like, and has a thickness less than 10 nm; the active upper electrode comprises a single-element electrode including Ag, Cu or Ni, or an alloy electrode including at least one of Ag, Cu or Ni, and has a thickness between 10 nm and 200 nm.

11. A method of manufacturing the conductive bridge semiconductor device according to claim 1, comprising: forming the lower electrode, the resistive switching functional layer and the ion barrier layer in sequence; forming the holes in the ion barrier layer; and preparing the active upper electrode over the ion barrier layer having the holes.

12. The method according to claim 11, wherein the holes are formed in the ion barrier layer by using optical exposure combined with focused ion beam etching.

13. The method according to claim 11, wherein when the number of holes in the ion barrier layer is one, the conductive bridge device is a memory; when the number of holes in the ion barrier layer is larger than one, the conductive bridge device is a selector, the holes are randomly distributed in the ion barrier layer, and an areal density of the holes is between 10.sup.7/cm.sup.2 and 10.sup.14/cm.sup.2.

14. The method according to claim 13, wherein high energy ions for bombardment are obtained by an ion implanter or a particle accelerator, with an energy between 2 KeV and 200 KeV, an incident angle between 80° and 100°, and a dose greater than 10.sup.5 ion/cm.sup.2.

15. The method according to claim 13, wherein a dose of high energy ions for bombardment is between 10.sup.12 ion/cm2 and 10.sup.14 ion/cm2.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A is a schematic view showing the structure and conductive path regulation of a conductive bridge resistive random access memory with a single hole in an ion barrier layer according to a first embodiment of the present disclosure.

(2) FIG. 1B is a schematic diagram of the single hole in the ion barrier layer of the conductive bridge resistive random access memory shown in FIG. 1A.

(3) FIG. 2 is a flow chart of manufacturing the conductive bridge resistive random access memory of FIG. 1A in accordance with an embodiment of the present disclosure.

(4) FIG. 3 and FIG. 4 are respectively a characteristic I-V curve, at 1 μA, of a conventional Cu/HfO.sub.2/Pt device and a Cu/single-hole graphene/HfO.sub.2/Pt device manufactured according to the first embodiment of the present disclosure.

(5) FIG. 5A is a schematic diagram showing the structure and conductive path regulation of a conductive bridge selector having an ion barrier layer with an array of holes thereon according to a second embodiment of the present disclosure.

(6) FIG. 5B is a schematic diagram of an array of holes in the ion barrier layer of the conductive bridge selector shown in FIG. 5A.

(7) FIG. 6 is Raman spectroscopy diagrams of unprocessed graphene and graphene being bombarded by ions at a certain condition.

(8) FIG. 7 and FIG. 8 respectively show a characteristic I-V curve, at the maximum volatile current limit of 100 μA, of an Ag/porous graphene/SiO.sub.2/Pt device when multiple holes are formed in the ion barrier layer with the implantation dose of D1, D2.

(9) FIG. 9 is a characteristic I-V curve, at a current limit of 100 μA, of an Ag/porous graphene/SiO.sub.2/Pt device when multiple holes are formed in the ion barrier layer with the implantation dose being increased to D3.

(10) FIG. 10 is a characteristic I-V curve, at a maximum volatile current limit of 500 μA, of the Ag/porous graphene/SiO.sub.2/Pt device when multiple holes are formed in the ion barrier layer with the implantation dose being increased to D3.

(11) FIG. 11 is a characteristic I-V curve obtained by testing an Ag/porous graphene/SiO.sub.2/Pt selector device connected in series with a Cu/HfO.sub.2/Pt memory device through a peripheral circuit.

DESCRIPTION OF MAIN COMPONENT SYMBOLS IN THE EMBODIMENTS OF THE PRESENT DISCLOSURE IN FIGURES

(12) 10—lower electrode;

(13) 20—resistive switching functional layer;

(14) 40—active upper electrode;

(15) 30—ion barrier layer with a single hole; 31—single hole;

(16) 30′—ion barrier layer with an array of holes; 31′, 32′, 33′—holes;

(17) CF—single conductive path; CF.sub.1, CF.sub.2, CF.sub.3—multiple conductive paths.

DETAILED DESCRIPTION

(18) The key to the implementation of the low-power conductive bridge resistive random access memory and the high-current conductive bridge selector function is to regulate the retention characteristics of the conductive bridge. Therefore, it is important to optimize the performance of the resistive random access memory and the selector based on the conductive bridge by regulating the retention characteristics of the conductive paths.

(19) The disclosure introduces an ion barrier layer containing hole(s) on the basis of the active upper electrode/resistive switching functional layer/lower electrode structure to form a structure including an active upper electrode/ion barrier layer with hole(s)/resistive switching functional layer/lower electrode, and enables precise regulation of the conductive path(s) of the conductive bridge-based memory and the selector by regulating the quantity, size and density of the holes in the ion barrier layer.

(20) The present disclosure will be further described in detail below in combination of the specific embodiments of the disclosure, with reference to the drawings, to make the purpose, technical solutions and advantages of the disclosure more apparent.

(21) In a first exemplary embodiment of the present disclosure, a conductive bridge resistive random access memory is provided. FIG. 1A is a schematic view showing the structure and conductive path regulation of a conductive bridge resistive random access memory with a single hole in an ion barrier layer according to a first embodiment of the present disclosure. FIG. 1B is a schematic diagram of the single hole in the ion barrier layer of the conductive bridge resistive random access memory shown in FIG. 1A. As shown in FIG. 1A and FIG. 1B, the conductive bridge resistive random access memory includes sequentially a lower electrode 10, a resistive switching functional layer 20, an ion barrier layer 30 and an active upper electrode 40 from bottom to top. Wherein, the ion barrier layer is provided with a single hole 31 through which the active conductive ions pass.

(22) The respective portions of the conductive bridge resistive random access memory of the present embodiment are described in detail below.

(23) The lower electrode 10 may be prepared using one or more of the following materials, TaN, TiN, W, Al, Ru, Ti, and Pt. The thickness of the lower electrode 10 is between 10 nm and 200 nm.

(24) The resistive switching functional layer 20 is a layered structure prepared by one or more of the following materials: TaO.sub.x, MgO, HfO.sub.2, Al.sub.2O.sub.3, TiO.sub.2, SiO.sub.2 and ZrO.sub.2. The thickness of the resistive switching functional layer 30 is between 3 nm and 100 nm.

(25) The ion barrier layer 30 is made of at least one of the following materials: graphene, MoS.sub.2, BN, Ti TiW, Ta, TaSiN, TiN, TaN, CuSiN and the like. The thickness of the ion barrier layer 30 is less than 10 nm.

(26) The active upper electrode 40 may utilize a single-element electrode such as Ag, Cu, Ni or an alloy electrode containing at least one of the listed elements. The thickness of the active upper electrode 40 is between 10 nm and 200 nm.

(27) It will be apparent to those skilled in the art that the active upper electrode is not limited to the species listed above, and other electrodes capable of generating active conductive ions may be utilized. Also, the lower electrode is not limited to the species listed above, and electrodes made of other conductive materials may be utilized. Similarly, the resistive switching functional layer can be prepared using other materials having resistive switching properties. Also, the ion barrier layer is not limited to the species listed above, and it is possible to use a structurally dense film made of other materials.

(28) In this embodiment, there is only one hole 31 in the ion barrier layer 30. The hole 31 is a nanometer-scale (5 nm to 200 nm) hole. For the conductive bridge resistive random access memory shown in FIG. 1A, the ion barrier layer with a single hole can facilitate the concentrated distribution of the conductive paths to form a single conduction path (Conduction filament, shortly regarded as CF), which enhances its resistive state retention characteristics, especially improves the resistive state retention characteristic of the conductive bridge resistive random access memory at a low current limit. This is beneficial to achieve stable and low power consumption operation of the device.

(29) The shape of the hole in the ion barrier layer may be various, such as, a rectangle, a square, a circle, an ellipse, a triangle, a hexagon, and the like, and the radial size of the hole is between 5 nm and 100 nm. Preferably, the holes are preferably circular in view of the uniformity of current transport in various directions.

(30) In this embodiment, a single hole in the ion barrier layer is preferably located at the center of the ion barrier layer, as shown in FIG. 1A. In this case, the single conduction path CF is positioned at the center of the ion barrier layer, which is more advantageous for device design and processing than positioned at the periphery.

(31) FIG. 2 is a flow chart of manufacturing the conductive bridge resistive random access memory of FIG. 1A in accordance with an embodiment of the present disclosure. Referring to FIG. 1A and FIG. 2, a method of manufacturing a conductive bridge resistive random access memory having a single hole in an ion barrier layer includes:

(32) at Step S202, forming a lower electrode 10, a resistive switching functional layer 20 and an ion barrier layer 30 in sequence;

(33) At Step S204, forming a single hole in the ion barrier layer 30;

(34) The method for forming a single hole in the ion barrier layer 30 at this step includes:

(35) at Sub-step S204a, coating a photoresist on the ion barrier layer;

(36) at Sub-step S204b, by using electron beam or nanoimprint lithography technology, accurately exposing a single hole of different diameters on the nanometer scale to form a photoresist pattern;

(37) at Sub-step S204c, directly positioning and etching the ion barrier layer with focused ion beam technology by using the photoresist as an ion barrier layer mask layer, etching the unmasked ion barrier layer in the hole, thereby forming a single hole in the ion barrier layer;

(38) at Sub-step S204d, removing the photoresist above the ion barrier layer to obtain an ion barrier layer having a single hole, and step S204 is completed.

(39) at Step S206, preparing the active upper electrode 40 over the ion barrier layer having a single hole, and thus, the manufacture of the conductive bridge resistive random access memory having a single hole in the ion barrier layer as shown in FIG. 1A is completed.

(40) In order to highlight the effect of the ion barrier layer with a single hole on the performance of the conductive bridge resistive random access memory, performance tests were performed on a conventional resistive random access memory and a conductive bridge resistive random access memory manufactured in accordance with an embodiment of the present disclosure.

(41) FIG. 3 and FIG. 4 are respectively a characteristic I-V curve, at 1 μA, of a conventional Cu/HfO.sub.2/Pt device and a Cu/single-hole graphene/HfO.sub.2/Pt device manufactured according to the first embodiment of the present disclosure. In the Cu/single-hole graphene/HfO.sub.2/Pt device, the single hole diameter of the graphene is between 5 nm and 100 nm.

(42) It can be seen from FIG. 3 and FIG. 4 that the Cu/HfO.sub.2/Pt device without graphene barrier layer exhibits volatile characteristics at a current limit of 1 μA, while Cu/single hole graphene/HfO.sub.2/Pt device exhibits non-volatile characteristics at this current limit.

(43) In another exemplary embodiment of the present disclosure, a conductive bridge selector is also provided. FIG. 5A is a schematic diagram showing the structure and conduction path regulation of a conductive bridge selector having an array of holes in an ion barrier layer according to an embodiment of the present disclosure. FIG. 5B is a schematic diagram of an array of holes in the ion barrier layer of the conductive bridge selector shown in FIG. 5A. As shown in FIG. 5A and FIG. 5B, the difference between this embodiment and the previous embodiment is that the ion barrier layer 30′ has a plurality of holes (31′, 32′, 33′, etc.) of atomic scale (less than 5 nm), thus forming an array of holes.

(44) As shown in FIG. 5A, for the ion barrier layer with the formed hole array, the conduction path can be discretely distributed to form a plurality of conduction paths (CF.sub.1, CF.sub.2, CF.sub.3, etc.), thereby greatly weakening its retention characteristics, increasing the maximum current that the conductive bridge selector can provide, and improving its driving ability and selection ratio.

(45) Preferably, if the holes in the ion barrier layer 20 are porous, the multiple holes follow a random distribution in the ion barrier layer with an areal density between 10.sup.7/cm.sup.2 and 10.sup.14/cm.sup.2. This setting is mainly to avoid excessive concentration of conductive paths and improve the response speed of the selector. It is verified by experiments that when the areal density of the graphene holes is at 10.sup.10/cm.sup.2 magnitude, the response speed of the device is faster, and the switching speed is within 1 μs.

(46) The method of manufacturing the conductive bridge selector having a plurality of holes in the ion barrier layer is similar to the method of manufacturing the conductive bridge resistive random access memory having a single hole in the ion barrier layer shown in FIG. 2A, and the difference is that in the method of manufacturing the multiple holes in the ion barrier layer, and the following two specific methods of manufacturing the multiple holes are provided:

(47) (1) forming an array of a plurality of holes in the ion barrier layer by using a lithographic exposure plus ion beam etching method similar to the sub-steps S204a to S204d;

(48) (2) forming a porous ion barrier layer having a regulatable diameter and density by high-energy ions accelerated by an ion implanter or a particle accelerator directly bombarding the ion barrier layer, and by controlling the bombardment energy and dose. Within a certain range, the aperture size of the hole is mainly determined by the energy of the bombarding ions and the angle of incidence, and the density of the holes is mainly determined by the dose of the bombarding ions.

(49) Preferably, during ion bombardment, the energy of the bombarding ions is between 2 KeV and 200 KeV, the incident angle is between 80° and 100°, and the dose is greater than 10.sup.5 ion/cm.sup.2.

(50) The aperture of the hole formed by the ion bombardment method is at the atomic scale, and this type of graphene defect can be characterized by testing Raman spectroscopy.

(51) FIG. 6 is Raman spectroscopy diagrams of unprocessed graphene and graphene being bombarded by ions at a certain condition. In FIG. 6, the G peak is a characteristic peak of the C sp.sup.2 structure, reflecting the symmetry and the degree of crystallization, and the 2D peak is a two-phonon inelastic scattering peak. The D peak, the D′ peak and the D+D′ peak are Raman peaks associated with graphene defects. It can be seen from FIGS. 6(a) and (b) that after the particle bombardment, the relative ratio between the peaks changes greatly, and the intensity ratio I.sub.D/I.sub.G of the D peak to the G peak can be used to qualitatively measure the average distance L.sub.D of defects and the density σ of the defects. The relationship is as follows: I.sub.D/I.sub.G∝1/L.sup.2.sub.D∝σ. The porous ion barrier layer is mainly used to disperse the conduction paths, weaken its retention characteristics, increase the maximum current that the conductive bridge selector can provide, and increase the selection ratio.

(52) To highlight the effect of the porous ion barrier layer on the performance of the conductive bridge selector, an Ag/porous graphene/SiO.sub.2/Pt device is manufactured. An ion implanter is used with Si as the bombarding ion source, an implantation energy of 10 KeV and implantation doses of D1, D2, and D3 (D1<D2<D3), where D1=10.sup.12 ion/cm.sup.2; D2=5×10.sup.12 ion/cm.sup.2; D3=10.sup.13 ion/cm.sup.2, thereby obtaining the Ag/porous graphene/SiO.sub.2/Pt devices with three different hole densities of graphene.

(53) FIG. 7 and FIG. 8 show the characteristic I-V curves, at the maximum volatile current limit of 100 μA, of Ag/porous graphene/SiO.sub.2/Pt devices with an implantation dose of D1, D2. It can be seen that the Ag/porous graphene/SiO.sub.2/Pt devices with the two doses exhibit unipolar characteristics and can therefore be used as unipolar conductive bridge selectors.

(54) FIG. 9 is a characteristic I-V curve, at a current limit of 100 μA, of an Ag/porous graphene/SiO.sub.2/Pt device when the implantation dose is increased to D3. As shown in FIG. 9, the Ag/porous graphene/SiO.sub.2/Pt device transits from unipolar to bipolar as the implantation dose is increased to D3. As the implantation dose increases, more active metal ions enter the resistive switching functional layer to form a conduction path and accumulate at the lower electrode, which also results in a unipolar to bipolar transition.

(55) FIG. 10 is a characteristic I-V curve, at a maximum volatile current limit of 500 μA, of the Ag/porous graphene/SiO.sub.2/Pt device when the implantation dose is increased to D3. It can be seen that the Ag/porous graphene/SiO.sub.2/Pt device still maintains the bidirectional volatile property at a higher current limit of 500 μA.

(56) It can be seen that, in the conductive bridge selector shown in FIG. 5B, the porous ion barrier layer can indeed disperse the conduction path, weaken its retention characteristics, increase the maximum current that the conductive bridge selector can provide, and increase the selection ratio. The Ag/porous graphite/SiO.sub.2/Pt device reaches a maximum volatile current limit of 500 μA and the selection ratio of 5×10.sup.8 at the dose of D3.

(57) Further, in order to test the effect of the conductive bridge selector of the Ag/porous graphene/SiO.sub.2/Pt in the present embodiment, the Ag/porous graphene/SiO.sub.2/Pt device is connected in series with the Cu/HfO.sub.2/Pt device through a peripheral circuit.

(58) FIG. 11 is a characteristic I-V curve obtained by testing an Ag/porous graphene/SiO.sub.2/Pt device connected in series with a Cu/HfO.sub.2/Pt device through a peripheral circuit. The characteristic I-V curve shows that the selector of the Ag/porous graphene/SiO.sub.2/Pt has a good selection effect, and the selection ratio reaches 10.sup.8.

(59) For the purpose of brief description, any of the technical features of the above-described first embodiment that can be used for the same application will be incorporated herein, and the same description will not be repeated.

(60) So far, the conductive bridge selector in the second embodiment of the present disclosure has been described.

(61) It will be apparent to those skilled in the art that in addition to the conductive bridge resistive random access memory and the conductive bridge selector, other semiconductor devices employing the conductive bridge principle are still applicable to the present disclosure and will not be described herein.

(62) It should be noted that the implementations that are not shown or described in the drawings or the text of the specification are all known to those of ordinary skill in the art and are not described in detail. In addition, the above definitions of the various elements and methods are not limited to the specific structures, shapes, dimensions or manners mentioned in the embodiments, and those skilled in the art can simply modify or replace them, for example:

(63) (1) The lower electrode may also be in the form of a conductive oxide such as ITO;

(64) (2) The resistive switching functional layer can be replaced by a novel two-dimensional material such as BN, MoS.sub.x, graphene oxide or the like.

(65) Heretofore, the embodiments of the present disclosure have been described in detail in conjunction with the accompanying drawings. Based on the above description, those skilled in the art should have a clear understanding of the conductive bridge semiconductor device of the present disclosure and the method of manufacturing the same.

(66) In summary, the present disclosure provides a conductive bridge semiconductor device with a structure of an active upper electrode/hole-containing ion barrier layer/resistive switching functional layer/lower electrode, by regulating the diameter, number and density of holes in the ion barrier layer, regulation of the size and number of conduction paths of the conductive bridge-based memory and selector can be achieved as follows:

(67) (1) forming a single nanometer-scale hole in the ion barrier layer can facilitate the concentrated distribution of the conduction paths, improve the resistance state retention characteristic, and realize the non-volatile resistive switching characteristic under a small operating current, thereby effectively reducing the power consumption of the conductive bridge resistive random access memory;

(68) (2) forming a plurality of atomic-scale holes in the ion barrier layer can facilitate the discrete distribution of the conduction paths, reduce the retention characteristics of the conduction paths, and realize the volatile resistive switching characteristics under a large operating current, thereby improving the drive current and selection ratio of the conductive bridge selector.

(69) The conductive bridge semiconductor device and the method of manufacturing the same in the present disclosure have the advantages of high performance, easy integration, low cost, and the like, and have good application prospects.

(70) It should also be noted that an example of parameters containing specific values may be provided herein, but these parameters need not be exactly equal to the corresponding values, but may approximate the corresponding values within acceptable error tolerances or design constraints. The directional terms mentioned in the embodiments, such as “upper”, “lower”, “front”, “back”, “left”, “right”, etc., are merely referring to the directions of the drawings, and are not intended to limit the scope of the disclosure. In addition, the order of the above steps is not limited to the above, and may be varied or rearranged depending on the desired design, unless specifically described or necessarily occurring in sequence. The above embodiments may be used in combination with each other or with other embodiments based on design and reliability considerations, that is, the technical features in different embodiments may be freely combined to form more embodiments.

(71) It should be noted that the same elements are denoted by the same or similar reference numerals throughout the drawings. In the following description, some specific embodiments are for illustrative purposes and are not to be construed as limiting the disclosure, and may be only an example of the present embodiment. Conventional structures or configurations will be omitted when it may cause confusion to the understanding of the present disclosure. It should be noted that the shapes and sizes of the various components in the drawings do not reflect the true size and proportions, but merely illustrate the contents of the embodiments of the present disclosure.

(72) The purpose, technical solutions and advantageous effects of the disclosure have been described in detail in the above specific embodiments. It is to be understood that those are only specific embodiments of the present disclosure but not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and scope of the present disclosure are intended to be included within the scope of the present disclosure.