Silicon carbide semiconductor device integrating clamper circuit for clamping voltage

Abstract

The present invention provides a silicon carbide (SiC) semiconductor device integrating a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bidirectional voltage clamping circuit. An object of protecting a device is achieved by using the simple structure above, effectively preventing device damage that may be caused by a positive overvoltage and a negative overvoltage between a gate and a source.

Claims

1. A silicon carbide (SiC) semiconductor device, integrating a damper circuit for clamping voltage, comprising: a SiC substrate, comprising a first surface and a second surface opposite to the first surface; an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET), comprising a SiC n-type drift layer, a gate, a source and a drain, wherein the SiC n-type drift layer, the gate and the source are disposed adjacent to the first surface and the drain is disposed adjacent to the second surface, the SiC n-type drift layer is provided with a plurality of p-type wells arranged at intervals, at least one p-type region disposed at the p-type well, at least one n-type region disposed at the p-type well, an insulator disposed on the SiC n-type drift layer, and a gate electrode connected to the gate; and a bidirectional voltage clamp, disposed on the first surface, and comprising a first terminal connected to the gate and a second terminal connected to the source.

2. The SiC semiconductor device of claim 1, wherein the bidirectional voltage clamp comprises at least one p-floating region spaced from the p-type well by a first distance, the p-floating region comprises a first n-type region and a second n-type region, the first n-type region and the second n-type region are separated from each other by a spacer region, the first terminal is connected to the gate electrode through an ohmic contact on the first n-type region, and the second terminal is connected to the source through an ohmic contact on the second n-type region.

3. The SiC semiconductor device of claim 2, wherein between the first terminal and the spacer region is a second distance, between the second terminal and the spacer region is a third distance, and the second distance is greater than the third distance.

4. The SiC semiconductor device of claim 2, wherein the p-floating region comprises a retrograde doping profile, in which the p-floating region comprises a bottom portion and a top portion comprising a doping concentration lower than that of the bottom portion.

5. The SiC semiconductor device of claim 1, wherein the MOSFET is a planar MOSFET.

6. The SiC semiconductor device of claim 1, wherein the MOSFET is a trench MOSFET.

7. The SiC semiconductor device of claim 1, wherein the bidirectional voltage clamp suppresses a positive overvoltage and a negative overvoltage applied between the gate and the source.

8. The SiC semiconductor device of claim 7, wherein absolute values of the positive overvoltage and the negative overvoltage are smaller than absolute values of positive and negative gate-to-source breakdown voltages of the MOSFET.

9. The SiC semiconductor device of claim 7, wherein an absolute value of the positive overvoltage is greater than an absolute value of the negative overvoltage.

10. The SiC semiconductor device of claim 1, wherein the bidirectional voltage clamp comprises a plurality of p-floating regions connected in parallel.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic diagram of transfer characteristics of drain current (I.sub.D) versus gate voltage (Vgs) of a conventional Si MOSFET;

(2) FIG. 2 is a schematic diagram of transfer characteristics of drain current (I.sub.D) versus gate voltage (Vgs) of a conventional SiC MOSFET;

(3) FIG. 3 is a schematic diagram of the difference in margins between suggested operating voltages and breakdown voltages of a gate oxide layer of a Si MOSEFT and a SiC MOSFET;

(4) FIG. 4 is a top schematic diagram of a SiC semiconductor device integrating a clamper circuit for clamping voltage according to an embodiment of the present invention;

(5) FIG. 5 is a sectional schematic diagram of FIG. 4 along A-A;

(6) FIG. 6 is a partial top schematic diagram of FIG. 5;

(7) FIG. 7 depicts curves of gate leakage current (Igs) versus gate/source voltage (Vgs) of a SiC semiconductor device integrating a clamper circuit for clamping voltage according to an embodiment of the present invention and a conventional SiC semiconductor device without a damper circuit for clamping voltage; and

(8) FIG. 8 depicts curves of gate leakage current (Igs) versus gate voltage (Vg) of a SiC semiconductor device integrating a clamper circuit for clamping voltage according to an embodiment of the present invention under different temperatures.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(9) Details and technical contents of the present invention are given with the accompanying drawings below.

(10) The present invention provides a silicon carbide (SiC) semiconductor device integrating a clamper circuit for clamping voltage. Referring to FIG. 4 and FIG. 5, FIG. 4 shows a schematic diagram of a SiC semiconductor device integrating a clamper circuit for clamping voltage according to an embodiment of the present invention, and FIG. 5 shows a sectional schematic diagram of FIG. 4 along A-A. A SiC semiconductor device 1 integrating a clamper circuit for clamping voltage according to an embodiment of the present invention includes a SiC substrate 10, a metal-oxide-semiconductor field-effect transistor (MOSFET) 20 and a bidirectional voltage clamp 30. The MOSFET 20 can be a planar MOSFET or a trench MOSFET.

(11) According to an embodiment of the present invention, the MOSFET 20 includes a SiC n-type drift layer 21, a gate 22, a source 23 and a drain 24. The SiC substrate 10 includes a first surface 11 and a second surface 12 opposite to each other. The SiC n-type drift layer 21, the gate 22 and the source 23 are disposed adjacent to the first surface 11, and the drain 24 is disposed adjacent to the second surface 12. The SiC n-type drift layer 21 is disposed on the first surface 11, and can have a doping concentration ranging from 1E14 cm.sup.−3 to 1E17 cm.sup.−3. The gate 22 includes a gate electrode 221 disposed on the SiC n-type drift layer 21.

(12) The MOSFET 20 further includes a plurality of p-type wells 25 and an insulator 26. The p-type wells 25 are arranged at intervals from one another in the SiC n-type drift layer 21, a part of the p-type wells 25 include at least one p-type region 251 and at least one n-type region 252, as shown by the p-type wells 25 on the right of FIG. 5, and a part of the p-type wells 25 do not include the p-type region 251 or the n-type region 252, as shown by the p-type wells 25 on the left of FIG. 5. In this embodiment, the doping concentration of the p-type regions 251 can be in a range from 1E18 cm.sup.−3 to 1E20 cm.sup.−3, and the doping concentration of the n-type region 252 can be in a range from 1E19 cm.sup.−3 to 1E20 cm.sup.−3. The SiC n-type drift layer 21 or the n-type region 252 can be individually and respectively doped by phosphorous or nitrogen, and the p-type well 25 and/or the p-type region 251 can be doped by aluminum or boron. The insulator 26 is disposed on the SiC n-type drift layer 21, and can be formed by thermal oxidation or be formed from a material having a high dielectric constant (e.g., aluminum oxide, Al.sub.2O.sub.3) through chemical vapor deposition or atomic layer deposition, and is processed by nitridation by post oxide annealing with a nitrogen-containing gas (e.g., N.sub.2, NO, or N.sub.2O) at a temperature of higher than 1000° C. At least a part of the bottom end of the source 23 forms an ohmic contact 27 to electrically connect to a part of the n-type region 252 and a part or all of the p-type region 251.

(13) Referring to FIG. 6 showing a partial top schematic diagram of FIG. 5, the bidirectional voltage clamp 30 is formed in the SiC n-type drift layer 21, and the bidirectional voltage clamp 30 includes a first terminal 31, a second terminal 32 and a p-floating region 33. The p-floating region 33 is spaced from the p-type well 25 by a first distance D1, and the p-floating region 33 can be formed by doping aluminum or boron. Further, the p-floating region 33 includes at least one first n-type region 331 formed by doping phosphorous or nitrogen and at least one second n-type region 332. The first n-type region 331 and the second n-type region 332 are separated from each other by a spacer region S. Between the first terminal 31 and the spacer region S is a second distance D2, and between the second terminal 32 and the spacer region S is a third distance D3, wherein the second distance D2 is greater than the third distance D3. It is seen from FIG. 5 that, in this embodiment, the width of the spacer region S along the edge of the second n-type region 332 is an equal distance. In other embodiments, the width of the spacer region S along the edge of the second n-type region 332 can be an unequal distance. In the p-floating region 33, the first terminal 31 is connected to the gate electrode 221 through the ohmic contact 27 on the first n-type region 331, and the second terminal 32 is connected to the source 23 through the ohmic contact 27 on the second n-type region 332. Accordingly, a positive overvoltage and a negative overvoltage between the gate 22 and the source 23 can be suppressed by the bidirectional voltage clamp 30. Further, in this embodiment, an absolute value of the positive overvoltage is greater than an absolute value of the negative overvoltage.

(14) In addition, the absolute values of the positive overvoltage and the negative overvoltage are both smaller than absolute values of positive and negative gate-to-source breakdown voltages of the MOSFET 20.

(15) The p-floating region 33 can include a retrograde doping profile, in which a doping concentration at a top portion is lower than a doping concentration at a bottom portion. Viewing from a vertical direction, the bidirectional voltage clamp 30 can be regarded as a parasitic bipolar junction transistor (BJT), and by adjusting the concentration distribution of the p-floating region 33, the open base breakdown voltage of the parasitic BJT can be adjusted.

(16) In another embodiment of the present invention, the bidirectional voltage clamp 30 can further include a plurality of p-floating regions 33 connected in parallel. Because the amount of energy that can be absorbed by one single bidirectional voltage clamp 30 is limited, the number or area of the p-floating regions 33 can be increased to boost the tolerance against electrostatic discharged (ESD).

(17) Referring to FIG. 7, by comparing a curve (in a solid line) of gate leakage current (Igs) versus gate/source voltage (Vgs) of the SiC semiconductor device integrating a clamper circuit for clamping voltage according to an embodiment of the present invention with that (in a dotted line) of a conventional SiC semiconductor device without a damper circuit for clamping voltage, the results show that, within a suggested gate/source voltage (Vgs) range (i.e., the gate/source voltage (Vgs) is in a range from −10 V to 20 V), the leakage current (Igs) of the SiC semiconductor device of the embodiment is extremely low, at approximately several nA; however, under similar conditions, the leakage current (Igs) of a SiC semiconductor device integrating a polysilicon Zener diode can reach as high as several μA. It is apparent that the SiC semiconductor device of the present embodiment is capable of providing protection against both the positive overvoltage and negative overvoltage between the gate and the source.

(18) FIG. 8 shows curves of gate leakage current (Igs) versus gate voltage (Vg) of the SiC semiconductor device integrating a clamper circuit for clamping voltage according to an embodiment of the present invention under different temperatures. The results show that, under different temperatures between 30° C. and 175° C., the curve of gate leakage current (Igs) versus gate voltage (Vg) of the SiC semiconductor device according to the present embodiment is not drastically changed, indicating a lower sensitivity to temperature. Therefore, even under high temperatures, instability issues such as a decreased breakdown voltage and an increased leakage current possibly occurring in the SiC semiconductors disclosed by the U.S. Pat. Nos. 6,172,383 and 6,413,822 are eliminated.

(19) In conclusion, comparing with the prior art, for example, the U.S. Pat. No. 9,627,383, which provides protection for only a negative overvoltage between the gate and the source, the design of the present invention is capable of avoiding device damage caused by a positive overvoltage and a negative overvoltage between the gate and the source through the SiC semiconductor device integrating a MOSFET and a clamper circuit for clamping voltage of the present invention, further achieves the object of device protection.