ELECTRONIC POWER MODULE

Abstract

An electronic power module includes at least a semiconductor chip having at least one electronic power component and two metal layers between which the semiconductor chip is directly secured. At least a first of the two metal layers forms a redistribution layer having several distinct metal portions, each electrically connected to at least one electrical contact pad of the semiconductor chip, and/or at least one second of the two metal layers includes at least one first structured face arranged against the semiconductor chip and having at least one pad formed in a part of its thickness.

Claims

1-16. (canceled)

17. A power electronic module including: at least one semiconductor chip comprising at least one power electronic component; at least two metal layers between which the at least one semiconductor chip is directly secured, wherein at least a first of the at least two metal layers includes at least one first structured face disposed against the at least one semiconductor chip and comprising at least one pad formed in part of a thickness thereof.

18. The power electronic module according to claim 17, wherein at least a second of the at least two metal layers forms a redistribution layer comprising a plurality of distinct metal portions each electrically connected to at least one electrical contact pad of the at least one semiconductor chip.

19. The power electronic module according to claim 18, wherein the second of the at least two metal layers has a thickness greater than approximately 100 μm and/or includes copper.

20. The power electronic module according to claim 18, wherein the second of the at least two metal layers includes a central layer comprising at least a first metal and covered with another layer of at least a second metal different from the first metal and against which said at least one semiconductor chip is secured.

21. The power electronic module according to claim 18, wherein the first of the at least two metal layers includes a second face, opposite to a first face disposed against the at least one semiconductor chip, secured at least to one of the following elements: a second metallised substrate, a power contact, a decoupling capacitor, and an electronic control device.

22. The power electronic module according to claim 18, wherein the second of the at least two metal layers includes a first structured face disposed against the semiconductor chip and comprising pads formed in a part of a thickness thereof.

23. The power electronic module according to claim 17, further including a first metallised support to which the at least the first of the at least two metal layers is secured by means of a first layer of solder.

24. The power electronic module according to claim 23, wherein a second face, opposite to the first structured face, of the first of the at least two metal layers includes a rim laterally delimiting a space wherein the first layer of solder is disposed.

25. The power electronic module according to claim 17, wherein the at least one pad of the first structured face of the first of the at least two metal layers includes a cross section, in a plane passing through the first structured face, a form of which includes rounded corners or is substantially circular.

26. The power electronic module according to claim 17, wherein the first of the at least two metal layers at least one of: has a thickness greater than approximately 100 μm, and includes copper.

27. The power electronic module according to claim 17, wherein the first of the at least two metal layers includes a central layer comprising at least a first metal and covered with another layer of at least a second metal different from the first metal and against which the at least one semiconductor chip is secured.

28. The power electronic module according to claim 17, including at least one second semiconductor chip comprising at least one second power electronic component and disposed directly between said at least two metal layers.

29. A power electronic module including: at least one semiconductor chip comprising at least one power electronic component; and at least two metal layers between which said at least one semiconductor chip is directly secured, wherein at least a first of said at least two metal layers forms a redistribution layer comprising a plurality of distinct metal portions each electrically connected to at least one electrical contact pad of said at least one semiconductor chip.

30. The power electronic module according to claim 29, wherein the first of the at least two metal layers includes a central layer comprising at least a first metal and covered with another layer of at least a second metal different from the first metal and against which the at least one semiconductor chip is secured.

31. The power electronic module according to claim 29, wherein the first of the at least two metal layers includes a first structured face disposed against the semiconductor chip and comprising pads formed in a part of a thickness thereof.

32. A method for producing at least one power electronic module including at least the implementation of the following steps: producing, from at least a first of at least two metal layers, a redistribution layer comprising a plurality of distinct metal portions; structuring of at least a first face of at least a second of said at least two metal layers, forming at least one pad in a part of the thickness thereof; and securing, by direct bonding, at least one semiconductor chip comprising at least one power electronic component between said at least two metal layers, so that each of metal portions of the first of the at least two metal layers is electrically connected to at least one electrical contact pad of said at least one semiconductor chip and/or so that the first structured face of said at least one second of said at least two metal layers is disposed against said at least one semiconductor chip.

33. The method according to claim 32, wherein the securing, by direct bonding, of said at least one semiconductor chip between said at least two metal layers includes implementation of thermocompression of said at least two metal layers against said at least one semiconductor chip.

34. The method according to claim 33, wherein the securing, by direct bonding, of said at least one semiconductor chip between said at least two metal layers comprises securing, by direct bonding, of a first substrate forming a matrix of semiconductor chips between two second metal substrates intended each to form one of said at least two metal layers.

35. The method according to claim 32, further comprising securing, by means of a first layer of solder, the second of said at least two metal layers of the power electronic module to a first metallised support.

36. Method according to claim 32, further comprising, after the securing step, cutting the first and second substrates, forming a plurality of power electronic modules each including at least one of the semiconductor chips directly secured to said at least two metal layers.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The present invention will be understood better from reading the description of example embodiments given purely by way of indication and in no way limitatively, referring to the accompanying drawings, wherein:

[0055] FIG. 1 shows a power electronic module that is the object of the present invention, according to a first embodiment;

[0056] FIGS. 2A and 2B show an example embodiment of pads formed on the surface of one of the two metal layers of a power electronic module that is the object of the present invention;

[0057] FIG. 3 shows a power electronic module that is the object of the present invention, according to a second embodiment;

[0058] FIG. 4 shows an example embodiment of one of the two metal layers of the power electronic module that is the object of the present invention, according to a second embodiment;

[0059] FIG. 5 shows a power electronic module that is the object of the present invention, according to a third embodiment;

[0060] FIGS. 6 and 7 show two variant embodiments of the power electronic module that is the object of the present invention.

[0061] Identical, similar or equivalent parts of the various figures described below bear the same numerical references so as to facilitate passing from one figure to another.

[0062] The various parts shown in the figures are not necessarily shown to a uniform scale, in order to make the figures more legible.

[0063] The various possibilities (variants and embodiments) must be understood as not being mutually exclusive and may be combined with each other.

DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

[0064] Reference is made first of all to FIG. 1, which shows a power electronic module 100, or power electronic module, according to a first embodiment.

[0065] The module 100 includes a semiconductor chip 102 wherein one or more power electronic components are formed. This power electronic component or components correspond for example to diodes, transistors or thyristors. The chip 102 includes first and second main faces respectively referenced 104 and 106. The chip 102 also includes electrical contact pads present on the first main face 104 and/or on the second main face 106 (on both these main faces if the power electronic component or components each have a vertical structure). The electrical contact pads of the chip 102 are connected to active regions of the power electronic component or components of the chip 102. These electrical contact pads of the chip 102 include for example copper, AlCu or titanium or any other metal material.

[0066] The module 100 also includes first and second metal layers 108, 110 each directly secured to one of the first and second main faces 104, 106 of the chip 102, i.e. without any intermediate material for implementing the bonding step (in particular solder) interposed between the metal layers 108, 110 and the faces 104, 106 of the chip 102. The thickness of each of the metal layers 108, 110 is for example greater than approximately 100 μm, and for example equal to several hundreds of microns. The metal layers 108, 110 advantageously include copper.

[0067] At least one of the two metal layers 108, 110 forms a redistribution layer, that is to say which is structured so that it forms a plurality of distinct metal portions electrically connected to the electrical contact pads of the chip 102.

[0068] According to a first configuration, the electrical contact pads of the chip 102 may be disposed on only one of the two faces 104, 106. This is the case with the example embodiment shown in FIG. 1, where all the electrical contact pads of the chip 102 are disposed on the main face 104. In this case, only one of the two metal layers 108, 110 forms a redistribution layer connected to these electrical contact pads (the first layer 108 on the example embodiment shown in FIG. 1). According to a second configuration, the electrical contact pads of the chip 102 may be disposed on the two faces 104, 106. In this case, the two layers 108, 110 form redistribution layers connected to these electrical contact pads.

[0069] The metal layer or layers serving as redistribution layers may be structured to form distinct metal portions each connected to one or more of the electrical contact pads of the chip 102. On the example embodiment shown in FIG. 1, the layer 108, serving as a redistribution layer, is structured so as to form a plurality of distinct portions each connected to one or more electrical contact pads of the chip 102 distinct from the other pad or pads to which the other portions of the layer 108 are connected. On the example in FIG. 1, three distinct portions 109a, 109b and 109c of the layer 108 are shown. In order to form these portions 109 distinct from each other, the first metal layer 108 is structured, for example etched, over the entire thickness thereof. Trenches separating these various portions 109 pass through the entire thickness of the layer 108.

[0070] In addition, in the first embodiment described here, the face of each of the metal layers 108, 110 that is located on the same side as the chip 102 is also structured so as to form pads 112 in contact with the chip 102. These pads 112 are formed in a part of the thickness of the metal layers 108, 110.

[0071] FIG. 2A shows a first example embodiment of the pads 112. This figure shows a plan view of the second metal layer 110, the top face of this layer 110 being structured by forming pads in part of the thickness of the layer 110. On this example, each of the pads 112 comprises a cross section, in a plane passing through this top face of the layer 110, with a substantially circular shape. On this FIG. 2A, hatchings represent the surfaces of the pads in contact with the chip 102.

[0072] FIG. 2B shows another variant embodiment with a single solid pad 112 on the layer 110. There also, hatchings represent the surface of the pad 112 in contact with the chip 102. According to a variant embodiment, the pads 112 may have a cross section the form of which includes rounded corners with a radius of curvature that may vary, which makes it possible to optimise the mechanical stresses due to the corners.

[0073] The assembly formed by the chip 102 and the metal layers 108, 110 is transferred onto the front face of a metallised support 114 corresponding here to a DBC substrate formed by a dielectric central layer 116, comprising for example a ceramic, disposed between a top metal layer 118 and a bottom metal layer 120, for example comprising on copper. The securing between this assembly and the metallised support 114, and more precisely between the metal layer 110 and the top metal layer 118, is provided by a layer of solder 122.

[0074] Although not visible in FIG. 1, the metallised support 114 may be secured, at the rear face thereof and by means of another layer of solder, to a cooling assembly comprising for example a metal sole plate, or “spreader” according to English terminology, and a heat dissipater connected to each other by a thermal grease.

[0075] The power electronic module 100 according to a second embodiment is shown in FIG. 3.

[0076] In this second embodiment, the second metal layer 110 includes, at the rear face thereof (the one located on the same side as the metallised support 114) a rim 124 laterally delimiting a space 125 (visible in FIG. 4) wherein the layer of solder 122 is disposed. FIG. 4 shows in more detail the second metal layer 110. The rim 124 is covered with a dielectric material 128 for containing the solder of the layer 122 through its low wettability by the solder. This dielectric material 128 is for example an oxide or a varnish. In this configuration, the risk that the solder material may interfere with the correct functioning of the chip 102 after the second metal layer 110 is secured to the metallised support 114 is avoided.

[0077] Furthermore, in this second embodiment, a second metallised substrate 126 is secured to the rear face (the one located on the side opposite to the chip 102) of the first metal layer 108. This second metallised substrate 126 corresponds for example to a DBC substrate formed, like the first metallised substrate 114, from a dielectric central layer 128 disposed between two metal layers 130 and 132. The securing between the rear face of the first metal layer 108 and the metallised support 126, and more precisely between the metal layers 108 and 132, is provided by a layer of solder 134. In the example embodiment described here, the metal layer 108 (or more precisely one or more of the various metal portions formed by the layer 108) includes, at the rear face thereof, a rim 136 laterally delimiting a space wherein the layer of solder 134 is disposed, in a similar manner to the metal layer 110. In this example embodiment, the cooling of the electronic chip may be implemented in dual face by securing a cooling system (not visible in the figure) to the two metallised supports 114 and 126.

[0078] The power electronic module 100 according to a third embodiment is shown in FIG. 5.

[0079] Compared with the second embodiment previously described, the rear face of the first metal layer 108 is not secured to a second metallised substrate, but to lyre-shaped connectors 138, at some of the distinct portions 109 of the metal layer 108. The securing between the lyre-shaped connectors 138 and the rear faces of the portions 109 of the metal layer 108 is provided by the layer of solder 134, here separated into a plurality of distinct portions on the various portions of the metal layer 108 in order to ensure the securing of each of the lyre-shaped connectors 138.

[0080] According to another variant embodiment shown in FIG. 6, the rear face of the first metal layer 108 may serve as a support for a decoupling capacitor 140 electrically connected to the power electronic component or components of the chip 102 by means of the first metal layer 108.

[0081] According to another variant embodiment shown in FIG. 7, the rear face of the first metal layer 108 may serve as a support for a control circuit 142, or driver, electrically connected to the power electronic component or components of the chip 102 by means of the first metal layer 108. Such a control circuit 142 can for example serve to control the switching of a power transistor formed in the chip 102. On the example in FIG. 7, the portions 109a, 109b and 109c formed by the first metal layer 108 are connected respectively to the drain, to the gate and to the source of a power transistor formed in the chip 102, the control circuit 142 being disposed on the metal portion 109c connected to the source of the power transistor and electrically connected to the metal portion 109b that is connected to the gate of the power transistor in order to control the switching to the on or off state of the transistor.

[0082] In all the embodiments described here, the power electronic component or components of the semiconductor chip 102 may form at least one switching cell. The power electronic module 100 may in particular form a power electronic module comprising a plurality of semiconductor chips 102 forming a plurality of switching cells electrically connected to each other by the two metal layers 108, 110.

[0083] An example of a method for producing the power electronic module 100 is described below. In the example described here, the method is implemented so that a plurality of power electronic modules 100 are produced collectively.

[0084] Power electronic components are first of all produced from a first semiconductor substrate. The contact pads of these components are produced from copper.

[0085] A structuring of two metal substrates is next implemented. This structuring corresponds in particular to the production of perforations passing right through the substrate or substrates intended to form the redistribution layers of the modules 100, and the production of pads on one or both faces of one or both substrates, in a part of the thickness of this or these substrates. Preferably, these metal substrates include copper, which is a metal that is advantageous for both the electrical conductivity thereof and the thermal conductivity thereof. In a variant, one or both metal substrates may include a central layer comprising another metal (for example tungsten or molybdenum, optionally covered with a metal layer more adapted to the implementation of direct bonding with the semiconductor chips produced in the first substrate.

[0086] Such metal wafers may be produced by rolling, trimming, structuring by etching (optionally followed by polishing) and right-through etching in order to form the various distinct metal portions.

[0087] Direct bonding is next implemented in order to assemble the three substrates by direct bonding. The semiconductor substrate is disposed between the two metal substrates. When the roughness of the bonded surfaces is less than or equal to approximately 0.5 nm RMS, the direct bonding can be implemented at ambient temperature without applying any pressure between the bonded elements. When the roughness of the bonded surfaces is higher than this value, for example between approximately 0.5 nm RMS and 100 nm RMS, a thermocompression (pressure for example of a few MPa and temperature controlled for example at between [300-400]° C. during the bonding) may be implemented during the bonding.

[0088] The assembly obtained after this bonding is next completely passivated, for example by injecting a passivation material into the assembly.

[0089] The assembly produced is next cutted in order to produce the various individual power electronic modules 100.

[0090] In a variant, the passivation may be implemented after this cutting step, each module 100 being passivated individually.

[0091] The metal layers 108, 110 are next secured to the other elements provided: metallised support 114, 126, lyre-shaped connectors 138, etc.