Electric Circuit Arrangement to Control Current Generation

Abstract

In an embodiment an electric circuit arrangement includes a current generator circuit having a first output terminal and to generate an output current, a controller configured to generate control signals to control the current generator circuit, a random code generator configured to generate random codes and a counter configured to generate a count, wherein the current generator circuit comprises a plurality of output current paths and a plurality of controllable switching circuits, wherein each of the output current paths includes a respective electrical component to define a current in the respective output current path, wherein a respective one of the controllable switching circuits is coupled to a respective one of the output current paths to connect the respective electrical component to the first output terminal, wherein the random code generator is configured to provide a respective code derived from a respective one of the random codes, and wherein the controller is configured to use the respective derived code or the count depending on the derived code to generate a respective one of the control signals to control a respective one of the controllable switching circuits of the current generator circuit.

Claims

1.-15. (canceled)

16. An electric circuit arrangement comprising: a current generator circuit having a first output terminal, the current generator configured to generate an output current; a controller configured to generate control signals to control the current generator circuit; a random code generator configured to generate random codes; and a counter configured to generate a count, wherein the current generator circuit comprises a plurality of output current paths and a plurality of controllable switching circuits, wherein each of the output current paths includes a respective electrical component to define a current in the respective output current path, wherein a respective one of the controllable switching circuits is coupled to a respective one of the output current paths to connect the respective electrical component to the first output terminal, wherein the random code generator is configured to provide a respective code derived from a respective one of the random codes, and wherein the controller is configured to use the respective derived code or the count depending on the derived code to generate a respective one of the control signals to control a respective one of the controllable switching circuits of the current generator circuit.

17. The electric circuit arrangement of claim 16, wherein the current generator circuit has a second output terminal, and wherein the controller is configured to generate the control signals such that one of the output current paths is connected to the second output terminal and a remainder of the output current paths are connected to the first output terminal.

18. The electric circuit arrangement of claim 16, wherein the controller is configured to use the respective derived code to generate the control signals, when a decimal representation of the derived code is lower than a number of a remainder of the output current paths.

19. The electric circuit arrangement of claim 18, wherein the controller is configured to use the count to generate the control signals, when the decimal representation of the derived code is larger than a number of the remainder of the output current paths.

20. The electric circuit arrangement of claim 16, wherein the counter is configured to increase the count, when the count is used by the controller to generate the control signals.

21. The electric circuit arrangement of claim 16, wherein the counter is configured to increase the count between a start value and a final value, and wherein a number of counts between the start value and the final value corresponds to a number of output current paths of the current generator circuit.

22. The electric circuit arrangement of claim 16, wherein the random code generator comprises a linear feedback shift register.

23. The electric circuit arrangement of claim 22, wherein the linear feedback shift register comprises a shift register including a plurality a storage cells, wherein each of the storage cells is configured to store one bit of the respective random code, wherein the linear feedback shift register is configured to provide the respective derived code from storage cells to be evaluated, the storage cells to be evaluated being a portion of the plurality of storage cells, and wherein the linear feedback shift register is configured to provide the respective derived code depending on a respective storage state of the storage cells to be evaluated.

24. The electric circuit arrangement of claim 23, wherein the linear feedback shift register is configured such that the storage cells to be evaluated are provided with a number M which fulfills the condition 2.sup.M>N+1, and wherein N+1 is a number of the output current paths of the current generator circuit.

25. The electric circuit arrangement of claim 16, further comprising: a clock circuit configured to generate a clock signal between subsequent time steps, wherein the random code generator is clocked by the clock signal such that the respective one of the random codes and the respective one of the derived codes is generated in a respective one of the time steps, and wherein the controller is clocked by the clock signal such that the respective derived code or the count is used in the respective one of the time steps to generate the control signals.

26. The electric circuit arrangement of claim 16, wherein the current generator circuit comprises a current mirror circuit including a plurality of mirror transistors, wherein each of the output current paths includes a respective one of the mirror transistors, and wherein the current generator circuit is configured to connect the respective mirror transistor to the first output terminal by the respective controllable switching circuit.

27. The electric circuit arrangement of claim 26, wherein a respective one of the controllable switching circuits is coupled in series with a respective one of the mirror transistors.

28. A signal processing circuit comprising: the electric circuit arrangement of claim 16; and at least one of a bias current generator, a band gap reference circuit, a digital to analogue converter and an analogue to digital converter, wherein the electric circuit arrangement is included in at least one of the bias current generator, the band gap reference circuit, the digital to analogue converter and the analogue to digital converter.

29. A communication device comprising: the signal processing circuit according to claim 28; and a sensor circuit, wherein the signal processing circuit is included in the sensor circuit.

30. The communication device of claim 29, wherein the analogue to digital converter of the signal processing circuit is embodied as a sigma-delta analogue to digital converter, and wherein the sensor circuit is embodied as one of a temperature sensor circuit, a pressure sensor circuit, a humidity sensor circuit or a resistance measurement circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are included to provide a further understanding and are incorporated in and constitute a part of this specification. The drawings illustrate several embodiments of the electric circuit arrangement to control current generation, and together with the description serve to explain principles and the operation of the various embodiments.

[0018] FIG. 1 shows an embodiment of a current generator circuit being comprising as a current mirror to generate an output current by dynamic element matching;

[0019] FIG. 2 shows a block diagram of an electric circuit arrangement to control current generation by a current generator circuit using dynamic element matching;

[0020] FIG. 3 shows an embodiment of a random code generator being configured as a linear feedback shift register to generate random codes;

[0021] FIG. 4 shows a control algorithm to select a code to control controllable switching circuits of a current generator circuit using dynamic element matching;

[0022] FIG. 5 illustrates a table containing states of a random code generator, a counter and selected output to control a current generator circuit using dynamic element matching;

[0023] FIG. 6A shows an embodiment of a signal processing circuit comprising an electric circuit arrangement to control current generation; and

[0024] FIG. 6B shows an embodiment of a communication device comprising an electric circuit arrangement to control current generation.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0025] FIG. 1 illustrates an exemplified embodiment of a current generator circuit 100 comprising a current mirror. The current generator circuit comprises an input path P.sub.o including a transistor T.sub.o and a reference current source IS to generate a reference current IREF. The current generator circuit 100 further comprises a plurality of output current paths P.sub.1, . . . , P.sub.N+1. Each of the output current paths P.sub.1, . . . , P.sub.N+1 includes a respective electrical component T.sub.1, . . . , T.sub.N+1 to define a current in the respective output current path. Furthermore, the current generator circuit 100 comprises a plurality of controllable switching circuit SC.sub.1, . . . , SC.sub.N+1.

[0026] A respective one of the controllable switching circuits SC.sub.1, . . . , SC.sub.N+1 is coupled to a respective one of the output current paths P.sub.1, . . . , P.sub.N+1 to connect the respective electrical component T.sub.1, . . . , T.sub.N+1 to an output terminal O1 of the current generator circuit wo to generate an output current I1. Each of the controllable switching circuits SC.sub.1, . . . , SC.sub.N+1 comprises a pair of controllable switches respectively including a first controllable switch S1a, S2a, S3a, . . . , SN+1a and a respective second controllable switch S1b, S2b, S3b, . . . , SN+1b.

[0027] According to the embodiment of the current generator circuit wo shown in FIG. 1, the current mirror circuit includes a plurality of mirror transistors T.sub.1, . . . , T.sub.N+1. Each of the output current paths P.sub.1, . . . , P.sub.N+1 includes a respective one of the mirror transistors T.sub.1, . . . , T.sub.N+1. The current generator circuit wo is configured to connect the respective mirror transistor T.sub.1, . . . , T.sub.N+1 to the first output terminal O1 by the respective controllable switching circuit SC.sub.1, . . . , SC.sub.N+1.

[0028] Furthermore, the respective controllable switching circuit SC.sub.1, . . . , SC.sub.N+1 can be controlled such that one of the respective mirror transistors T.sub.1, . . . , T.sub.N+1 is connected to a second output terminal O2 of the current generator circuit wo. By way of example, the mirror transistor T.sub.1 of the current path P.sub.1 may be connected to the output terminal O2 by operating the controllable switch S1a in a closed or low resistive/conductive state and by operating the controllable switch S1b in an open or high resistive/non-conductive state. Furthermore, the remaining mirror transistors T.sub.2, . . . , T.sub.N+1 of the current mirror circuit can be connected to the first output terminal O1 by operating the controllable switches S2b, S3b, . . . , SN+1b in a closed or low resistive/conductive state and by operating the controllable switches S2a, S3a, . . . , SN+1a in an open or high resistive/non-conductive state.

[0029] FIG. 1 illustrates the current generator circuit wo comprising a current mirror circuit with P-type transistors. According to a possible alternative embodiment, the current mirror circuit 100 could also be implemented with N-type transistors. In this case, the current generator circuit would sink I1/I2. Basically, the current generator circuit can be implemented with transistors of the N- or P-type or with cascaded transistors. Furthermore, any type of mirror circuit can be adapted, as long as it can be decomposed into electrical components/unit elements that can be connected to the output terminal O1 and the output terminal O2 selectively.

[0030] FIG. 2 illustrates a block diagram of an electric circuit arrangement 10 to control current generation by means of a dynamic element matching method. The electric circuit arrangement comprises the current generator circuit 100 which can be embodied as shown and explained with reference to FIG. 1.

[0031] The electric circuit arrangement 10 further comprises a controller 200 to generate control signals C.sub.1, IC.sub.1, . . . , C.sub.N+1, IC.sub.N+1 to control a respective one of the controllable switching circuits. The electric circuit arrangement 10 further comprises a random code generator 300 to generate random codes and a counter 400 to generate a count. The random code generator 300 is configured to provide a respective code derived from a respective one of the random codes.

[0032] FIG. 3 shows an embodiment of the random code generator 300. As shown in the exemplified embodiment of FIG. 3, the random code generator 300 is configured or comprises a linear feedback shift register (LFSR) 310. The linear feedback shift register 310 comprises a shift register 320 including a plurality of storage cells 320a, . . . , 320n. Each of the storage cells 320a, . . . , 320n is configured to store one bit of the respective random code generated by the linear feedback shift register.

[0033] The linear feedback shift register 310 is configured to provide the respective derived code from storage cells to evaluated, these storage cells being a portion of the plurality of all of the storage cells 320a, . . . , 320n. The respective derived code is provided in dependence on a respective storage state of the storage cells to be evaluated, for example the storage cells 310a, 310b and 310c. According to the illustrated embodiment of the linear feedback shift register 310, the first three storage cells of the shift register 320 are the cells which contain the derived code which is evaluated by the controller 200.

[0034] As shown in FIG. 3, the linear feedback shift register 310 further comprises a logic circuitry 330 which receives the storage content of at least two storage cells of the shift register 320. In the illustrated example of the linear feedback shift register 310, the logic circuitry 330 receives the storage content of the third-last storage cell 320l and the storage content of the last storage cell 320n. The storage content of these two storage cells is combined by the logic circuitry 330. The output of the logic circuitry 330 is connected to an input side of the shift register 320 so that a new storage content is moved in the first storage cell 320a of the shift register and the respective content of the other storage cells 320b, . . . , 320n is shifted to the right by one storage cell.

[0035] The use of a linear shift register for the random code generator 300 allows to generate a pseudo-random code which repeats with a long period.

[0036] The embodiment of the linear feedback shift register shown in FIG. 3 is only an example for the implementation of a code generator which may be used for the electric circuit arrangement 10. The particular implementation of the linear feedback shift register 310 depends from the chosen polynomial. As a result, the random code generator 300 based on the linear feedback shift register 310 can be advantageously adapted to the application in which the electric circuit arrangement 10 is used for current generation. In particular, the chosen polynomial and thus the realization of the linear feedback shift register can be adapted to the needed application purpose.

[0037] Another advantage is that the length of the generated pseudo-random sequence/code can be easily affected by the number X of the storage cells 320a, . . . , 320n of the shift register 320. The more storage cells that are provided for the shift register 320, the longer the repeating period for the pseudo-random sequence (2.sup.X−1).

[0038] As shown in FIG. 2, the electric circuit arrangement 1 comprises a clock circuit 500 to generate a clock signal CLK between subsequent time steps. The random code generator 300 is clocked by the clock signal CLK such that the respective one of the random codes and the respective one of the derived codes is generated in a respective one of the time steps.

[0039] Referring to FIG. 2, the controller 200 is configured to select one of the respective derived code and the count depending on the derived code and to use the selected one of the respective derived code and the count provided by the counter 400 to generate a respective one of the control signals C.sub.1, IC.sub.1, . . . , C.sub.N+1, IC.sub.N+1 to control a respective one of the controllable switching circuits SC.sub.1, . . . , SC.sub.N+1 of the current generator circuit 100. The controller 200 is clocked by the clock signal CLK such that the respective derived code of the random code generator 300 or the count of the counter 400 is used in the respective one of subsequent time steps to generate the control signals C.sub.1, IC.sub.1, . . . C.sub.N+1, IC.sub.N+1.

[0040] The use of a clock circuit advantageously enables to operate the controller 200 and the random code generator 300 as clocked circuits. As a result, a new random code, and thus a new derived code, is provided by the random code generator 300 in every clock cycle. Furthermore, the switching state of the controllable switching circuits SC.sub.1, . . . , SC.sub.N+1 is changed by the controller 200 in every clock cycle so that the use of the electrical components, for example the mirror transistors, for the generation of the output current is changed every clock cycle by means of dynamic element matching. As a result, an output current can be generated by the current generator circuit 100 which is close to a predefined rational factor of the precise reference current IREF.

[0041] The controller 200 is configured to generate the control signals C.sub.1, IC.sub.1, . . . C.sub.N+1, IC.sub.N+1 such that one of the output current paths P.sub.1, . . . , P.sub.N+1 with its respective electrical component is connected to the second output terminal O2 and the remainder of the output current paths with their respective electrical component are connected to the first output terminal O1. Regarding the embodiment of the current generator circuit 100 being configured as a current mirror circuit shown in FIG. 1, the controller 200 is configured to generate the control signals to control the respective controllable switching circuits SC.sub.1, . . . , SC.sub.N+1 such that only one of the output current paths with its mirror transistor is connected to the output terminal O2, and the remainder of the output current paths with their respective current mirror are connected to the output terminal O1.

[0042] The proposed configuration of the electric circuit arrangement enables to provide the output current at the output terminal O1 as a sum of various partial currents which are generated by the electrical components being arranged in the respective output current path. The amount of the output current is thus defined by the number of partial currents to be summed at the output terminal O1 and, in particular, by the geometrical size of the electrical component, for example the mirror transistor, being included in the respective output current path.

[0043] According to an embodiment of the electric circuit arrangement 10, the random code generator 300 may provide the random codes and thus also the derived codes in a hexadecimal or binary format which can easily be stored in the storage cells 320a, . . . , 320n of the shift register 320. The controller 200 is configured to use the derived code to decide if the derived code generated by the random code generator 300 or the count generated by the counter has to be selected to generate the control signals C.sub.1, IC.sub.1, . . . C.sub.N+1, IC.sub.N+1 to control the controllable switching circuits SC.sub.1, . . . , SC.sub.N+1 of the current generator circuit 100.

[0044] According to a possible embodiment of the electric circuit arrangement 10, the controller 200 is configured to use the respective derived code provided from the random code generator 300 to generate the control signals C.sub.1, IC.sub.1, . . . C.sub.N+1, IC.sub.N+1 when a decimal representation C of the derived code is lower than the number N of the remaining output current paths. Furthermore, the controller 200 is configured to use the count provided by the counter 400 to generate the control signals C.sub.1, IC.sub.1, . . . C.sub.N+1, IC.sub.N+1 when the decimal representation C of the derived code is larger than the number N of remaining output current paths of the current generator circuit 100.

[0045] The proposed embodiment of the controller 200 advantageously allows to combine a random code generation of a random code generator being configured as a linear feedback shift register with the code generation of a counter. Assuming the random code generator 300 comprises X storage cells of which M storage cells are to be evaluated to provide the derived code, the linear feedback shift register generates 2M derived codes.

[0046] Since the generated 2.sup.M derived codes are larger than the number N+1 of output current paths but only N+1 codes are required to control the controllable switching circuits SC.sub.1, . . . , SC.sub.N+1, the random code generator 300 generates illegal/non-permitted derived codes. The generation of the control signals C.sub.1, IC.sub.1, . . . C.sub.N+1, IC.sub.N+1 in dependence on an illegal code generated by the random code generator 300 has to be avoided. In particular, if an illegal code, for example an non-permitted binary code, having a decimal representation being larger than the number N of the remaining output current paths of the current generator circuit 100 to be connected to the output terminal O1 is generated by the random code generator 300, the controller 200 advantageously selects the count generated by the counter 400 to determine the code used to generate the control signals C.sub.1, IC.sub.1, . . . , C.sub.N+1, IC.sub.N+1 to control the controllable switching circuits SC.sub.1, . . . , SC.sub.N+1 of the current generator circuit 100.

[0047] According to an embodiment of the electric circuit arrangement 10, the linear feedback shift register 310 is configured such that the storage cells to be evaluated, for example the storage cells 310a, 310b and 310c, are provided with a number M which fulfils the condition 2.sup.M being larger than N+1, wherein N+1 is the number of the output current paths P.sub.1, . . . , P.sub.N+1 of the current generator circuit 100.

[0048] This configuration of the linear feedback shift register 310 allows to generate a number of derived codes being larger than the number of available output current paths P.sub.1, . . . , P.sub.N+1 of the current generator circuit 100. Thus, the linear feedback shift register 310 allows to generate a large number of random codes by avoiding repeating codes with a small period, as this is typical for a rotation-based dynamic element matching.

[0049] According to an embodiment of the electric circuit arrangement 10, the counter 400 is configured to increase the count when the count is used by the controller 200 to generate the control signals C.sub.1, IC.sub.1, . . . C.sub.N+1, IC.sub.N+1. In particular, the counter 400 may be configured to increase the count between a start value and a final value, wherein the number of counts between the start value and the final value corresponds to the number of output current paths P.sub.1, . . . , P.sub.N+1 of the current generator circuit 100.

[0050] This configuration of the counter 400 advantageously allows to implement the counter 400 with low area consumption, wherein the complexity of the counter 400 is directly dependent and adapted to the current generator circuit and, in particular, to the number of output current paths of the current generator circuit 100. Moreover, the use of the counter 400 to generate a count which is used as an auxiliary code allows to overcome the limitation of the generation of 2.sup.M codes given by the linear feedback shift register alone. Furthermore, the generation of an auxiliary code by the counter allows to extend the dynamic element matching method to an arbitrary number of codes at run time.

[0051] In case an application requires at least two current mirror circuits to be provided, and a correlation between the random codes generated by the current mirror circuits has to be avoided, a second counter dedicated to the additional current generator circuit may be included, and the controller can apply the same algorithm to both outputs. The input code from the linear feedback shift register has to be different, so that a different tap of its outputs has to be selected.

[0052] The functionality of the electric circuit arrangement 10 is explained in the following with reference to the control algorithm illustrated in FIG. 4 and the list of states of the random code generator 300 and the counter 400 illustrated in FIG. 5.

[0053] The electric circuit arrangement 10 is used to control current generation such that the current generator circuit 100 generates an output current I1 with a defined ratio in relation to the reference current IREF or the output current I2. The basing sizing parameter is the target current ratio N. In order to generate an output current I1=N*I2, one of the output current paths and thus one of the electrical components, for example one of the mirror transistors, has to be connected to the output terminal O2, whereas the other output current paths and thus the remaining electrical components, for example the remainder of the mirror transistors, have to be connected to the output terminal O1.

[0054] Referring to FIG. 1, the current generator circuit 100 has N+1 output current paths/control lines, wherein the respective controllable switching circuits SC.sub.1, . . . , SC.sub.N+1 decide, which one of the electrical components, for example which one of the unit current sources/mirror transistors T.sub.1, . . . , T.sub.N, has to be connected to the output terminal O.sub.1 or the output terminal O.sub.2.

[0055] The purpose of the random code generator 300, for example the linear feedback shift register 310, is to generate a pseudo-random code/number of width X. From the possible X outputs of the random code generator 300, only a number M of storage cells to be evaluated are used to generate a derived code from the generated random code. As a consequence, the random code generator 300 may generate a number of 2.sup.M possible derived codes. As explained above, the number 2.sup.M of possible derived codes is higher than the number of the output current paths P.sub.1, . . . , P.sub.N+1 or the number of the electrical components, for example the mirror transistors, T.sub.1, . . . , T.sub.N+1, of the current generator circuit 100.

[0056] The controller 200 is configured to update the random code generator 300, for example the linear feedback shift register 310, periodically in every clock cycle, according to the requirements of the application. At every update, the derived code corresponding to the storage content of the number M of storage cells of the shift register 320 is compared with the number N. The controller 200 evaluates the derived code, for example a binary code. If the controller 200 detects that a decimal representation C of the derived code is lower than or equal to N (C≤N), then the derived code generated by the random code generator 300 is considered by the controller 200 as permitted code and is selected by the controller to generate the control signals C.sub.1, IC.sub.1, . . . C.sub.N+1, IC.sub.N+1 to control the controllable switching circuits SC.sub.1, . . . , SC.sub.N+1 of the current generator circuit 100.

[0057] On the other hand, if the controller 200 detects that the decimal representation C of the derived code generated by the random code generator 300 is larger than N (C>N), then the derived code is considered by the controller 200 as non-permitted code, and the controller 200 selects the count of the auxiliary counter 400 counting from 0 to N to generate the control signals C.sub.1, IC.sub.1, . . . C.sub.N+1, IC.sub.N+1 to control the controllable switching circuits SC.sub.1, . . . , SC.sub.N+1. Thereafter, the count of the counter 400 is increased.

[0058] FIG. 5 illustrates an example of a list of states of the random code generator 300 and the counter 400 which are evaluated by the controller 200 to detect, if a derived code is a permitted or non-permitted code, and to select the derived code from the random code generator 300, if the derived code is considered as permitted code, and to select the count from the counter 400 to generate the control signals C.sub.1, IC.sub.1, . . . C.sub.N+1, IC.sub.N+1 to control the controllable switching circuits SC.sub.1, . . . , SC.sub.N+1, if the derived code is considered as a non-permitted code.

[0059] Referring to the illustrated exemplary list of FIG. 5 and assuming the random code generator 300 comprises the linear shift register 310, the linear feedback shift register 310 comprises twenty storage cells (X=20) to generate a random code which is given in the first column of the table of FIG. 5 in a hexadecimal format. The second column of the table of FIG. 5 shows a decimal representation of the derived code of the storage cells to be evaluated, for example the three storage cells of the linear feedback shift register 310.

[0060] According to the example in the third row of the table, the random code generator generates the random code DB546. The decimal representation of a derived code with M=3 storage cells to be evaluated associated to the hexadecimal code DB546 is “6” (row 3, column 2 of the table). Assuming that the current generator circuit 100 has six output current paths P.sub.1, . . . , P.sub.6 or six electrical components, for example six mirror transistors, T.sub.1, . . . , T.sub.6, i.e. N=6, the controller selects the output of the counter 400 with the count “o” to generate the control signals to control the controllable switching circuits SC.sub.1, . . . , SC.sub.6 of the current generator circuit 100, because the condition C>N is fulfilled.

[0061] The subsequent rows 4 to 5 of the table of FIG. 5 respectively illustrate an example, where the condition C≤N is fulfilled, so that the controller 200 selects the derived code generated from the random code generator 300 to generate the control signals to control the controllable switching circuits SC.sub.1, . . . , SC.sub.6 of the current generator circuit 100.

[0062] FIG. 6A shows an example of an application that uses the electric circuit arrangement 10 to control current generation. According to the illustrated embodiment of an application, the electric circuit arrangement 10 is included in a signal processing circuit 1. The signal processing circuit 1 comprises at least one of a bias current generator 21 and/or a bandgap reference circuit 22 and/or a digital-to-analog converter 23 and/or an analog-to-digital converter 24. The electric circuit arrangement 10 may be included in at least one of the bias current generator 21 and/or the bandgap reference circuit 22 and/or the digital-to-analog converter 23 and/or the analog-to-digital converter 24. In particular, the analog-to-digital converter 24 can be embodied as a sigma-delta analog-to-digital converter.

[0063] FIG. 6B shows another application comprising a communication device 2 comprising a sensor circuit 30. The signal processing circuit 1 is included in the sensor circuit 30. The sensor circuit 30 can be embodied, for example, as one of a temperature sensor, a pressure sensor, a humidity sensor or a resistance measurement sensor, etc.

[0064] Although the invention has been illustrated and described in detail by means of the preferred embodiment examples, the present invention is not restricted by the disclosed examples and other variations may be derived by the skilled person without exceeding the scope of protection of the invention.