Memory Device and Method for Its Operation

Abstract

The invention describes a memory device which combines a switchable resistive element and a superconductor element electrically in parallel. The switchable resistive element comprises an active material, which is switchable between first and second values of electrical resistivity ρ.sub.1 and ρ.sub.2 at the same temperature, wherein ρ.sub.1 is different to ρ.sub.2. The superconductor element is operable so that at least part of the superconductor element is switchable from a superconducting state to a non-superconducting state. When the superconductor element is switched from the superconducting state to the non-superconducting state, a current injection is provided through the switchable resistive element capable of switching the switchable resistive element between said first and second values of electrical resistivity.

Claims

1. A memory device comprising: a switchable resistive element comprising an active material, the active material being switchable, by current injection, between first and second values of electrical resistivity ρ.sub.1 and ρ.sub.2 at the same temperature, wherein ρ.sub.1 is different to ρ.sub.2; and a superconductor element connected electrically in parallel with the switchable resistive element, the superconductor element being operable so that at least part of the superconductor element is switchable from a superconducting state to a non-superconducting state, wherein the memory device is operable so that, when the superconductor element is switched from the superconducting state to the non-superconducting state, a current injection is provided through the switchable resistive element capable of switching the switchable resistive element between said first and second values of electrical resistivity.

2. A memory device according to claim 1 wherein the first and second resistive states of the active material represent first and second memory states of the switchable resistive element.

3. A memory device according to claim 1 wherein the memory device is a volatile memory device.

4. A memory device according to claim 1 wherein the memory device is a non-volatile memory device.

5. A memory device according to claim 1 wherein the superconductor is in the form of a nanowire or a narrow channel.

6. A memory device according to claim 1 wherein the superconductor element includes a constriction region adapted to switch to a non-superconducting state in preference to the remainder of the superconductor element.

7. A memory device according to claim 1 wherein the superconductor element and the switchable resistive element are formed in a stacked arrangement.

8. A memory device according to claim 1 wherein the superconductor element is a two terminal device.

9. A memory device according to claim 1 wherein the superconductor element is a three terminal device.

10. A memory device according to claim 1 wherein the active material of the switchable resistive element is selected from the group consisting of: 1T-TaS.sub.2, a layered dichalcogenide, a chalcogenide, and an oxide material.

11. A memory device according to claim 1 wherein the current injection is provided, in use, by an external circuit.

12. A method of operation of a memory device, the memory device comprising: a switchable resistive element comprising an active material, the active material being switchable, by current injection, between first and second values of electrical resistivity ρ.sub.1 and ρ.sub.2 at the same temperature, wherein ρ.sub.1 is different to ρ.sub.2; and a superconductor element connected electrically in parallel with the switchable resistive element, the superconductor element being operable so that at least part of the superconductor element is switchable from a superconducting state to a non-superconducting state, the method including the steps: providing a temperature environment for at least the superconductor element to allow at least part of the superconductor element to be in a superconducting state; and switching at least part of the superconductor element from the superconducting state to a non-superconducting state and thereby causing a current injection to flow through the switchable resistive element capable of switching the switchable resistive element between said first and second values of electrical resistivity.

13. A method according to claim 12, wherein at least part of the superconductor element is switched from a superconducting state to a non-superconducting state by current density.

14. A method according to claim 12, wherein at least part of the superconductor element is switched from a superconducting state to a non-superconducting state by temperature.

15. A method according to claim 12 wherein the current injection is in a pulsed mode.

16. A method according to claim 12 wherein the current injection is in a continuous mode.

17. A method according to claim 12 wherein the current injection is achieved by control of an applied current to the device or by control of an applied voltage across the device.

Description

SUMMARY OF THE FIGURES

[0036] Embodiments and experiments illustrating the principles of the invention will now be discussed with reference to the accompanying figures in which:

[0037] FIG. 1. An effective simplified circuit diagram of the ‘parallelotron’ or ‘p-tron’ device, including superconductor element 1 and switchable resistive element 2 in physical contact or connected electrically via external circuit to the superconductor element.

[0038] FIG. 2. Schematic of a superconductor element 3 fabricated on top of a switchable resistive element 2 forming a parallel device on substrate 5. A constriction 6 in the superconductor element 3 serves to locally increase the current density and create a hot spot 7 where the current density is sufficient to cause a superconductor-to-normal state transition which then causes part of the current to flow through the switchable resistive element 4.

[0039] FIG. 3. The behaviour of a switchable resistive element according to Vaskivskyi et al. (2016). a) The V-j curve for a switchable resistive element Write cycle. b) The V-j curve for the Erase cycle. c) The V-j curves corresponding to the R.sub.HI and R.sub.LO states of the switchable resistive material. d) The V-j curves R.sub.S1 and R.sub.S2 for a superconductor nanowire with high (R.sub.HI) and low (R.sub.LO) shunt resistances respectively, j.sub.c is the superconducting critical current. e) The Write cycle for a nanowire weak link with a switchable resistive element switching from R.sub.HI to R.sub.LO at or above a threshold current j.sub.w. f) The Erase cycle for a nanowire weak link with a switchable resistive element shunt switching from R.sub.LO to R.sub.HI at or above a threshold current j.sub.E.

[0040] FIG. 4. Supplements FIG. 3 to show a) The V-j curve for a switchable resistive element Write cycle. b) The V-j curve for the Erase cycle. c) The V-j curves corresponding to the R.sub.HI and R.sub.LO states of the switchable resistive material. d) The V-j curves R.sub.S1 and R.sub.S2 for a superconductor nanowire with high (R.sub.HI) and low (R.sub.LO) shunt resistances respectively e) The V-j curves for; the Write cycle for a switchable resistive element, a superconductor nanowire with resistance R.sub.S1 and R.sub.S2 with high (R.sub.HI) and low (R.sub.LO) shunt resistances respectively, the Write cycle for a nanowire weak link with a switchable resistive element switching from R.sub.HI to R.sub.LO at or above a threshold current j.sub.W.

DETAILED DESCRIPTION OF THE INVENTION

[0041] Aspects and embodiments of the present invention will now be discussed with reference to the accompanying figures. Further aspects and embodiments will be apparent to those skilled in the art. All documents mentioned in this text are incorporated herein by reference.

[0042] In a general overview, it can be seen that the preferred embodiments of the invention provide a hybrid superconducting memory device that combines a superconductor element in parallel with a switchable resistive element. The preferred embodiments are characterized by ultrafast switching speed, two- or three-terminal operation, scalability, low switching energy (due to the ability to use low-energy memristive elements), low-temperature operation, ease of integration, simple 2-element circuit design and compatibility with superconducting electronics, particularly superconducting flux-quantum electronics.

[0043] The basic device in one embodiment is composed of a superconductor element on top of a switchable resistive element, effectively forming a narrow superconducting channel shunted with a controllable resistance shunt. An effective circuit diagram of the device is shown in FIG. 1. The shunt resistance is R.sub.s which is switchable (non-volatile), or a non-linear element that acts as a variable or non-linear shunt resistance.

[0044] Typically, a constriction is fabricated in the superconducting channel such that the current density is higher at a selected region in the channel as shown in FIG. 2.

[0045] The Principle of Operation of the Device

[0046] The device consists of a narrow superconductor channel deposited on a memristive non-volatile CDW material described previously (U.S. Pat. No. 9,818,479 (B2)), thereby forming a device with parallel current paths (‘parallelotron’). The memristive non-volatile CDW material or memristor may otherwise be referred to as a switchable resistive element. The memory device is connected such that a supercurrent j passes through the superconducting channel. When the supercurrent exceeds a critical value j, it causes the superconductor to go normal and become resistive with the formation, for example, of a thermal hot spot. When the superconducting channel goes to the normal state, a voltage appears across the memristor and part of the current j.sub.m starts to flow in parallel through the memristive material below. Above a certain threshold current j.sub.W, or threshold applied voltage V.sub.W, the memristor is caused to undergo a transition to the low-resistance state which constitutes the Write operation, placing the device into a low-shunt resistance state.

[0047] The reverse transition from the low resistance state to the high resistance state of the shunt memristor (the Erase operation) is caused when the current exceeds a certain but different value of critical current j.sub.c2, changing the shunt resistance to a high value. A geometrical constriction in the memristive material may be used to confine and tailor the current path through the memristive material. The detailed operation of a preferred embodiment of the device is described below.

Operation of the CDW Memristor without Superconducting Nanowire

[0048] The operation cycles are shown in FIGS. 3 a-c and FIGS. 4 a-c, describing the Write, Erase and read cycles of a CDW memristor, as described by Vaskivskyi et al. (2016).

[0049] In the Write cycle (FIG. 3a and FIG. 4a) the device is initially in a high resistance state R.sub.HI, in which the current-voltage (j-V) curve is approximately described by j=j.sub.0 exp(V/V.sub.0), where j.sub.0 and V.sub.0 are constants (Vaskivskyi et al., 2016). Above a threshold current j.sub.W, the resistance drops to a low resistance state R.sub.LO, remaining in this state indefinitely, i.e. as long as the memristor remains in the low-resistance state as determined by external factors, such as the state lifetime, or temperature.

[0050] The Erase cycle (FIG. 3b and FIG. 4b) involves increasing the current in the low-resistance state R.sub.LO of the CDW memristor until an Erase threshold is reached (j.sub.E). Upon reducing the current, the original high-resistance state R.sub.HI is recovered.

[0051] Read operations in the R.sub.HI and R.sub.LO states are shown in FIG. 3c and FIG. 4c.

[0052] Operation of the Superconducting Nanowire Channel without CDW Memristor

[0053] The operation of the nanowire channel shunted by a fixed resistance R.sub.s as shown in FIG. 1 is described by Brenner et al. (2012) and is shown in FIG. 3d and FIG. 4d for two different values of R.sub.s1 and R.sub.s2. For R.sub.s>R.sub.critical, where R.sub.critical is some critical resistance value, the device shows hysteretic V-I behavior. When R.sub.s<R.sub.critical, the device shows no hysteresis and a lower overall resistance, with a higher critical current value.

[0054] Operation of the Superconducting Nanowire and CDW Memristor in Parallel (Parallelotron)

[0055] a) The Write Cycle

[0056] In the initial state, the CDW memristor is in the R.sub.HI state, and the superconducting channel in the R.sub.S1 state. As the supercurrent increases, it follows the trajectory shown in FIG. 3e, 4e. At a critical value j.sub.c1, the superconductor element becomes resistive and follows the path up to the point where the current through the memristor exceeds j.sub.W. At this point the CDW memristor switches to R.sub.LO (FIG. 4e), effectively changing the shunt resistance, thus causing the superconducting channel to revert to the R.sub.S2 state (FIGS. 3d, e and 4d, e),

[0057] b) The Erase Cycle

[0058] The device is in the initial state R.sub.S2. Increasing the current causes it to follow the curve R.sub.S2 until j.sub.E is reached through the CDW memristor shunt (FIG. 3 d, f and FIG. 4 d, f). Upon reducing the current, the CDW memristor reverts to the high resistance state R.sub.HI and the superconducting channel reverts to the state R.sub.S1 (FIGS. 3 d, f and FIG. 4 d, f).

[0059] The values of critical currents and switching thresholds can be varied by appropriate design, thickness, widths of either channel.

[0060] In another embodiment, the two-terminal device is extended to a three-terminal configuration incorporating a superconductor on top of a memristive material, whereby an additional narrow choke is used to control the supercurrent in the narrow nanowire channel as demonstrated, but not limited to, the nano-cryotron (nTron) device described by McCaughan et al. (2014).

[0061] The nTron described by McCaughan et al. (2014) is a thin-film superconducting device consisting of a gate nanowire and a channel nanowire with its two ends referred to as a drain and source. The intersection between the gate and the channel is referred as the choke. The choke is placed perpendicularly to where the channel is narrowest and the current density is the highest to maximize the sensitivity of the nTron. Current entering the gate terminal switches the phase of the choke from the superconducting to the resistive state when the local critical current density is exceeded. Breaking the superconductivity in a nanowire leads to the diffusion of hot quasiparticles and a growth of resistance. In the present invention, when the nTron channel switches to a resistive state, a current injection will flow through the memristor.

[0062] In a further embodiment of the device, the memristor and superconducting channel are not in direct contact, but are in electrical contact as shown in FIG. 1, such that they are connected on the chip, the substrate or the contacts are configurable outside the chip.

[0063] In a further configuration, an array of memory devices substantially as described above can be set out, for example with a set of word lines and bit lines in a cross-bar configuration.

[0064] The features disclosed in the foregoing description, or in the following claims, or in the accompanying drawings, expressed in their specific forms or in terms of a means for performing the disclosed function, or a method or process for obtaining the disclosed results, as appropriate, may, separately, or in any combination of such features, be utilised for realising the invention in diverse forms thereof.

[0065] While the invention has been described in conjunction with the exemplary embodiments described above, many equivalent modifications and variations will be apparent to those skilled in the art when given this disclosure. Accordingly, the exemplary embodiments of the invention set forth above are considered to be illustrative and not limiting. Various changes to the described embodiments may be made without departing from the spirit and scope of the invention.

[0066] For the avoidance of any doubt, any theoretical explanations provided herein are provided for the purposes of improving the understanding of a reader. The inventors do not wish to be bound by any of these theoretical explanations.

[0067] Any section headings used herein are for organizational purposes only and are not to be construed as limiting the subject matter described.

[0068] Throughout this specification, including the claims which follow, unless the context requires otherwise, the word “comprise” and “include”, and variations such as “comprises”, “comprising”, and “including” will be understood to imply the inclusion of a stated integer or step or group of integers or steps but not the exclusion of any other integer or step or group of integers or steps.

[0069] It must be noted that, as used in the specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Ranges may be expressed herein as from “about” one particular value, and/or to “about” another particular value. When such a range is expressed, another embodiment includes from the one particular value and/or to the other particular value. Similarly, when values are expressed as approximations, by the use of the antecedent “about,” it will be understood that the particular value forms another embodiment. The term “about” in relation to a numerical value is optional and means for example +/−10%.

REFERENCES

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