METHOD FOR CONNECTION BY BRAZING ENABLING IMPROVED FATIGUE RESISTANCE OF BRAZED JOINTS
20220001475 · 2022-01-06
Inventors
Cpc classification
H01L2224/13076
ELECTRICITY
H01L2224/11312
ELECTRICITY
H01L2924/00014
ELECTRICITY
H01L2224/1329
ELECTRICITY
H01L2224/131
ELECTRICITY
H01L2224/81193
ELECTRICITY
H01L2224/81191
ELECTRICITY
H01L2224/133
ELECTRICITY
H01L2224/13023
ELECTRICITY
H01L2924/00014
ELECTRICITY
H01L2224/133
ELECTRICITY
B23K2103/08
PERFORMING OPERATIONS; TRANSPORTING
H01L2224/131
ELECTRICITY
H01L2224/1329
ELECTRICITY
B23K3/0623
PERFORMING OPERATIONS; TRANSPORTING
B23K1/0016
PERFORMING OPERATIONS; TRANSPORTING
H01L2224/1411
ELECTRICITY
International classification
Abstract
The connection method between at least two elements (E1, E2) corresponding to a printed circuit (4) and to an electronic component (5), comprises a step of forming a plurality of pad-type stacks (2) of bosses (3), the stacks (2) of bosses (3) being formed on a face (10) of a first (E1) of the elements (E1, E2), the stacks (2) of bosses (3) each comprising the same given number of bosses (3), said method also comprising a step of depositing a brazing product (7) on this first element (E1) provided with stacks (2) of bosses (3), a step of arranging the second (E2) of the elements (E1, E2) on the first element (E1), and a step of remelting the assembly thus formed, in order to obtain an electronic device (1). This method makes it possible to produce a precise and flexible raising of surface mounted electronic components.
Claims
1. A method for connection, by brazing, between at least two elements, said two elements corresponding respectively to a printed circuit and to an electronic component characterised in that it comprises at least the following sequence of steps: a) a step of forming a plurality of stacks of stud bump, said stacks of bumps being formed on a face of a first of said elements, said stacks of bumps each comprising the same given number of bumps; b) a step of depositing a brazing product on this first element provided with stacks of bumps or on the second element; c) a step of arranging the second of said elements on said first element; and d) a step of remelting the assembly thus formed in the arranging step, in order to obtain an electronic device.
2. The method according to claim 1, characterized in that the forming step consists, for each stack of bumps, in implementing, in succession, a predetermined number of forming sub-steps, each of said forming sub-steps consisting in forming a bump, the bumps of each stack of bumps being formed in succession by being stacked on top of each other.
3. The method according to claim 2, characterised in that each forming sub-step comprises at least the following operations: an operation of heating of a metal wire by means of an electrode; an operation of depositing a metal ball formed at the end of the heated metal wire; an operation of crushing and welding the metal ball; and an operation of separating the metal wire from the crushed metal ball to form the bump.
4. The method according to claim 1, characterised in that each bump has a height of between 20 μm and 30 μm.
5. The method according to claim 1, characterised in that each stack of bumps has a height of between 110 μm and 150 μm.
6. The method according to claim 1, characterised in that at least some of said stacks of bumps are separated from each other by a distance of between 0.05 mm and 0.1 mm on said first element.
7. The method according to claim 1, characterised in that the bumps are made of one of the following materials: gold, copper, silver, platinum.
8. The method according to claim 1, characterised in that it comprises a plurality of sequences of steps, each of these sequences of steps enabling to connect an electronic component onto the same printed circuit so as to obtain an electronic device comprising a single printed circuit provided with a plurality of electronic components.
9. The method according to claim 1, characterised in that said first element corresponds to the printed circuit, and said second element corresponds to the electronic component.
10. The method according to claim 1, characterized in that said first element corresponds to the electronic component, and said second element corresponds to the printed circuit.
11. An electronic device, characterised in that it is obtained by implementing the method according to claim 1.
Description
BRIEF DESCRIPTION OF THE FIGURES
[0042] The attached figures will make it clear how the invention can be implemented. In these figures, identical references denote similar elements. More particularly:
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DETAILED DESCRIPTION
[0054] The method P illustrating the invention and shown schematically in
[0055] These two elements E1 and E2 correspond, one to a printed circuit 4 (or PCB type (Printed Circuit Board)), and the other to an electronic component 5.
[0056] This electronic component 5 may, in particular, be a printed circuit 6 of the QFN type (for “Quad Flat No-leads package”) as shown in
[0057] According to the invention, said method P comprises, as shown in
[0062] Thus, thanks to the method P, an elevation is generated at the forming step F1 by the installation of stacks 2 of stud bumps 3, which enables to increase the height of the brazed joints of the first element E1 with respect to the second element E2, thus enabling to increase the robustness and, more precisely, the thermo-mechanical fatigue resistance of the electronic device 1 obtained after carrying out said method P.
[0063] This method P enables to improve the behaviour in a severe environment (as mentioned above) for “consumer” components. More particularly, the electronic device 1 thus formed is able to withstand a number of temperature cycles, between −55° C. and +125° C., over a period of about 25 years, as required in the military field.
[0064] The forming step F1 consists, for each stack 2 of bumps 3, in implementing, successively, a predetermined number N of forming sub-steps F1i, i varying from 1 to N.
[0065] Each of said successive forming sub-steps F11, F12, . . . , to F1N (
[0066] By way of illustration, in
[0067] To this end, in a preferred embodiment, each forming step F1i, by thermosonic bonding, is carried out, as shown in
[0072] For the purpose of the present invention: [0073] each bump 3 preferably has a height h (shown in
[0075] Thus, by way of illustration, each stack 2 of bumps 3 preferably has a height H (shown in
[0076] Furthermore, with the aforementioned method P, it is possible to bring the stacks 2 close to each other at a short distance, if this is necessary or desired in the forming step F1. By way of example, it is conceivable that at least some of the stacks 2 of bumps are separated from each other, on said first element E1, by a distance D (shown in
[0077] In a particular embodiment, the bumps 3 are made of one of the following materials: copper, gold, silver or platinum. Preferably, however, said bumps 3 are made of copper or silver so as to allow better cohesion with the brazing product 7 and avoid dissolution (in the case of gold) of the bump by the brazing.
[0078] The method P and in particular the forming step F1 can be integrated into standard brazing connection methods. Thus, in particular the depositing step F2 can be implemented in a standard way.
[0079] Therefore, the method P, as described above: [0080] is flexible and adaptable; [0081] is not limited by the pitch (or distance) of the inputs/outputs (distance D between the inputs/outputs); [0082] can be carried out with precise and wide control of the height variation range, with for example 2 to 30 levels of stacked bumps 3 (per stack of bumps); and [0083] enables to limit the thermal stresses for the elements E1 and E2 during the assembly phases. The thermal stresses undergone while carrying out the method are limited, with a maximum temperature of the order of 150° C. during the thermosonic bonding step F1.
[0084] In a particular embodiment (not shown), the method P comprises a plurality of sequences of steps SF. Each of these sequences of steps SF is intended to connect another electronic component on the same printed circuit. This enables to obtain an electronic device comprising a single printed circuit provided with a plurality of electronic components.
[0085] Furthermore, thanks to the embodiment of the method P, the bumps 3 (and thus the element E2) can thus be arranged on an element E1, the face 10 of which has a substantially flat shape, as shown in
[0086] As indicated above, for the purpose of the present invention, said first element E1 on which the stacks 2 of bumps 3 are formed may be either the printed circuit board 4 or the electronic component 5.
[0087] Thus: [0088] in a first embodiment, as shown in
[0090] With method P, there is great freedom and therefore flexibility regarding the number and location of the stacks on the element E1. In particular, as illustrated in
[0091] The stack 2 of bumps 3 on an element E1, for example on an electronic component 5 such as an integrated circuit, thus enables to raise it and to obtain a maximum of brazing under this element E1. This stack 2 thus increases the height of the brazed joint (obtained in steps F3 and F4 using the brazing product 7) and improves the thermomechanical fatigue resistance of the electronic device 1.
[0092] Thus, thanks to the invention, a method P is obtained which is: [0093] flexible: [0094] in height, by choosing an appropriate height H per stack 2; [0095] in positioning on the element E1, with, for example, a formation of stacks 2 on heat dissipation ranges or on inputs/outputs of the element E1; [0096] in the number of stacks 2. By way of illustration, several thousand stacks 2 can be provided per element E1, in particular per electronic component 5; and [0097] adaptable. This method P can be integrated into standard brazing connection methods, and is adaptable according to the applications related to the electronic component and the printed circuit.
[0098] This method P can be implemented via automatic equipment and standard methods existing in the field of consumer electronics.
[0099] Furthermore, there is a possibility of isostatic formation of three stacks of bumps or hyperstatic formation of a large number of stacks of bumps.
[0100] Furthermore, said method P has no impact on repairs, and is adaptable to any type of stack distribution (or design).
[0101] Furthermore, the method P is in particular applicable to electronic components having: [0102] Bottom Terminations Components (BTC), for example QFN, DFN, or LCC; [0103] Ball Terminations in arrays, e.g. BGA or flip chip; [0104] Area terminations under the component, e.g. LGA.
[0105] The method P as described above, which is thus based on the formation of stacks 2 of bumps 3, has, in particular, the following features and advantages: [0106] a microelectronic precision adaptable to existing and future needs (distance (or pitch) D of 0.05 mm for example); [0107] a temperature to which the electronic component in particular is subjected, which is reduced, of the order of 150° C. during the thermosonic bonding; [0108] a repeatability of the geometry by automating the method; [0109] a self-controlled method; [0110] flexibility; [0111] controlled cost; and [0112] increased integration density.
[0113] This method is therefore mainly suitable for improving the fatigue life of the brazed joints. However, due to the high accuracy, this method can also perform specific secondary alignment functions (optical function alignment, three-axis function alignment, . . . ).