Pixel circuit and display apparatus

Abstract

A pixel circuit performs a threshold voltage correcting function. A sampling transistor becomes conductive in response to a control signal supplied from a scan line and samples a video signal supplied from a signal line to a pixel capacitor during a horizontal scanning period. The pixel capacitor applies an input voltage to a gate of a drive transistor in response to the sampled video signal. The drive transistor supplies an output current in accordance with the input voltage to a light-emitting device. A threshold voltage correcting period is provided to be part of the horizontal scanning period, to detect the threshold voltage of the drive transistor, and to write the threshold voltage in the pixel capacitor.

Claims

1. A display device comprising: a plurality of scanning lines disposed in rows, a plurality of signal lines disposed in columns, and a plurality of pixels arranged at places where the scanning lines and the signal lines intersect; and a control circuitry configured to drive the pixels through the scanning lines and the signal lines, wherein each of the pixels arranged along an n-th row of the rows respectively includes: a light emitting element a capacitor; a sampling transistor configured to supply a data signal from a corresponding one of the signal lines to the capacitor in response to a control signal supplied through a corresponding scanning line disposed in the n-th row; a drive transistor configured to supply a drive current to the light emitting element according to a voltage stored in the capacitor; and a switching transistor configured to connect the capacitor to a predetermined voltage line in response to a control signal supplied through a corresponding scanning line disposed in an (n-1)th row of the rows.

2. The display device according to claim 1, wherein the sampling transistor is configured to turn on a plurality of times before the voltage stored in the capacitor becomes a threshold voltage that reflects a property of the drive transistor.

3. The display device according to claim 2, wherein the drive transistor is configured to control a driving current from a power supply line to the light-emitting element depending on a potential held by the capacitor.

4. The display device according to claim 2, wherein the switching transistor has a first terminal connected to the predetermined voltage line, and a second terminal connected to a first terminal of the capacitor.

5. The display device according to claim 2, wherein a first pixel and a second pixel are connected to one of the signal lines, wherein the control circuitry is configured to sequentially provide, through the signal line: a predetermined signal in a first period; a first video signal for the first pixel in a second period; the predetermined signal in a third period; and a second video signal for the second pixel in a fourth period, wherein the control circuitry is configured to drive each of the first and second pixels so as to: perform a correction operation such that the voltage stored in the capacitor reflects a property of the drive transistor; and perform a sampling operation to sample a video signal, wherein a period of the correction operation of the first and second pixels is divided into the first and the third periods.

6. The display device according to claim 5, wherein the correction operation is performed during the first and third periods after the sampling transistor becomes conductive.

7. The display device according to claim 5, wherein the correction operation is configured to detect the property of the drive transistor and to write the property in the capacitor in the first and third periods.

8. The display device according to claim 5, wherein, during the second and fourth periods, the capacitor applies an input voltage to the drive transistor, the input voltage being a sum of a sampled video signal and the property of the drive transistor.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a block diagram illustrating a display apparatus according to the present invention.

(2) FIG. 2 is a circuit diagram illustrating a first embodiment of a pixel circuit included in the display apparatus illustrated in FIG. 1.

(3) FIG. 3 is a schematic view illustrating the pixel circuit included in the display apparatus illustrated in FIG. 2.

(4) FIG. 4 is a timing chart for describing an operation of the pixel circuit illustrated in FIG. 3.

(5) FIG. 5 is a schematic view for describing the operation of the pixel circuit illustrated in FIG. 3.

(6) FIG. 6 is a graph for describing the operation.

(7) FIG. 7 is a schematic view for describing the operation.

(8) FIG. 8 is a graph illustrating an operation characteristic of a drive transistor included in the pixel circuit illustrated in FIG. 7.

(9) FIG. 9 is a timing chart illustrating a second embodiment of the pixel circuit according to the present invention.

(10) FIG. 10 is a block diagram illustrating a display apparatus according to the present invention.

(11) FIG. 11 is a circuit diagram illustrating a third embodiment of pixel circuits included in the display apparatus illustrated in FIG. 10.

(12) FIG. 12 is a schematic view illustrating a pixel circuit included in the display apparatus illustrated in FIG. 11.

(13) FIG. 13 is a timing chart for describing an operation of the pixel circuit illustrated in FIG. 12.

(14) FIG. 14 is a block diagram illustrating a display apparatus according to a reference example.

(15) FIG. 15 is a schematic view of a pixel circuit included in the display apparatus illustrated in FIG. 14.

(16) FIG. 16 is a timing chart for describing an operation of the pixel circuit illustrated in FIG. 15.

BEST MODES FOR CARRYING OUT THE INVENTION

(17) Hereinafter, embodiments of the present invention are described in detail with reference to the drawings. First, an entire configuration of an active matrix display apparatus having a threshold voltage (Vth) correcting function is described with reference to FIG. 1. As illustrated in the figure, the active matrix display apparatus includes a pixel array 1 serving as a main unit and a peripheral circuit unit. The peripheral circuit unit includes a horizontal selector 3, a write scanner 4, a drive scanner 5, a correcting scanner 7, and so on. The pixel array 1 includes scan lines WS in rows, signal lines SL in columns, and pixels R, G, and B arranged in a matrix pattern at parts where the both lines cross each other. Pixels of three primary colors RGB are provided for enabling color display, but the present invention is not limited to this. Each of the pixels R, G, and B includes a pixel circuit 2. The signal lines SL are driven by the horizontal selector 3. The horizontal selector 3 constitutes a signal unit and supplies video signals to the signal lines SL. The scan lines WS are scanned by the write scanner 4. Also, other scan lines DS and AZ are provided in parallel with the scan lines WS. The scan lines DS are scanned by the drive scanner 5. The scan lines AZ are scanned by the correcting scanner 7. The write scanner 4, the drive scanner 5, and the correcting scanner 7 constitute a scanner unit and sequentially scan rows of pixels in each horizontal period. Each pixel circuit 2 samples a video signal from the signal line SL when selected by the scan line WS. Furthermore, the pixel circuit 2 drives a light-emitting device included in the pixel circuit 2 in response to the sampled video signal when selected by the scan line DS. In addition, the pixel circuit 2 performs a predetermined correcting operation when scanned by the scan line AZ.

(18) The above-described pixel array 1 is typically formed on an insulating substrate, such as glass, and is a flat panel. Each pixel circuit 2 includes an amorphous silicon thin film transistor (TFT) or a low-temperature polysilicon TFT. In the case of the amorphous silicon TFT, the scanner unit is constituted by TAB or the like separated from the panel, and is connected to the flat panel via a flexible cable. In the case of the low-temperature polysilicon TFT, the signal unit and the scanner unit can also be formed by the low-temperature polysilicon TFT, and thus the pixel array unit, the signal unit, and the scanner unit can be integrally formed on the flat panel.

(19) FIG. 2 is a circuit diagram illustrating a first embodiment of the pixel circuit 2 incorporated into the display apparatus illustrated in FIG. 1. The pixel circuit 2 includes four TFTs Tr1, Tr3, Tr4, and Trd, one capacitor element (pixel capacitor) Cs, and one light-emitting device EL. The transistors Tr1, Tr3, and Trd are N-channel polysilicon TFTs. Only the transistor Tr4 is a P-channel polysilicon TFT. The capacitor element Cs constitutes a pixel capacitor of the pixel circuit 2. The light-emitting device EL is a diode-type organic EL device including an anode and a cathode, for example. However, the present invention is not limited to this, but the light-emitting device includes all devices that typically emit light by current drive.

(20) In the drive transistor Trd, which is a main component of the pixel circuit 2, the gate G connects to one end of the pixel capacitor Cs, and the source S connects to the other end of the pixel capacitor Cs. The drain of the drive transistor Trd connects to a power supply Vcc via the second switching transistor Tr4. The gate of the switching transistor Tr4 connects to the scan line DS. The anode of the light-emitting device EL connects to the source S of the drive transistor Trd, and the cathode is grounded. The ground potential may be represented by Vcath. Also, the first switching transistor Tr3 exists between the source S of the drive transistor Trd and a predetermined reference potential Vss. The gate of the transistor Tr3 connects to the scan line AZ. On the other hand, the sampling transistor Tr1 connects between the signal line SL and the gate G of the drive transistor Trd. The gate of the sampling transistor Tr1 connects to the scan line WS.

(21) In this configuration, the sampling transistor Tr1 is brought into conduction in response to a control signal WS supplied from the scan line WS and samples a video signal Vsig supplied from the signal line SL to the pixel capacitor Cs during a horizontal scanning period (1H) assigned to the scan line WS. The pixel capacitor Cs applies an input voltage Vgs to the gate of the drive transistor Trd in response to the sampled video signal Vsig. The drive transistor Trd supplies an output current Ids in accordance with the input voltage Vgs to the light-emitting device EL during a predetermined light-emitting period. The output current Ids has dependency on the threshold voltage Vth in a channel region of the drive transistor Trd. The light-emitting device EL emits light at brightness in accordance with the video signal Vsig by the output current Ids supplied from the drive transistor Trd.

(22) As a feature of the present invention, the pixel circuit 2 includes correcting means including the first switching transistor Tr3 and the second switching transistor Tr4. This correcting means operates in part of the horizontal scanning period (1H), detects the threshold voltage Vth of the drive transistor Trd, and writes it in the pixel capacitor Cs, in order to cancel the dependency of the output current Ids on the threshold voltage Vth. This correcting means operates in a state where the sampling transistor Tr1 is in conduction and one end of the pixel capacitor Cs is held at a certain potential Vss0 by the signal line SL during the horizontal scanning period (1H), and charges the pixel capacitor Cs until a potential difference from the other end of the pixel capacitor Cs to the certain potential Vss0 becomes the threshold voltage Vth. This correcting means detects the threshold voltage Vth of the drive transistor Trd and writes it in the pixel capacitor Cs in the first half of the horizontal scanning period (1H), whereas the sampling transistor Tr1 samples the video signal Vsig supplied from the signal line SL to the pixel capacitor Cs in the latter half of the horizontal scanning period (1H). The pixel capacitor Cs applies the input voltage Vgs, which is the sum of the sampled video signal Vsig and the written threshold voltage Vth, between the gate G and source S of the drive transistor Trd, thereby cancelling the dependency of the output current Ids on the threshold voltage Vth. This correcting means includes the first switching transistor Tr3, which is brought into conduction before the horizontal scanning period (1H) and which performs reset so that the potential difference across the pixel capacitor Cs exceeds the threshold voltage Vth, and the second switching transistor Tr4, which is brought into conduction during the horizontal scanning period (1H) and which charges the pixel capacitor Cs until the potential difference across the pixel capacitor Cs becomes the threshold voltage Vth. The sampling transistor Tr1 samples the video signal Vsig supplied from the signal line SL to the pixel capacitor Cs during a signal supplying period when the signal line SL is at the potential of the video signal Vsig in the horizontal scanning period (1H), whereas the correcting means detects the threshold voltage Vth of the drive transistor Trd and writes it in the pixel capacitor Cs during a signal fixed period when the signal line SL is at the certain potential Vss0 in the horizontal scanning period (1H).

(23) In this embodiment, the output current Ids from the drive transistor Trd has dependency on carrier mobility μ in addition to the threshold voltage Vth in the channel region. In order to deal with this, the correcting means of the present invention operates in part of the horizontal scanning period (1H) in order to cancel the dependency of the output current Ids on the carrier mobility μ, takes the output current Ids from the drive transistor Trd in a state where the video signal Vsig is sampled, and negatively feeds back the output current Ids, so as to correct the input voltage Vgs.

(24) FIG. 3 is a schematic view of the part of the pixel circuit 2 in the display apparatus illustrated in FIG. 2. For easy understanding, the video signal Vsig sampled by the sampling transistor Tr1, the input voltage Vsig and the output current Ids of the drive transistor Trd, and furthermore, a capacitor component Coled held by the light-emitting device EL, are also shown. Also, the scan lines WS, DS, and AZ connected to the gates of the respective transistors are shown. This pixel circuit 2 performs a Vth correcting operation and a video signal writing operation during the horizontal scanning period. Accordingly, the pixel circuit 2 can be constituted by the four transistors Tr1, Tr3, Tr4, and Trd, the one pixel capacitor Cs, and the one light-emitting device EL. Compared to the conventional pixel circuit having a Vth correcting function, at least one transistor can be reduced. Accordingly, at least one power-supply line and one gate line (scan line) can be reduced, which leads to improvement in yield of panels. Also, simplified layout of the pixel circuit enables higher resolution.

(25) FIG. 4 is a timing chart of the pixel circuit illustrated in FIGS. 2 and 3. An operation of the pixel circuit illustrated in FIGS. 2 and 3 is specifically described in detail with reference to FIG. 4. FIG. 4 illustrates the waveforms of control signals applied to the respective scan lines WS, AZ, and DS, along a time axis T. In order to simplify the illustration, each control signal is indicated with the same code as that of the corresponding scan line. Also, the waveform of the video signal Vsig applied to the signal line is illustrated along the time axis T. As illustrated in the figure, the video signal Vsig is at the certain potential Vss0 in the first half of each horizontal scanning period H, and is at a signal potential in the latter half. The transistors Tr1 and Tr3 are N-channel transistors, and are thus turned ON when the scan lines WS and AZ are in a high level and are turned OFF in a low level. On the other hand, the transistor Tr4 is a P-channel transistor, and is thus turned OFF when the scan line DS is in a high level and is turned ON in a low level. Also, this timing chart illustrates changes in potential of the gate G and source S of the drive transistor Trd, together with the waveforms of the respective control signals WS, AZ, and DS and the waveform of the video signal Vsig.

(26) In the timing chart in FIG. 4, timings T1 to T8 correspond to one field (1f). The respective rows of the pixel array are sequentially scanned once during the one field. The timing chart illustrates the waveforms of the respective control signals WS, AZ, and DS that are applied to the pixels of one row.

(27) At timing T0 before the field starts, all the control signals WS, AZ, and DS are in a low level. Thus, the N-channel transistors Tr1 and Tr3 are in an OFF state, whereas only the P-channel transistor Tr4 is in an ON state. Thus, the drive transistor Trd connects to the power supply Vcc via the ON-state transistor Tr4, and thus supplies the output current Ids to the light-emitting device EL in accordance with the predetermined input voltage Vgs. Thus, the light-emitting device EL emits light at timing T0. The input voltage Vgs applied to the drive transistor Trd at this time is expressed by a difference between a gate potential (G) and a source potential (S).

(28) At timing T1 when the field starts, the control signal DS is switched from a low level to a high level. Accordingly, the transistor Tr4 is turned OFF and the drive transistor Trd is disconnected from the power supply Vcc, so that light emission stops to enter a non-light-emitting period. At timing T1, all the transistors Tr1, Tr3, and Tr4 are brought into an OFF state.

(29) Then, at timing T2, the control signal AZ rises from a low level to a high level, and the switching transistor Tr3 is turned ON. Accordingly, the reference potential Vss is written in the other end of the pixel capacitor Cs and the source S of the drive transistor Trd. At this time, the gate potential of the drive transistor Trd is high impedance, and thus the gate potential (G) drops in accordance with a drop of the source potential (S).

(30) After that, the control signal AZ returns to a low level and the switching transistor Tr3 is turned OFF. Then, at timing Ta, the control signal WS becomes a high level and the sampling transistor Tr1 is brought into conduction. At this time, the potential that appears in the signal line is set to the predetermined certain potential Vss0. Here, Vss0 and Vss are set so that Vss0−Vss>Vth is satisfied. Vss0−Vss is the input voltage Vgs of the drive transistor Trd. Here, Vgs>Vth is realized as preparation for the Vth correcting operation performed thereafter. In other words, at timing Ta, the both ends of the pixel capacitor Cs are set at a voltage exceeding Vgs, and the pixel capacitor Cs is reset prior to the Vth correcting operation. Furthermore, by setting VthEL>Vss, wherein VthEL is a threshold voltage of the light-emitting device EL, a reverse bias is applied to the light-emitting device EL. This is necessary for normally performing the Vth correcting operation thereafter.

(31) Then, at timing T3, the control signal DS is switched to a low level, the switching transistor Tr4 is turned ON, and Vth correction is performed. At this time, the potential of the signal line is still held at the certain potential Vss0 in order to accurately perform Vth correction. Turn ON of the switching transistor Tr4 causes the drive transistor Trd to be connected to the power supply Vcc, inducing flow of the output current Ids. Accordingly, the pixel capacitor Cs is charged, and the source potential (S) connected to the other end thereof rises. On the other hand, the potential (gate potential G) of one end of the pixel capacitor Cs is fixed to Vss0. Thus, the source potential (S) rises in accordance with the charge of the pixel capacitor Cs, and the drive transistor Trd is cut off when the input voltage Vgs reaches just Vth. When the drive transistor Trd is cut off, the source potential (S) thereof becomes Vss0−Vth, as illustrated in the timing chart.

(32) Then, at timing T4, the control signal DS is returned to a high level and the switching transistor Tr4 is turned OFF, so that the Vth correcting operation ends. With this correcting operation, a voltage corresponding to the threshold voltage Vth is written in the pixel capacitor Cs.

(33) In this way, Vth correction is performed from timing T3 to timing T4, when half of one horizontal scanning period (1H) elapses, and then the potential of the signal line changes from Vss0 to Vsig. Accordingly, the video signal Vsig is written in the pixel capacitor Cs. The pixel capacitor Cs is sufficiently small compared to the equivalent capacitor Coled of the light-emitting device EL. As a result, a most part of the video signal Vsig is written in the pixel capacitor Cs. Therefore, the voltage Vgs between the gate G and source S of the drive transistor Trd becomes a level of the sum of Vth that was previously detected and held and Vsig that is sampled this time (Vsig+Vth). The gate-source voltage Vgs becomes Vsig+Vth, as illustrated in the timing chart in FIG. 4. Sampling of the video signal Vsig continues until timing T7, when the control signal WS returns to a low level. That is, timing T5 to timing T7 correspond to the sampling period.

(34) As described above, in the present invention, the Vth correcting period T3-T4 and the sampling period T5-T7 are included in one horizontal scanning period (1H). During 1H, the control signal WS for sampling is in a high level. In the present invention, Vth correction and Vsig writing are performed in a state where the sampling transistor Tr1 is in an ON state. Accordingly, the configuration of the pixel circuit 2 is simplified.

(35) In this embodiment, correction of the mobility μ is performed at the same time in addition to the above-described Vth correction. However, the present invention is not limited to this, but of course can be applied to a pixel circuit not performing mobility μ correction but performing only a simple Vth correcting operation. Also, in the pixel circuit 2 according to this embodiment, N-channel and P-channel transistors are used as the transistors other than the drive transistor Trd. However, the present invention is not limited to this, but the transistors may be constituted by only N-channel transistors or only P-channel transistors.

(36) Correction of the mobility μ is performed from timing T6 to timing T7. Hereinafter, this point is described in detail. The control signal DS becomes a low level and the switching transistor Tr4 is turned ON at timing T6, before timing T7 when the sampling period ends. Accordingly, the drive transistor Trd is connected to the power supply Vcc, and thus the pixel circuit enters a light-emitting period from a non-light-emitting period. In this way, mobility correction of the drive transistor Trd is performed in the period T6-T7 when the sampling transistor Tr1 is still in an ON state and the switching transistor Tr4 has entered an ON state. That is, in this embodiment, mobility correction is performed in the period T6-T7 when an end part of the sampling period and a head part of the light-emitting period overlap each other. Note that, at the head of the light-emitting period when the mobility correction is performed, the light-emitting device EL is in a reverse bias state and thus does not emit light. In this mobility correcting period T6-T7, a drain current Ids flows in the drive transistor Trd in a state where the gate G of the drive transistor Trd is fixed to the level of the video signal Vsig. Here, the setting of Vss0−Vth<VthEL allows the light-emitting device EL to be in a reverse bias state, thereby having a simple capacitance characteristic instead of a diode characteristic. Thus, the current Ids flowing in the drive transistor Trd is written into a capacitor C=Cs+Coled, which is a combination of the pixel capacitor Cs and the equivalent capacitor Coled of the light-emitting device EL. Accordingly, the source potential (S) of the drive transistor Trd rises. This rise is represented by ΔV in the timing chart in FIG. 4. This rise ΔV is eventually subtracted from the gate-source voltage Vgs held in the pixel capacitor Cs, which is equivalent to negative feedback. In this way, by negatively feeding back the output current Ids of the drive transistor Trd to the input voltage Vgs of the drive transistor Trd, the mobility μ can be corrected. Note that the negative feedback amount ΔV can be optimized by adjusting a time width t of the mobility correcting period T6-T7.

(37) At timing T7, the control signal WS becomes a low level and the sampling transistor Tr1 is turned OFF. As a result, the gate G of the drive transistor Trd is disconnected from the signal line SL. Since application of the video signal Vsig stops, the gate potential (G) of the drive transistor Trd can rise and rises with the source potential (S). During that time, the gate-source voltage Vgs held in the pixel capacitor Cs maintains a value of (Vsig−ΔV+Vth). With the rise of the source potential (S), the reverse bias state of the light-emitting device EL is canceled, and thus inflow of the output current Ids causes the light-emitting device EL to actually start light emission. At this time, the relationship between the drain current Ids and the gate voltage Vgs can be given as expressed in the following expression 2 by substituting Vsig−ΔV+Vth into Vgs in the above transistor characteristic expression 1.
Ids=kμ(Vgs−Vth).sup.2=kμ(Vsig−ΔV).sup.2  expression 2

(38) In the above expression 2, k=(½) (W/L)Cox. The term of Vth is canceled from this characteristic expression 2, and it is understood that the output current Ids supplied to the light-emitting device EL does not depend on the threshold voltage Vth of the drive transistor Trd. Basically, the drain current Ids is determined by the signal voltage Vsig of the video signal. In other words, the light-emitting device EL emits light at brightness in accordance with the video signal Vsig. At that time, Vsig is corrected with the feedback amount ΔV. This correction amount ΔV acts to cancel the effect of the mobility μ positioned at a coefficient part of the characteristic expression 2. Thus, the drain current Ids substantially depends on only the video signal Vsig.

(39) Finally, at timing T8, the control signal DS becomes a high level, the switching transistor Tr4 is turned OFF, and light emission ends and also the field ends. Then, the next field starts and the Vth correcting operation, the mobility correcting operation, and the light emitting operation are repeated again.

(40) FIG. 5 is a circuit diagram illustrating a state of the pixel circuit 2 in the mobility correcting period T6-T7. As illustrated in the figure, in the mobility correcting period T6-T7, the sampling transistor Tr1 and the switching transistor Tr4 are in an ON state, whereas the other switching transistor Tr3 is in an OFF state. In this state, the source potential (S) of the drive transistor Tr4 is Vss0−Vth. This source potential S is an anode potential of the light-emitting device EL. As described above, setting of Vss0−Vth<VthEL allows the light-emitting device EL to be in a reverse bias state and to have a simple capacitance characteristic instead of a diode characteristic. Accordingly, the current Ids flowing in the drive transistor Trd flows into the composite capacitor C=Cs+Coled of the pixel capacitor Cs and the equivalent capacitor Coled of the light-emitting device EL. In other words, part of the drain current Ids is negatively fed back to the pixel capacitor Cs, so that correction of the mobility is performed.

(41) FIG. 6 is a graph illustrating the above-described transistor characteristic expression 2, in which the vertical axis indicates Ids and the horizontal axis indicates Vsig. The characteristic expression 2 is also shown under the graph. The graph in FIG. 6 shows characteristic curves comparing pixels 1 and 2. The mobility μ of the drive transistor of pixel 1 is relatively high. On the other hand, the mobility μ of the drive transistor included in pixel 2 is relatively low. In this way, when the drive transistor is made of a polysilicon thin film transistor or the like, it is inevitable that the mobility μ varies among pixels. For example, when a video signal Vsig of the same level is written in both pixels 1 and 2 and when any mobility correction is not performed, a significant difference occurs between an output current Ids1′ flowing in pixel 1 having the high mobility μ and an output current Ids2′ flowing in pixel 2 having the low mobility μ. In this way, a significant difference in output current Ids occurs due to variations in mobility μ, so that uniformity of the screen is impaired.

(42) In the present invention, the variations in mobility are canceled by negatively feeding back an output current to the side of an input voltage. As is clear from the transistor characteristic expression, a high mobility results in a large drain current Ids. Thus, the negative feedback amount ΔV is larger as the mobility is higher. As illustrated in the graph in FIG. 6, a negative feedback amount ΔV1 of pixel 1, having a high mobility μ, is larger than a negative feedback amount ΔV2 of pixel 2, having a low mobility. Thus, a larger amount of negative feedback is applied as the mobility μ is higher, and variations can be suppressed. As illustrated in the figure, when correction of ΔV1 is applied in pixel 1 having a high mobility μ, the output current significantly drops from Ids1′ to Ids1. On the other hand, the correction amount ΔV2 in pixel 2 having a low mobility μ is small, and thus the output current Ids2′ does not so significantly drop to Ids2. As a result, Ids1 and Ids2 become almost equal to each other, and variations in mobility are canceled. The cancellation of variations in mobility is performed in an entire range of Vsig from a black level to a white level, so that very high uniformity of the screen can be obtained. In summary, when pixels 1 and 2 having different mobilities exist, the correction amount ΔV1 of pixel 1 having a high mobility is smaller than the correction amount ΔV2 of pixel 2 having a low mobility. That is, as the mobility is larger, ΔV is larger and a decrease value of Ids is larger. Accordingly, current values of pixels having different mobilities are uniformed, and variations in mobility can be corrected.

(43) Hereinafter, numeric analysis of the above-described mobility correction is performed for reference, with reference to FIG. 7. As illustrated in FIG. 7, analysis is performed by using the source potential of the drive transistor Trd as a variable V, in a state where the transistors Tr1 and Tr4 are in an ON state. Regarding the source potential (S) of the drive transistor Trd as V, the drain current Ids flowing in the drive transistor Trd is expressed by the following expression 3.

(44) [Equation 1]
I.sub.ds=kμ(V.sub.gs−V.sub.th).sup.2=kμ(V.sub.sig−V−V.sub.th).sup.2  expression 3

(45) Also, based on the relationship between the drain current Ids and the capacitor C (=Cs+Coled), Ids=dQ/dt=CdV/dt is satisfied as shown in the following expression 4.

(46) $\begin{array}{cc}\left[\mathrm{Equation}2\right]& \\ I_{\mathrm{ds}}=\frac{\mathrm{dQ}}{\mathrm{dt}}=C\frac{\mathrm{dV}}{\mathrm{dt}}\mathrm{thereby}\int \frac{1}{C}\mathrm{dt}=\int \frac{1}{I_{\mathrm{ds}}}\mathrm{dV}\iff {\int }_0^t\frac{1}{C}\mathrm{dt}={\int }_{-\mathrm{Vth}}^V\frac{1}{k{\mu \left(V_{\mathrm{sig}}-V_{\mathrm{th}}-V\right)}^2}\mathrm{dV}\iff \frac{k\mu }{C}t={\left[\frac{1}{V_{\mathrm{sig}}-V_{\mathrm{th}}-V}\right]}_{-\mathrm{Vth}}^V=\frac{1}{V_{\mathrm{sig}}-V_{\mathrm{th}}-V}-\frac{1}{V_{\mathrm{sig}}}\iff V_{\mathrm{sig}}-V_{\mathrm{th}}-V=\frac{1}{\frac{1}{V_{\mathrm{sig}}}+\frac{k\mu }{C}t}=\frac{V_{\mathrm{sig}}}{1+V_{\mathrm{sig}}\frac{k\mu }{C}t}& \mathrm{expression}4\end{array}$

(47) Expression 3 is substituted into expression 4, and both sides are integrated. Here, assume that the initial state of the source voltage V is −Vth and that the mobility variation correcting time (T6-T7) is t. By solving this differential equation, a pixel current for the mobility correcting time t can be given as in the following expression 5.

(48) $\begin{array}{cc}\left[\mathrm{Equation}3\right]& \\ I_{\mathrm{ds}}=k{\mu \left(\frac{V_{\mathrm{sig}}}{1+V_{\mathrm{sig}}\frac{k\mu }{C}t}\right)}^2& \mathrm{expression}5\end{array}$

(49) FIG. 8 is a graph illustrating expression 5, in which the vertical axis indicates the output current Ids and the horizontal axis indicates the video signal Vsig. As a parameter, cases where the mobility correcting period t=0 us, 2.5 us, and 5 us are set. Furthermore, the mobility μ is used as a parameter, which is relatively high of 1.2μ or relatively low of 0.8μ. It can be understood that, compared to a case where the mobility is not substantially corrected in t=0 us, variations in mobility can be sufficiently corrected when t=2.5 us. Ids has a 40% variation with no correction of mobility, whereas the variation can be suppressed to 10% or less by performing mobility correction. However, if the correcting period is long in t=5 us, variations in output current Ids become significant due to a difference in mobility μ. In this way, t needs to be set to an optimal value in order to perform an appropriate mobility correction. In the graph illustrated in FIG. 8, the optimal value is around t=2.5 us.

(50) Next, a second embodiment of the pixel circuit according to the present invention is described. In the above-described first embodiment, Vth correction and Vsig writing are performed within one horizontal scanning period (1H), as illustrated in the timing chart in FIG. 4. Accordingly, the number of circuit elements is reduced. However, in the pixel circuit according to the first embodiment, when the resolution is high with a larger number of pixels in the panel or when a field frequency is high for high image quality, the horizontal scanning period (1H) is short, and thus it is possible that Vth correction cannot sufficiently be performed. On the other hand, if a certain Vth correcting period is ensured, the Vsig writing period is squeezed, and it is possible that a video signal cannot sufficiently be written in the pixel capacitor. The second embodiment is made by improving the first embodiment, and can deal with higher resolution and higher quality of the panel. The configuration of the pixel circuit according to the second embodiment is basically the same as that of the pixel circuit according to the first embodiment illustrated in FIG. 2. However, the operation sequence thereof is different, which is described in detail with reference to the timing chart in FIG. 9. For easy understanding, parts corresponding to those in the timing chart in FIG. 4 illustrating the operation of the first embodiment are denoted by corresponding reference numerals.

(51) As is clear from referring to FIG. 9, the Vth correcting period is divided into a plurality of periods in this embodiment. Accordingly, although each Vth correcting period is short, a sufficiently long Vth correcting period can be ensured by performing the correction plural times. This enables reduction of the number of circuit elements and dealing with higher resolution and higher frequency of the panel. Each Vth correcting period is very short of several μs, but a total correction amount of the plural times enables sufficient correction of variations in Vth.

(52) Hereinafter, the operation of the second embodiment is described in detail with reference to the timing chart in FIG. 9. First, at timing T1, the control signal DS is allowed to be in a high level and the switching transistor Tr4 is turned OFF. Then, at timing T2, the control signal AZ is allowed to be in a high level and the switching transistor Tr3 is turned ON. Accordingly, the reference potential Vss is written in the source potential (S) of the drive transistor Trd. At this time, the gate potential (G) is high impedance, so that the gate potential (G) drops in accordance with a drop of the source potential (S).

(53) After that, Vth correction is performed in a timesharing manner in horizontal blanking periods to delimit the respective horizontal scan lines. In each horizontal blanking period, the potential of the signal line is set to the certain potential Vss0. In a first Vth correcting period, the control signal WS becomes a high level and the sampling transistor is turned ON. At this time, the potential of the signal line is set to Vss0, as described above. Here, Vss0−Vss=Vgs>Vth is satisfied, and Vgs>Vth allows preparation for subsequent Vth correction. Also, when the threshold voltage of the light-emitting device EL is VthEL, setting of VthEL>Vss allows a reverse bias to be applied to the light-emitting device EL. This is necessary to normally perform the subsequent Vth correcting operation and the mobility correcting operation.

(54) Then, while keeping the sampling transistor in an ON state, the control signal DS is switched to a low level and the switching transistor Tr4 is turned ON at timing T31. Accordingly, the first Vth correction is performed. At this time, the potential of the signal line is held at the certain potential Vss0 in order to accurately perform Vth correction. Turn ON of the switching transistor Tr4 causes the drive transistor Trd to output the output current Ids toward cut off. Then, at timing T41, the control signal DS is returned to a high level, the switching transistor Tr4 is turned OFF, and the first Vth correction ends. Then, it is desirable that the control signal WS is returned to a low level before the potential of the signal line changes and the sampling transistor is turned OFF. However, even if that operation is not performed, no problem occurs in the operation.

(55) In this embodiment, each Vth correcting period is set to be within the horizontal blanking period. Thus, in one Vth correcting operation, the drive transistor Trd is not cut off and the source potential (S) thereof is held at a mid operation point.

(56) When the potential of the signal line becomes Vss0 again in the next horizontal blanking period, a second Vth correcting operation is performed. That is, WS is switched to a high level so as to bring the sampling transistor Tr1 into conduction. Also, the control signal DS is switched to a low level so as to bring the switching transistor Tr4 into conduction. Accordingly, the second Vth correcting operation is performed. The second Vth correcting period is represented by T32-T42. By performing the series of Vth correcting operation a plurality of times until the drive transistor is cut off, Vth correction is completed.

(57) In the example illustrated in the timing chart in FIG. 9, a third Vth correction is performed in the horizontal blanking period positioned at the head of the horizontal scanning period (1H) assigned to the scan line WS, and then the video signal Vsig is written in the pixel capacitor, and then the mobility μ is corrected. The third Vth correcting period is represented by T33-T43. After the third Vth correction has completed, the difference between the gate potential (G) and the source potential (S) is set to just Vth.

(58) As described above, in this embodiment, the correcting means incorporated in the pixel circuit 2 operates in a plurality of horizontal scanning periods assigned to a plurality of scan lines and charges the pixel capacitor Cs to the threshold voltage Vth in a timesharing manner. The sampling transistor samples the video signal supplied from the signal line SL to the pixel capacitor Cs during a signal supplying period when the signal line SL is at the potential Vsig of the video signal in the horizontal scanning period (1H) assigned to the scan line WS. On the other hand, the correcting means detects the threshold voltage Vth of the drive transistor Trd and charges the pixel capacitor Cs to the threshold voltage Vth in a timesharing manner during a signal fixed period when the signal line SL is at the certain potential Vss0 in each of the horizontal scanning periods assigned to the plurality of scan lines WS. This signal fixed period is a horizontal blanking period to delimit the respective horizontal scanning periods that are sequentially assigned to the respective scan lines WS. The correcting means charges the pixel capacitor Cs to the threshold voltage Vth in a timesharing manner in each horizontal blanking period. Preferably, after the correcting means has charged the pixel capacitor Cs in each signal fixed period, the sampling transistor Tr1 should be closed and the pixel capacitor Cs should be electrically disconnected from the signal line SL before the signal line SL is switched from the certain potential Vss0 to the potential Vsig of the video signal.

(59) FIG. 10 is a schematic block diagram illustrating a display apparatus according to a third embodiment of the present invention. For easy understanding, parts corresponding to those of the display apparatus according to the first embodiment illustrated in FIG. 1 are denoted by corresponding reference numerals. The different point is that the pixel array 1 according to the third embodiment includes two types of scan lines WS and DS so as to further reduce the gate lines, whereas the three types of scan lines (gate lines) WS, DS, and AZ are provided in the first embodiment. Specifically, the scan lines AZ are not provided. Instead of the scan line AZ of this stage, the scan line WS of the preceding stage is used. Accordingly, the gate lines can be reduced by one type and also a correcting scanner is not required.

(60) FIG. 11 schematically illustrates two pixel circuits, one in the preceding stage and the other in this stage, among the pixel circuits included in the pixel array of the display apparatus illustrated in FIG. 10. The configuration of the respective pixel circuits 2 is basically similar to that of the first embodiment illustrated in FIG. 2, and corresponding parts are denoted by corresponding reference numerals. Each pixel circuit 2 includes the sampling transistor Tr1, the drive transistor Trd, the first switching transistor Tr3, the second switching transistor Tr4, the pixel capacitor Cs, and the light-emitting device EL. The different point is that the scan line WS of the preceding stage connects to the gate of the first switching transistor Tr3. However, the pixel circuit 2 of the first stage does not have the scan line WS of the preceding stage, and thus another supply is required.

(61) FIG. 12 is a schematic view illustrating one pixel circuit in the pixel array illustrated in FIG. 11. For easy understanding, the video signal Vsig sampled by the sampling transistor Tr1, the input voltage Vgs and the output current Ids of the drive transistor Trd, and also the capacitor component Coled held by the light-emitting device EL are shown. Also, the scan line of this stage connected to the gate of the sampling transistor Tr1 is represented by WSn, the scan line of the preceding stage connected to the gate of the first switching transistor Tr3 is represented by WSn−1, and the scan line connected to the gate of the second switching transistor Tr4 is represented by DS.

(62) FIG. 13 is a timing chart illustrating an operation of the pixel circuit illustrated in FIG. 12. For easy understanding, parts corresponding to those in the timing chart of the first embodiment illustrated in FIG. 4 are denoted by corresponding reference numerals. This timing chart illustrates the waveforms of control signals applied to the respective scan lines WSn, WSn−1, and DS along the time axis T. For simple illustration, the control signals are represented by the same codes as those of the corresponding scan lines. Also, this timing chart illustrates changes in potential of the gate G and source S of the drive transistor Trd and the waveform of the video signal Vsig applied to the signal line, together with the waveforms of the respective control signals WSn, WSn−1, and DS. As illustrated in the figure, the video signal Vsig is fixed to the certain potential Vss0 in the first half of each horizontal scanning period and is at the video signal potential in the latter half. At timing T1, the control signal DS becomes a high level, the switching transistor Tr4 is turned OFF, and the pixel circuit enters a non-light-emitting state. At timing T2, the control signal WSn−1 of the preceding stage becomes a high level and the switching transistor Tr3 is turned ON. Accordingly, the pixel capacitor Cs is reset and Vgs>Vth is set. That is, a preparing operation for Vth correction is performed. At timing Ta, the control signal WSn of this stage rises to a high level and the sampling transistor Tr1 is brought into conduction. Then, at timing T3, the control signal DS becomes a low level and the second switching transistor Tr4 is turned ON. Accordingly, the pixel capacitor Cs is charged to write Vth in a state where one end of the pixel capacitor Cs is fixed to the certain potential Css0. That is, a Vth correcting operation is performed. Then, at timing T5, the video signal Vsig is written in the pixel capacitor Cs. Furthermore, at timing T6, an operation of correcting the mobility μ is performed and a light-emitting state starts.

(63) As described above, the third embodiment is provided with the correcting means for detecting the threshold voltage Vth of the drive transistor Trd and writing it in the pixel capacitor Cs in order to cancel the dependency of the output current Ids on the threshold voltage Vth. This correcting means includes the first switching transistor Tr3 and the second switching transistor Tr4. The first switching transistor Tr3 is brought into conduction in response to a control signal WSn−1 supplied from another scan line WSn−1, positioned before the scan line WSn of this stage, during the preceding horizontal scanning period assigned to the other scan line WSn−1, whereby setting is made so that the potential difference across the pixel capacitor Cs exceeds the threshold voltage Vth. The second switching transistor Tr4 is brought into conduction in the horizontal scanning period (1H) assigned to this stage and charges the pixel capacitor Cs until the potential difference (Vgs) across the pixel capacitor Cs becomes the threshold voltage Vth. In the embodiment illustrated in FIG. 13, the scan line WSn−1 positioned immediately before the scan line WSn of this stage is used as the scan line of the preceding stage. In some cases, a scan line WSn−2 before the scan line WSn−1 or a scan line before the scan line WSn−2 can be used as the gate line of the first switching transistor Tr3, instead of the scan line WSn−1. In this way, in this embodiment, the scan line WS is shared by two pixels and thus the gate lines can be reduced by one type. This leads to improvement of yield of panels. Also, simplified layout enables higher resolution of the panel.

(64) FIG. 14 is a block diagram illustrating a reference example of the pixel circuit. For easy understanding, parts corresponding to those of the first embodiment illustrated in FIG. 2 are denoted by corresponding reference numerals. The different point is that, in this reference example, the Vth correcting operation is performed before the horizontal scanning period. For this reason, a switching transistor Tr2 is necessary in addition to the switching transistor Tr3 for preparation for Vth correction. The one transistor Tr3 resets a source-side terminal of the pixel capacitor Cs, whereas the additional transistor Tr2 resets a gate-side terminal of the pixel capacitor Cs. In order to drive the additional switching transistor Tr2, an additional scan line AZ1 and an additional correcting scanner 71 is necessary. In the present invention, setting of the gate-side terminal of the pixel capacitor Cs is performed in the horizontal scanning period, so that the transistor Tr2 is unnecessary. The transistor Tr2 writes a power supply voltage Vss1 in the gate G. On the other hand, in the present invention, the fixed potential Vss0 supplied from the signal line SL is written during the horizontal scanning period.

(65) Hereinafter, an operation according to the reference example illustrated in FIG. 14 is described. This active matrix display apparatus includes a pixel array 1 serving as a main unit and a peripheral circuit unit. The peripheral circuit unit includes a horizontal selector 3, a write scanner 4, a drive scanner 5, the first correcting scanner 71, a second correcting scanner 72, and so on. The pixel array 1 includes scan lines WS in rows, signal lines SL in columns, and pixel circuits 2 arranged in a matrix pattern at parts where the both lines cross each other. In the figure, only one pixel circuit 2 is illustrated by enlarging it for easy understanding. The signal lines SL are driven by the horizontal selector 3. The horizontal selector 3 constitutes a signal unit and supplies video signals to the signal lines SL. The scan lines WS are scanned by the write scanner 4. Also, other scan lines DS, AZ1, and AZ2 are provided in parallel with the scan lines WS. The scan lines DS are scanned by the drive scanner 5. The scan lines AZ1 are scanned by the first correcting scanner 71. The scan lines AZ2 are scanned by the second correcting scanner 72. The write scanner 4, the drive scanner 5, the first correcting scanner 71, and the second correcting scanner 72 constitute a scanner unit and sequentially scan rows of pixels in each horizontal period. Each pixel circuit 2 samples a video signal from the signal line SL when selected by the scan line WS. Furthermore, the pixel circuit 2 drives the light-emitting device EL included in the pixel circuit 2 in response to the sampled video signal when selected by the scan line DS. In addition, the pixel circuit 2 performs a predetermined correcting operation when being scanned by the scan lines AZ1 and AZ2.

(66) The pixel circuit 2 includes five thin film transistors Tr1 to Tr4 and Trd, one capacitor element (pixel capacitor) Cs, and one light-emitting device EL. The transistors Tr1 to Tr3 and Trd are N-channel polysilicon TFTs. Only the transistor Tr4 is a P-channel polysilicon TFT. The capacitor element Cs constitutes a capacitor unit of the pixel circuit 2. The light-emitting device EL is a diode-type organic EL device including an anode and a cathode, for example.

(67) In the drive transistor Trd, serving as a main element of the pixel circuit 2, the gate G thereof connects to one end of the pixel capacitor Cs and the source S thereof connects to the other end of the pixel capacitor Cs. Also, the gate G of the drive transistor Trd connects to another reference potential Vss1 via the switching transistor Tr2. The drain of the drive transistor Trd connects to a power supply Vcc via the switching transistor Tr4. The gate of the switching transistor Tr2 connects to the scan line AZ1. The gate of the switching transistor Tr4 connects to the scan line DS. The anode of the light-emitting device EL connects to the source S of the drive transistor Trd, and the cathode is grounded. This ground potential may be represented by Vcath. Also, the switching transistor Tr3 exists between the source S of the drive transistor Trd and a predetermined reference potential Vss2. The gate of the transistor Tr3 connects to the scan line AZ2. On the other hand, the sampling transistor Tr1 is connected between the signal lines SL and the gate G of the drive transistor Trd. The gate of the sampling transistor Tr1 connects to the scan line WS.

(68) In this configuration, the sampling transistor Tr1 is brought into conduction in response to a control signal WS supplied from the scan line WS and samples a video signal Vsig supplied from the signal line SL to the capacitor unit Cs during a predetermined sampling period. The capacitor unit Cs applies an input voltage Vgs between the gate G and source S of the drive transistor in response to the sampled video signal Vsig. The drive transistor Trd supplies an output current Ids in accordance with the input voltage Vgs to the light-emitting device EL during a predetermined light-emitting period. Note that the output current (drain current) Ids has dependency on carrier mobility μ and a threshold voltage Vth in a channel region of the drive transistor Trd. The light-emitting device EL emits light at brightness in accordance with the video signal Vsig by the output current Ids supplied from the drive transistor Trd.

(69) The pixel circuit 2 includes correcting means including the switching transistors Tr2 to Tr4, and corrects the input voltage Vgs held in the capacitor unit Cs in advance at the head of a light-emitting period in order to cancel the dependency of the output current Ids on the carrier mobility μ. Specifically, the connecting means (Tr2 to Tr4) operates in part of the sampling period in response to control signals WS and DS supplied from the scan lines WS and DS, takes the output current Ids from the drive transistor Trd in a state where the video signal Vsig is sampled, and negatively feeds back the output current Ids to the capacitor unit Cs, so as to correct the input voltage Vgs. Furthermore, this correcting means (Tr2 to Tr4) detects the threshold voltage Vth of the drive transistor Trd prior to the sampling period and adds the detected threshold voltage Vth to the input voltage Vgs in order to cancel the dependency of the output current Ids on the threshold voltage Vth.

(70) The drive transistor Trd is an N-channel transistor. The drain thereof connects to the power supply Vcc side, whereas the source S connects to the light-emitting device EL side. In this case, the above-described correcting means takes the output current Ids from the drive transistor Trd and negatively feeds back the output current Ids to the capacitor unit Cs side at a head part of the light-emitting period that overlaps a latter part of the sampling period. At that time, the correcting means allows the output current Ids, taken from the source S side of the drive transistor Trd at the head part of the light-emitting period, to flow into the capacitor held by the light-emitting device EL. Specifically, the light-emitting device EL is a diode-type light-emitting device including an anode and a cathode. The anode side connects to the source S of the drive transistor Trd, whereas the cathode side is grounded. In this configuration, the correcting means (Tr2 to Tr4) sets between the anode and cathode of the light-emitting device EL to a reverse bias state in advance, and allows the diode-type light-emitting device EL to function as a capacitor element when the output current Ids taken from the source S side of the drive transistor Trd flows into the light-emitting device EL. Also, the correcting means can adjust a time width t, when the output current Ids is taken from the drive transistor Trd, in the sampling period, thereby optimizing a negative feedback amount of the output current Ids to the capacitor unit Cs.

(71) FIG. 15 is a schematic view illustrating the part of the pixel circuit in the display apparatus illustrated in FIG. 14. For easy understanding, the video signal Vsig sampled by the sampling transistor Tr1, the input voltage Vgs and the output current Ids of the drive transistor Trd, and also the capacitor component Coled held by the light-emitting device EL are shown. Hereinafter, a basic operation of the pixel circuit 2 is described based on FIG. 15.

(72) FIG. 16 is a timing chart of the pixel circuit illustrated in FIG. 15. The operation of the pixel circuit illustrated in FIG. 15 is specifically described in detail with reference to FIG. 16. FIG. 16 illustrates the waveforms of control signals applied to the respective scan lines WS, AZ1, AZ2, and DS along a time axis T. For simplifying the illustration, the control signals are represented by the same codes as those of the corresponding scan lines. The transistors Tr1, Tr2, and Tr3, which are N-channel transistors, are turned ON when the scan lines WS, AZ1, and AZ2 are in a high level and are turned OFF in a low level. On the other hand, the transistor Tr4, which is a P-channel transistor, is turned OFF when the scan line DS is in a high level and is turned ON in a low level. Also, this timing chart illustrates changes in potential of the gate G and source S of the drive transistor Trd, together with the waveforms of the respective control signals WS, AZ1, AZ2, and DS.

(73) In the timing chart in FIG. 16, timings T1 to T8 correspond to one field (1f). The respective rows of the pixel array are sequentially scanned once during the one field. The timing chart illustrates the waveforms of the respective control signals WS, AZ1, AZ2, and DS that are applied to the pixels of one row.

(74) At timing T0 before the field starts, all the control signals WS, AZ1, AZ2, and DS are in a low level. Thus, the N-channel transistors Tr1, Tr2, and Tr3 are in an OFF state, whereas only the P-channel transistor Tr4 is in an ON state. Thus, the drive transistor Trd connects to the power supply Vcc via the ON-state transistor Tr4, and thus supplies the output current Ids to the light-emitting device EL in accordance with the predetermined input voltage Vgs. Thus, the light-emitting device EL emits light at timing T0. The input voltage Vgs applied to the drive transistor Trd at this time is represented by a difference between a gate potential (G) and a source potential (S).

(75) At timing T1 when the field starts, the control signal DS is switched from a low level to a high level. Accordingly, the transistor Tr4 is turned OFF and the drive transistor Trd is disconnected from the power supply Vcc, so that light emission stops to enter a non-light-emitting period. Therefore, at timing T1, all the transistors Tr1 to Tr4 are brought into an OFF state.

(76) Then, at timing T2, the control signals AZ1 and AZ2 become a high level, so that the switching transistors Tr2 and Tr3 are turned ON. As a result, the gate G of the drive transistor Trd is connected to the reference potential Vss1, and the source S is connected to the reference potential Vss2. Here, Vss1−Vss2>Vth is satisfied. By setting Vss1−Vss2=Vgs>Vth, a preparation for Vth correction performed at timing T3 is performed. In other words, the period T2-T3 corresponds to a reset period of the drive transistor Trd. Also, when the threshold voltage of the light-emitting device EL is represented by VthEL, VthEL>Vss2 is set. Accordingly, a minus bias is applied to the light-emitting device EL and a so-called reverse bias state occurs. This reverse bias state is necessary for normally performing a Vth correcting operation and a mobility correcting operation later.

(77) Just before timing T3, the control signal AZ2 is allowed to be in a low level. Also, at timing T3, the control signal DS is allowed to be in a low level. Accordingly, the transistor Tr3 is turned OFF, whereas the transistor Tr4 is turned ON. As a result, the drain current Ids flows into the pixel capacitor Cs and the Vth correcting operation starts. At this time, the gate G of the drive transistor Trd is held at Vss1, and the current Ids flows until the drive transistor Trd is cut off. After the cut off, the source potential (S) of the drive transistor Trd becomes Vss1−Vth. At timing T4 after the drain current is cut off, the control signal DS is returned to a high level and the switching transistor Tr4 is turned OFF. Furthermore, the control signal AZ1 is returned to a low level and the switching transistor Tr2 is turned OFF. As a result, Vth is held and fixed in the pixel capacitor Cs. As described above, timing T3-T4 is a period to detect the threshold voltage Vth of the drive transistor Trd. Here, this detecting period T3-T4 is called a Vth correcting period.

(78) At timing T5 after Vth correction has been performed in the above-described manner, the control signal WS is switched to a high level, the sampling transistor Tr1 is turned ON, and the video signal Vsig is written in the pixel capacitor Cs. The pixel capacitor Cs is sufficiently small compared to the equivalent capacitor Coled of the light-emitting device EL. As a result, a most part of the video signal Vsig is written into the pixel capacitor Cs, precisely, to Vss1. A difference Vsig-Vss1 of Vsig is written in the pixel capacitor Cs. Therefore, the voltage Vgs between the gate G and source S of the drive transistor Trd becomes a level of the sum of the Vth that has been previously detected and held and the Vsig-Vss1 that is sampled this time (Vsig−Vss1+Vth). Hereinafter, it is assumed that Vss1=0 V for easy description, then the gate-source voltage Vgs becomes Vsig+Vth, as illustrated in the timing chart in FIG. 7. Sampling of the video signal Vsig is performed until timing T7, when the control signal WS returns to a low level. That is, timing T5-T7 corresponds to the sampling period.

(79) At timing T6, before timing T7 when the sampling period ends, the control signal DS becomes a low level and the switching transistor Tr4 is turned ON. Accordingly, the drive transistor Trd is connected to the power supply Vcc, so that the pixel circuit enters a light-emitting period from a non-light-emitting period. In this way, mobility correction of the drive transistor Trd is performed in the period T6-T7 when the sampling transistor Tr1 is still in an ON state and the switching transistor Tr4 is brought into an ON state. That is, in this embodiment, mobility correction is performed in the period T6-T7 when a latter part of the sampling period and a head part of the light-emitting period overlap each other. Note that, at the head of the light-emitting period to perform mobility correction, the light-emitting device EL is actually in a reverse bias state, and thus does not emit light. In this mobility correcting period T6-T7, the drain current Ids flows in the drive transistor Trd in a state where the gate G of the drive transistor Trd is fixed to the level of the video signal Vsig. Here, by setting Vss1−Vth<VthEL, the light-emitting device EL is kept in a reverse bias state, and thus has a simple capacitance characteristic instead of a diode characteristic. Accordingly, the current Ids flowing in the drive transistor Trd is written in a capacitor C=Cs+Coled, the sum of the pixel capacitor Cs and the equivalent capacitor Coled of the light-emitting device EL. Accordingly, the source potential (S) of the drive transistor Trd rises. In the timing chart in FIG. 16, this rise is represented by ΔV. This rise ΔV is eventually subtracted from the gate-source voltage Vgs held in the pixel capacitor Cs, which corresponds to negative feedback. In this way, by negatively feeding back the output current Ids of the drive transistor Trd to the input voltage Vgs of the drive transistor Trd, the mobility μ can be corrected. The negative feedback amount ΔV can be optimized by adjusting the time width t of the mobility correcting period T6-T7.

(80) At timing T7, the control signal WS becomes a low level and the sampling transistor Tr1 is turned OFF. As a result, the gate G of the drive transistor Trd is disconnected from the signal line SL. Since application of the video signal Vsig stops, the gate potential (G) of the drive transistor Trd can rise, and rises with the source potential (S). During that time, the gate-source voltage Vgs held in the pixel capacitor Cs maintains a value of (Vsig−ΔV+Vth). The reverse bias state of the light-emitting device EL is canceled in accordance with a rise of the source potential (S), and thus flow-in of the output current Ids causes the light-emitting device EL to actually start emitting light. The relationship between the drain current Ids and the gate voltage Vgs at this time is given as in the following expression 2, by substituting Vsig−ΔV+Vth to Vgs of the above transistor characteristic expression 1.
Ids=kμ(Vgs−Vth).sup.2=kμ(Vsig−ΔV).sup.2  expression 2

(81) In expression 2, k=(½) (W/L)Cox. The term of Vth is canceled from this characteristic expression 2, and it is understood that the output current Ids supplied to the light-emitting device EL does not depend on the threshold voltage Vth of the drive transistor Trd. Basically, the drain current Ids is determined by the signal voltage Vsig of the video signal. In other words, the light-emitting device EL emits light at brightness in accordance with the video signal Vsig. At that time, Vsig is corrected with the feedback amount ΔV. This correction amount ΔV acts to cancel the effect of the mobility μ positioned at a coefficient part of the characteristic expression 2. Thus, the drain current Ids substantially depends on only the video signal Vsig.

(82) Finally, at timing T8, the control signal DS becomes a high level, the switching transistor Tr4 is turned OFF, and light emission ends and also the field ends. Then, the next field starts and the Vth correcting operation, the mobility correcting operation, and the light emitting operation are repeated again.