Abstract
Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments comprise an adaptive bias decoder for providing additional bias to array input lines to compensate for instances where ground floats above 0V. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation while maintaining accuracy in the operation.
Claims
1. A non-volatile memory system, comprising: an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain of each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to a control gate line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the control gate line in response to changes in a voltage of the source line.
2. The non-volatile memory system of claim 1, further comprising a plurality of pull down bit lines, each of the plurality of pull down bit lines coupling a row of non-volatile memory cells to a pull down node.
3. The non-volatile memory system of claim 1, wherein the operation is a program operation.
4. The non-volatile memory system of claim 3, wherein the adaptive bias decoder adjusts the voltage provided to the source line in response to changes in temperature.
5. The non-volatile memory system of claim 1, wherein the adaptive bias decoder adjusts the voltage provided to the source line in response to changes in temperature.
6. The non-volatile memory system of claim 1, wherein the adaptive bias decoder comprises a resistor comprising a first end and a second end, the first end coupled to an adjustable current source and the second end coupled to the source line.
7. The non-volatile memory system of claim 6, wherein the adaptive bias decoder further comprises a regulator coupled to the first end of the resistor.
8. The non-volatile memory system of claim 1, wherein the adaptive bias decoder adjusts the voltage provided to the control gate line based on a function performed on characterization data.
9. The non-volatile memory system of claim 1, wherein the adaptive bias decoder adjusts the voltage provided to the control gate line based on source line voltage changes.
10. The non-volatile memory system of claim 1, wherein the adaptive bias decoder adjusts the voltage provided to the control gate line based on body effect change.
11. The non-volatile memory system of claim 1, wherein the adaptive bias decoder comprises an adjustable current source and an adjustable resistor.
12. The non-volatile memory system of claim 1, wherein the adaptive bias decoder comprises an operational amplifier and one or more adjustable resistors.
13. The non-volatile memory system of claim 1, wherein the adaptive bias circuit further comprises a digital-to-analog converter for converting a digital input to an analog signal applied to the control gate line.
14. The non-volatile memory system of claim 13, wherein the adaptive bias circuit further comprises an analog-to-digital for converting an array output current to digital output bits.
15. The non-volatile memory system of claim 1, wherein the adaptive bias circuit further comprises an output circuit for converting an array output to digital output bits.
16. The non-volatile memory system of claim 1, wherein the adaptive bias circuit further comprises an analog-to-digital for converting an array output current to digital output bits.
17. A non-volatile memory system, comprising: an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain of each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to a word line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the word line in response to changes in a voltage of the source line.
18. The non-volatile memory system of claim 17, further comprising: a plurality of pull down bit lines, each of the plurality of pull down bit lines coupling a row of non-volatile memory cells to a pull down node.
19. The non-volatile memory system of claim 17, wherein the operation is a read operation.
20. The non-volatile memory system of claim 17, wherein the operation is a program operation.
21. The non-volatile memory system of claim 17, wherein the adaptive bias decoder adjusts the voltage provided to the source line in response to changes in temperature.
22. The non-volatile memory system of claim 17, further comprising an analog-to-digital converter.
23. The non-volatile memory system of claim 17, wherein the adaptive bias decoder comprises a resistor comprising a first end and a second end, the first end coupled to an adjustable current source and the second end coupled to the pull down node.
24. The non-volatile memory system of claim 23, wherein the adaptive bias decoder further comprises a voltage regulator coupled to the first end of the resistor.
25. The non-volatile memory system of claim 23, wherein the adaptive bias decoder further comprises a digital-to-analog converter for converting a digital input to an analog signal applied to the word line.
26. The non-volatile memory system of claim 17, wherein the adaptive bias decoder adjusts the voltage provided to the word line based on a function performed on characterization data.
27. The non-volatile memory system of claim 17, wherein the adaptive bias decoder adjusts the voltage provided to the word line based on source voltage changes.
28. The non-volatile memory system of claim 17, wherein the adaptive bias decoder adjusts the voltage provided to the word line based on body effect change.
29. The non-volatile memory system of claim 17, wherein the adaptive bias decoder adjusts the voltage provided to the word line based on coupling ratio change.
30. A non-volatile memory system, comprising: an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to an erase gate line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the erase gate line in response to changes in a voltage of the source line node.
31. The non-volatile memory system of claim 30, further comprising: a plurality of pull down bit lines, each of the plurality of pull down bit lines coupling a row of non-volatile memory cells to a pull down node.
32. The non-volatile memory system of claim 30, wherein the operation is a read operation.
33. The non-volatile memory system of claim 30, wherein the operation is a program operation.
34. The non-volatile memory system of claim 30, wherein the adaptive bias decoder adjusts the voltage provided to the source line in response to changes in temperature.
35. The non-volatile memory system of claim 30, further comprising an analog-to-digital converter.
36. The non-volatile memory system of claim 30, wherein the adaptive bias decoder comprises a resistor comprising a first end and a second end, the first end coupled to an adjustable current source and the second end coupled to the pull down node.
37. The non-volatile memory system of claim 37, wherein the adaptive bias decoder further comprises a voltage regulator coupled to the first end of the resistor.
38. The non-volatile memory system of claim 37, wherein the adaptive bias decoder further comprises a digital-to-analog converter for converting a digital input to an analog signal applied to the erase gate line.
39. The non-volatile memory system of claim 30, wherein the adaptive bias decoder adjusts the voltage provided to the erase gate line based on a function performed on characterization data.
40. The non-volatile memory system of claim 30 wherein the adaptive bias decoder adjusts the voltage provided to the erase gate line based on source voltage modulation.
41. The non-volatile memory system of claim 30, wherein the adaptive bias decoder adjusts the voltage provided to the erase gate line based on body effect change.
42. The non-volatile memory system of claim 30, wherein the adaptive bias decoder adjusts the voltage provided to the erase gate line based on coupling ratio change.
43. A non-volatile memory system, comprising: an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a fixed voltage to the source line of the array during operation.
44. The non-volatile memory system of claim 43, wherein the adaptive bias decoder adjusts the voltage provided to the source line in response to changes in temperature.
45. The non-volatile memory system of claim 43, wherein the adaptive bias decoder is a force/sense regulator.
46. The non-volatile memory system of claim 43, wherein the adaptive bias decoder is a buffer regulator.
47. The non-volatile memory system of claim 43, wherein the adaptive bias decoder adjusts the voltage provided to the source line in response to changes in temperature.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0079] FIG. 1 depicts a prior art artificial neural network.
[0080] FIG. 2 depicts a prior art split gate flash memory cell.
[0081] FIG. 3 depicts another prior art split gate flash memory cell
[0082] FIG. 4 depicts another prior art split gate flash memory cell.
[0083] FIG. 5 depicts another prior art split gate flash memory cell.
[0084] FIG. 6 depicts another prior art split gate flash memory cell.
[0085] FIG. 7 depicts a prior art stacked gate flash memory cell.
[0086] FIG. 8 depicts a twin split-gate memory cell.
[0087] FIG. 9 depicts different levels of an exemplary artificial neural network utilizing one or more VMM arrays.
[0088] FIG. 10 depicts a VMM system comprising a VMM array and other circuitry.
[0089] FIG. 11 depicts an exemplary artificial neural network utilizing one or more VMM systems.
[0090] FIG. 12 depicts an embodiment of a VMM array.
[0091] FIG. 13 depicts another embodiment of a VMM array.
[0092] FIG. 14 depicts another embodiment of a VMM array.
[0093] FIG. 15 depicts another embodiment of a VMM array.
[0094] FIG. 16 depicts another embodiment of a VMM array.
[0095] FIG. 17 depicts a VMM system.
[0096] FIGS. 18A, 18B, and 18C depict a prior art VMM array.
[0097] FIGS. 19A, 19B, and 19C depicts an improved VMM array.
[0098] FIG. 20 depicts another improved VMM array.
[0099] FIG. 21 depicts a VMM system with an improved source line pull down mechanism.
[0100] FIG. 22 depicts another VMM system with an improved source line pull down mechanism.
[0101] FIG. 23 depicts another VMM system with an improved source line pull down mechanism.
[0102] FIG. 24 depicts another VMM system with an improved source line pull down mechanism.
[0103] FIG. 25 depicts an exemplary layout diagram of a VMM system with an improved source line pull down mechanism.
[0104] FIG. 26 depicts another exemplary layout diagram of a VMM system with an improved source line pull down mechanism.
[0105] FIG. 27A, 27B, and 27C depict other improved VMM arrays.
[0106] FIG. 28 depicts another improved VMM array comprising a redundant array.
[0107] FIG. 29 depict another improved VMM system that comprises two VMM arrays and shared dummy bit line switching circuitry.
[0108] FIG. 30 depicts another improved VMM system.
[0109] FIG. 31 depicts an embodiment of a summer circuit.
[0110] FIG. 32 depicts another embodiment of a summer circuit.
[0111] FIGS. 33A and 33B depicts other embodiments of a summer circuit.
[0112] FIGS. 34A, 34B, and 34C depicts embodiments of an output circuit.
[0113] FIG. 35 depicts a neuron output circuit.
[0114] FIG. 36 depicts an embodiment of an analog-to-digital converter.
[0115] FIG. 37 depicts another embodiment of an analog-to-digital converter.
[0116] FIG. 38 depicts another embodiment of an analog-to-digital converter.
[0117] FIG. 39 depicts another embodiment of an analog-to-digital converter.
[0118] FIG. 40 depicts a desired voltage difference between a control gate line and a source line in a VMM array.
[0119] FIG. 41 depicts a desired voltage difference between a word line and a source line in a VMM array.
[0120] FIG. 42 depicts a desired voltage difference between a bit line and a source line in a VMM array.
[0121] FIG. 43 depicts a typical change in voltage for a terminal in a VMM array in response to a change in temperature.
[0122] FIGS. 44A and 44B depicts adaptive bias circuits.
[0123] FIGS. 45A and 45B depicts regulator circuits.
[0124] FIG. 46A depicts a digital-to-analog converter.
[0125] FIG. 46B depicts an analog-to-digital converter.
[0126] FIG. 47 depicts a decoder.
[0127] FIG. 48 depicts a current-to-voltage summer.
[0128] FIG. 49 depicts another current-to-voltage summer.
[0129] FIG. 50 depicts another current-to-voltage summer.
[0130] FIG. 51 depicts another current-to-voltage summer.
[0131] FIG. 52 depicts another current-to-voltage summer.
[0132] FIG. 53 depicts high voltage decoding circuitry for an erase gate decoder, control gate decoder, and source line decoder.
DETAILED DESCRIPTION OF THE INVENTION
[0133] The artificial neural networks of the present invention utilize a combination of CMOS technology and non-volatile memory arrays.
[0134] Embodiments of Improved VMM Systems
[0135] FIG. 17 depicts a block diagram of VMM system 1700. VMM system 1700 comprises VMM array 1701, row decoders 1702, high voltage decoders 1703, column decoders 1704, bit line drivers 1705, input circuit 1706, output circuit 1707, control logic 1708, and bias generator 1709. VMM system 1700 further comprises high voltage generation block 1710, which comprises charge pump 1711, charge pump regulator 1712, and high voltage level generator 1713. VMM system 1700 further comprises algorithm controller 1714, analog circuitry 1715, control logic 1716, and test control logic 1717. The systems and methods described below can be implemented in VMM system 1700.
[0136] The input circuit 1706 may include circuits such as a DAC (digital to analog converter), DPC (digital to pulses converter), AAC (analog to analog converter, such as current to voltage converter), PAC (pulse to analog level converter), or any other type of converters. The input circuit 1706 may implement normalization , scaling functions, or arithmetic functions. The input circuit 1706 may implement temperature compensation function for input. The input circuit 1706 may implement activation function such as ReLU or sigmoid. The output circuit 1707 may include circuits such as a ADC (analog to digital converter, to convert neuron analog output to digital bits), AAC (analog to analog converter, such as current to voltage converter), APC (analog to pulse(s) converter), or any other type of converters. The output circuit 1707 may implement activation function such as ReLU or sigmoids. The output circuit 1707 may implement statistic normalization, regularization, up/down scaling functions, statistical rounding, or arithmetic functions (e.g., add, subtract, divide, multiply, shift, log) for neuron outputs. The output circuit 1707 may implement temperature compensation function for neuron outputs or array outputs (such as bitline output) such as to keep power consumption of the array approximately constant or to improve precision of the array (neuron) outputs such as by keeping the IV slope approximately the same.
[0137] FIG. 18A depicts prior art VMM system 1800. VMM system 1800 comprises exemplary cells 1801 and 1802, exemplary bit line switch 1803 (which connects bit lines to sensing circuitry), exemplary dummy bit line switch 1804 (which couples to a low level such as ground level in read), exemplary dummy cells 1805 and 1806 (source line pull down cells). Bit line switch 1803 is coupled to a column of cells, including cells 1801 and 1802, that are used to store data in VMM system 1800. Dummy bit line switch 1804 is coupled to a column (bitline) of cells that are dummy cells are not used to store data in VMM system 1800. This dummy bitline (aka source line pulldown bitline) is used as source line pull down in read, meaning used to pull the source line SL to low level such ground level through the memory cells in the dummy bitline.
[0138] One drawback of VMM system 1800 is that the input impedance for each cell varies due to the length of the electrical path through the relevant bit line switch, the cell itself, and the relevant dummy bit line switch. For example, FIG. 18B shows the electrical path through bit line switch 1803, cell 1801, dummy cell 1805, and dummy bit line switch 1804. Similarly, FIG. 18C shows the electrical path through bit line switch 1803, vertical metal bitline 1807, cell 1802, dummy cell 1808, vertical metal bitline 1808, and dummy bit line switch 1804. As can be seen, the path through cell 1802 traverses a significantly larger length of bit line and dummy bit line, which is associated with a higher capacitance and higher resistance. This results in cell 1802 having a greater parasitic impedance in the bit line or source line than cell 1801. This variability is a drawback, for instance, because it results in a variance in the precision of the cell output as applied to read or verify (for program/erase tuning cycles) cells depending on their location within the array.
[0139] FIG. 19A depicts improved VMM system 1900. VMM system 1900 comprises exemplary cells 1901 and 1902, exemplary bit line switch 1903 (which connects the bit lines to sensing circuitry), exemplary dummy cells 1905 and 1906 (source line pull down cells), and exemplary dummy bit line switch 1904 (which couples to a low level such as ground level in read, this switch connects to dummy bit line that connects to dummy cells used as source line pull down). As can be seen, exemplary dummy bit line switch 1904 and the other dummy bit line switches are located on the opposite end of the array from bit line switch 1903 and the other bit line switches.
[0140] The benefit of this design can be seen in FIGS. 19B and 19C. FIG. 19B depicts the electrical path through bit line switch 1903, cell 1901, dummy cell 1905 (source line pull down cell), vertical metal bit line 1908, and dummy bit line switch 1904 (which couples to a low level such as ground level in read). FIG. 19C depicts the electrical path through bit line switch 1903, vertical metal line 1907, cell 1902, dummy cell 1906 (source line pull down cell), and dummy bit line switch 1904. The paths are substantially the same (cells, interconnect lengths), which is true for all cells in VMM system 1900. As a result, the impedance of the bit line impedance plus source line impedance of each cell is substantially the same, which means that the variance in the amount of parasitic voltage drop drawn to read or verify operation of the various cells in the array is relatively same .
[0141] FIG. 20 depicts VMM system 2000 with global source line pulldown bitline. VMM system 2000 is similar to VMM system 1900, except that: the dummy bit lines 2005a-2005n or 2007a-2007n are connected together (to act as global source line pulldown lines to pull memory cell source lines to ground level during read or verify), the dummy bit line switches, such as dummy bit line switch 2001 and 2002, are connected or coupled to a common ground denoted ARYGND; and the source lines are coupled together to source line switch 2003, which selectively pulls the source lines to ground. These changes further decrease the variance in (array) parasitic impedance among cells during read or verify operations. The source lines are connected together as SLARY 2888.
[0142] FIG. 21 depicts VMM system 2100. VMM system 2100 comprises bit line switch 2101, pull down bit line switch 2102, pull down bit line switch 2103, bit line switch 2104, data cell 2105 (herein, a “data cell” is a memory cell used to store a weight value for a neural network), pull down cell 2106, pull down cell 2107, and data cell 2018. Note that the pulldown cells 2106 and 2107 are adjacent to each together. This allows vertical metal lines BLpdx of the two pulldown cells 2106 and 2107 to be connected together (line 2111) to reduce parasitic resistance due to the resulting wider metal line. During a read or verify (for program/erase tuning cycles) operation of data cell 2105, current will flow through bit line switch 2101 into the bit line terminal of cell 2105 and out to the source line terminal of cell 2015, where it then flows into source line 2110, where it flows into the source line terminals of pull down cells 2106 and 2107 and through pull down bit line switches 2102 and 2103. During a read or verify (for program/erase tuning cycles) operation of cell 2104, current will flow through bit line switch 2104 into the bit line terminal of data cell 2108 and out to the source line terminal of cell 2108, where it then flows into source line 2110, where it flows into the source line terminals of pull down cells 2106 and 2107 and through pull down bit line switches 2102 and 2103. This pattern of columns repeats throughout the array, where every four columns contains two columns of data cells and two adjacent array columns used for pull down operations. In another embodiment, the diffusion of the two pull down cells of the two adjacent columns can be merged together into one bigger diffusion to increase the pull down capability. In another embodiment, the diffusion of the pull down cell can be made to be bigger than that of the data cell diffusion to increase the pull down capability. In another embodiment, each pull down cell has a bias condition different than a bias condition of a selected data cell.
[0143] In one embodiment, the pull down cell has the same physical structure as a regular data memory cell. In another embodiment, the pull down cell has a different physical structure than a regular data memory cell, for example, the pull down cell can be a modified version of a regular data memory cell such as by modifying one or more physical dimensions (width, length, etc.) for electrical parameters (layer thickness, implant, etc.). In another embodiment, the pull down cell is a regular transistor (without a floating gate) such as an I0 or high voltage transistor.
[0144] FIG. 22 depicts VMM system 2200. VMM system 2200 comprises bit line 2201, pull down bit line 2202, data cells 2203 and 2206, pull down cells 2204 and 2205, and source line 2210. During a read or verify operation of cell 2203, current will flow through bit line switch 2201 into the bit line terminal of cell 2203 and out to the source line terminal of cell 2203, where it then flows into source line 2210 and into the source line terminals of pull down cell 2204 and through pull down bit line BLpd 2202. This design is repeated for every column, with the net result that the row containing pull down cell 2204 is a row of pull down cells.
[0145] During a read or verify (for program/erase tuning cycles) operation of cell 2206, current will flow through bit line switch 2201 into the bit line terminal of cell 2206 and out to the source line terminal of cell 2206, where it then flows into source line 2211 and into the source line terminals of pull down cell 2205 and through pull down bit line 2202. This design is repeated for every column, with the net result that the row containing pull down cell 2205 is a row of pull down cells. As shown in FIG. 22, there are four rows, the two middle adjacent rows are used for pull down cells, the top and bottom rows are data cells.
[0146] Table No. 10 depicts operating voltages for VMM system 2200. The columns in the table indicate the voltages placed on bit lines for selected cells, bit line pull downs, word lines for selected cells, control gates for selected cells, word lines WLS for selected pull down cells, control gates CGS for selected pull down cells, erase gates for all cells, and source lines for all cells. The rows indicate the operations of read, erase, and program. Note that the voltage bias for CGS and WLS in read are higher than that of the regular WL and CG biases to enhance the drive capability of the pull down cells. The voltage biased for WLS and CGS can be negative in programming to reduce disturb.
TABLE-US-00010 TABLE NO. 10 Operation of VMM Array 2200 of FIG. 22 Op Table BL BLpd WL CG WLS CGS EG SL Erase 0 V 0 V 0 V 0 V 0 V 0 V 11.5 V 0 V Program Iprog VINH ~0.7 V ~10.5 V −0.5 V to 0 V −2 V to 0 V ~4.5 V ~4.5 V Read 0.6 V 0 V ~0-1.1 V ~0-1.5 V 1.1-1.3 V 1.8-3 V 0 V 0 V
[0147] FIG. 23 depicts VMM system 2300. VMM system 2300 comprises bit line 2301, bit line 2302, data cells 2303 and 2306, and pull down cells 2304 and 2305. During a read or verify (for program/erase tuning cycles) operation of cell 2303, current will flow through bit line 2301 into the bit line terminal of cell 2303 and out to the source line terminal of cell 2303, where it then flows into source line terminals of pull down cell 2304 and through bit line 2302 (acting as pull down bit line in this case). This design is repeated for every column, with the net result that the row containing pull down cell 2304, in a first mode, is a row of pull down cells. During a read or verify (for program/erase tuning cycles) operation of data cell 2306, current will flow through bit line 2301 into the bit line terminal of cell 2306 and out to the source line terminal of cell 2306, where it then flows into source line terminals of pull down cell 2305 and through bit line 2302 (acting as pull down bit line in this case). This design is repeated for every column, with the net result that the row containing pull down cell 2305, in a second mode, is a row of pull down cells. As shown in FIG. 23, there are four rows, the alternative odd (or even) rows are used for pull down cells, the alternative even (or odd) rows are data cells.
[0148] Notably, during a second mode, cells 2305 and 2306 are active in read or verify and cells 2303 and 2305 are used for the pull down process, with the roles of bit lines 2301 and 2302 being reversed.
[0149] Table No. 11 depicts operating voltages for VMM system 2300. The columns in the table indicate the voltages placed on bit lines for selected data cells, bit lines for selected pull down cells, word lines for selected data cells, control gates for selected data cells, word lines WLS for selected pull down cells, control gates CGS for selected pull down cells, erase gates for all cells, and source lines for all cells. The rows indicate the operations of read, erase, and program.
TABLE-US-00011 TABLE NO. 11 Operation of VMM System 2300 of FIG. 23 Op Table BL0A BL0B WL CG WLS CGS EG SL Erase 0 V 0 V 0 V 0 V 0 V 0 V 11.5 V 0 V Program Iprog VINH ~0.7 V ~10.5 V −0.5 V to 0 V −2 V to 0 V ~4.5 V ~4.5 V Read 0.6 V/0 V 0 v/0.6 V ~0-1.1 V ~0-1.5 V 1.1-1.3 V 1.8-3 V 0 V 0 V
[0150] FIG. 24 depicts VMM system 2400. VMM system 2400 comprises bit line 2401, pull down bit line 2402, (data) cell 2403, source line 2411, and pull down cells 2404, 2405, and 2406. During a read or verify operation of cell 2403, current will flow through bit line 2401 into the bit line terminal of cell 2403 and out to the source line terminal of cell 2403, where it then flows into source line 2411, and where it then flows into the source line terminal of pull down cells 2404, 2405, and 2406, from which is flows through pull down bit line 2402. This design is repeated for every column, with the net result that the rows containing pull down cells 2404, 2405, and 2406 each are rows of pull down cells. This maximizes the pull down applied to the source line terminal of cell 2403, as current is drawn through three cells into pull down bit line 2402. Note the source lines of the four rows are connected together.
[0151] Table No. 12 depicts operating voltages for VMM system 2400. The columns in the table indicate the voltages placed on bit lines for selected cells, bit line pull downs, word lines for selected cells, control gates for selected cells, erase gates for selected cells, word lines WLS for selected pull down cells, control gates CGS for selected pull down cells, erase gates for selected pulldown cells, and source lines for all cells. The rows indicate the operations of read, erase, and program.
TABLE-US-00012 TABLE NO. 12 Operation of VMM System 2400 of FIG. 24 Op Table BL BPpd WL CG WLS CGS EG EGS SL Erase 0 V 0 V 0 V 0 V 0 V 0 V 11.5 V 11.5 V 0 V Program Iprog VINH ~0.7 V ~10.5 V −0.5 V to 0 V −2 V to 0 V ~4.5 V 0 V ~4.5 V Read 0.6 V 0 V ~0-1.1 V ~0-1.5 V 1.1-1.3 V 1.8-3 V 0 V ~2.5 V 0 V
[0152] FIG. 25 depicts an exemplary layout 2500 for VMM system 2200 of FIG. 22. The light squares indicate metal contacts to bit lines such as bit line 2201 and pull down bit lines such as pull down bit line 2202.
[0153] FIG. 26 depicts an alternative layout 2600 for a VMM system similar to the VMM system 2200 of FIG. 22, with the difference that pull down bit line 2602 is extremely wide and traverses two columns of pull down cells. That is, the diffusion area for pull down bit line 2602 is wider than the diffusion area for bit line 2601. Layout 2600 further shows cells 2603 and 2604 (pull down cell), source line 2610, and bit line 2601. In another embodiment, the diffusion of the two pull down cells (left and right) can be merged together into one bigger diffusion.
[0154] FIG. 27A depicts VMM system 2700. To implement negative and positive weights of a neural network, half of the bit lines are designated as w+ lines (bit lines connecting to memory cells implementing positive weights), and the other half of the bit lines are designated as w− lines (bit lines connecting to memory cells implementing negative weights) and are interspersed among the w+ lines in an alternating fashion. The negative operation is done at the output of the w− bit line (neuron output) by a summation circuit, such as summation circuits 2701 and 2702. The output of a w+ line and the output of a w− line are combined together to give effectively w=w+−w− for each pair of (w+, w−) cells for all pairs of (w+, w−) lines. The dummy bitlines or source line pulldown bitlines used to avoid FG-FG coupling and/or reduce IR voltage drop in the source line in read are not shown in the figure. The input (such as to CG or WL) to the system 2700 can has positive value or negative value input. For the case of the input has negative value, since actual input to array is still positive (such as an voltage level on CG or WL), the array output (bitline output) is negated before output to realize the equivalent function of the negative value input.
[0155] Alternatively, with reference to FIG. 27B, positive weights can be implemented in a first array 2711 and negative weights can implemented in a second array 2712, separate from the first array, and the resulting weights are appropriately combined together by summation circuits 2713. Similarly, the dummy bitlines (not shown) or source line pulldown bitlines (not shown) are used to avoid FG-FG coupling and/or reduce IR voltage drop in the source line in read.
[0156] Alternatively, FIG. 27C depicts VMM system 2750 to implement negative and positive weights of a neural network with positive or negative input. First array 2751 implements positive value inputs with negative and positive weights and second array 2752 implements negative value inputs with negative and positive weights. The output of the second array is negated before adding to the output of the first array by the summer 2755 since any input to any array only has positive value (such as an analog voltage level on CG or WL).
[0157] Table 10A shows an exemplary layout of a physical array arrangement of a (w+, w−) pair of bit lines BL0/1 and BL2/3, where 4 rows are coupled to source line pulldown bit lines BLPWDNs. Pair of (BL0,BL1) bit lines is used to implement (w+, w−) lines. Between the (w+, w−) line pair, there is a source line pull down bit line (BLPWDN). This is used to prevent coupling (e.g., FG to FG coupling) from adjacent (w+, w−) lines into the current (w+, w−) lines. Basically, the source line pull down bit line (BLPWDN) serves as physical barrier between pair of (w+, w−) lines.
[0158] Additional details regarding the FG to FG coupling phenomena and mechanisms for counteracting that phenomena are found in U.S. Provisional Patent Application No. 62/981,757, filed on Feb. 26, 2020 by the same assignee, and titled “Ultra-Precise Tuning of Analog Neural Memory Cells in a Deep Learning Artificial Neural Network,” which is incorporated by reference herein.
[0159] Table 10B shows different exemplary weight combination. ‘1’ means that the cell is used and has a real output value, whereas ‘0’ means the cell is not used and has no value or no significant output value.
[0160] In another embodiment, dummy bit lines instead of source line pull down bit lines can be used.
[0161] In another embodiment, dummy rows can also be used as physical barriers to avoid coupling between rows.
TABLE-US-00013 TABLE 10A Exemplary Layout BLPWDN BL0 BL1 BLPWDN BL2 BL3 BLPWDN row0 w01+ w01− w02+ w02− row1 w11+ w11− w12+ w12− row2 w21+ w21− w22+ w22− row3 w31+ w31− w32+ w32−
TABLE-US-00014 TABLE 10B Exemplary Weight Combinations BLPWDN BL0 BL1 BLPWDN BL2 BL3 BLPWDN row0 1 0 1 0 row1 0 1 0 1 row2 0 1 1 0 row3 1 1 1 1
[0162] Table 11A shows another array embodiment of a physical arrangement of (w+−w−) pair lines BL0/1 and BL2/3 with redundant lines BL01,BL23 and source line pulldown bit lines BLPWDN. BL01 is used to weight re-mapping for pair BL0/1 and BL23 is used to weight re-mapping for pair BL2/3.
[0163] Table 11B shows a case of distributed weight that needs no re-mapping, basically there is no adjacent ‘1’ between BL1 and BL3, which causes adjacent bit line coupling. Table 11C shows a shows a case of distributed weight that needs re-mapping, basically there is adjacent ‘1’ between BL1 and BL3, which causes adjacent bit line coupling. This re-mapping is shown in Table 11D, resulting in no ‘1’ value between any adjacent bit lines. Furthermore by re-mapping, meaning re-distributing the weights, the ‘1’ real value weight among the bit lines, the total current along the bit line is now reduced leading to more precise value in the bit line (output neuron). In this case, additional columns (bitline) are needed (BL01, BL23) to act as redundant columns.
[0164] Tables 11E and 11F depict another embodiments of remapping noisy cells (or defective cells) into the redundant (spare) columns such as BL01, BL23 in Table 10E or BL0B and BL1B in Table 11F. A summer is used to sum up the bit line outputs with mapping appropriately.
TABLE-US-00015 TABLE 11A Exemplary Layout BLPWDN BL01 BL0 BL1 BL2 BL3 BL23 BLPWDN row0 w01+ w01− w02+ w02− row1 w11+ w11− w12+ w12− row2 w21+ w21− w22+ w22− row3 w31+ w31− w32+ w32−
TABLE-US-00016 TABLE 11B Exemplary Weight Combinations BLPWDN BL01 BL0 BL1 BL2 BL3 BL23 BLPWDN row0 1 0 1 0 row1 0 1 0 1 row2 1 0 1 0 row3 0 1 0 1
TABLE-US-00017 TABLE 11C Exemplary Weight Combinations BLPWDN BL01 BL0 BL1 BL2 BL3 BL23 BLPWDN row0 0 1 1 0 row1 0 1 1 0 row2 0 1 1 0 row3 0 1 1 0
TABLE-US-00018 TABLE 11D Remapped Weight Combinations BLPWDN BL01 BL0 BL1 BL2 BL3 BL23 BLPWDN row0 0 0 1 0 0 1 row1 1 0 0 1 0 0 row2 0 0 1 0 0 1 row3 1 0 0 1 0 0
TABLE-US-00019 TABLE 11E Remapped Weight Combinations BLPWDN BL01 BL0 BL1 BL2 BL3 BL23 BLPWDN row0 0 0 1 0 0 1 row1 1 0 noisy or 1 0 0 defective cell (not used) row2 0 0 1 noisy or 0 1 defective cell (not used) row3 1 0 0 1 0 0
TABLE-US-00020 TABLE 11F Remapped Weight Combinations BLPWDN BL0A BL0B BL1A BL1B BLPWDN row0 1 0 0 0 row1 noisy or 1 1 0 defective cell (not used) row2 1 0 noisy or 1 defective cell (not used) row3 0 0 1 0
[0165] Table 11G shows an embodiment of array physical arrangement that is suitable for FIG. 27B. Since each array has either positive weight or negative weight, a dummy bitline acting as source line pull down and physical barrier to avoid FG-FG coupling is needed for each bit line.
TABLE-US-00021 TABLE 11G Exemplary Layout BLPWDN BL0 BLPWDN BL1 BLPWDN row0 w01+/− w02+/− row1 w11+/− w12+/− row2 w21+/− w22+/− row3 w31+/− w32+/−
[0166] Another embodiment has a tuning bit line as an adjacent bit line to a target bitline to tune the target bit line to final target by virtue of FG-FG coupling. In this case source line pull down bitline (BLPWDN is inserted on one side of the target bit line that does not border the tuning bitline.
[0167] Alternative embodiment for mapping noisy or defective cells are to designate these cells (after identify them as noisy or defective by sensing circuitry) as non-used cells, meaning they are to be (deeply) programmed to not contribute any value to the neuron output.
[0168] An embodiment for handling fast cells are first to identify these cells, then apply a more precision algorithm to these cells such as smaller or no voltage increment pulses or using floating gate coupling algorithm.
[0169] FIG. 28 depicts an optional redundant array 2801 that can be included in any of the VMM arrays discussed thus far. Redundant array 2801 can be used as redundancy to replace defective columns if any of the columns attached to bit line switches are deemed defective. The redundant array can have its own redundant neuron outputs (e.g., bit lines) and ADC circuits for redundancy purpose. For the case of redundancy is needed, the output of redundancy ADC is to replace the output of the ADC of the bad bit line. Redundant array 2801 can also be used for weight mapping such as described in Table 10x for power distribution across bit lines.
[0170] FIG. 29 depicts VMM system 2900, which comprises array 2901, array 2902, column multiplexors 2903, local bit lines LBL 2905a-d, global bit line GBL 2908 and 2909, and dummy bit line switches 2905. The column multiplexors 2903 is used to select top local bit line 2905 of the array 2901 or bottom local bit line 2905 of the array 2902 into the global bit line 2908. In one embodiment, the (metal) global bit line 2908 has the same number of lines as number of the local bit lines, e.g. 8 or 16. In another embodiment, the global bit line 2908 has only one (metal) line per N number of local bit lines, such as one global bit line per 8 or 16 local bit lines. The column multiplexors 2903 further includes multiplexing (muxing) the adjacent global bit line (such as GBL 2909) into the current global bit line (such as GBL 2908) to effectively increase the width of the current global bit line. This reduces the voltage drop across the global bit line.
[0171] FIG. 30 depicts VMM system 3000. VMM system 3000 comprises array 3010, (shift registers) SRs 3001, digital-to-analog converters 3002 (which receives the input from the SRs 3001 and output an equivalent (analog or pseudo-analog) level or info) to respective control gate lines CG, summer circuits 3003, analog-to-digital converters 3004, and bit line switches 3005. Dummy bit lines and dummy bit line switches are present but not shown. As shown, ADC circuits can be combined together to create a single ADC with greater precision (i.e., greater number of bits). The source lines are connected together as SLARY 3888.
[0172] Summer circuits 3003 can include the circuits that are shown in FIGS. 31-33. It may include circuits for normalization, scaling, arithmetic operations, activation, statistical rounding, etc.
[0173] FIG. 31 depicts current-to-voltage summer circuit 3100 adjustable by a variable resistor, which comprises current source 3101-1, . . . , 3101-n drawing current Ineu(1), . . . , Ineu(n), respectively (which are the currents received from bit line(s) of a VMM array), operational amplifier 3102, variable holding capacitor 3104, and variable resistor 3103. Operational amplifier 3102 outputs a voltage, Vneuout=R3103*(Ineu1+Ineu0), which is proportional to the current Ineux. The holding capacitor 3104 is used to hold the output voltage when switch 3106 is open. This holding output voltage is used for example to be converted into digital bits by an ADC circuit. VREF is a reference voltage for example 0.1V to 1.0V. This is voltage that can be imposed on the bitlines of the array in read.
[0174] FIG. 32 depicts current-to-voltage summer circuit 3200 adjustable by a variable capacitor (basically an integrator), which comprises current source 3201-1, . . . , 3201-n drawing current Ineu(1), . . . Ineu (n), respectively (which are the currents received from bit line(s) of a VMM array), operational amplifier 3202, variable capacitor 3203, and switch 3204. Operational amplifier 3202 outputs a voltage, Vneuout=Ineu*integration time/C3203, which is proportional to the current Ineu(s).
[0175] FIG. 33A depicts voltage summer 3300 adjustable by variable capacitors (i.e., a switch cap SC circuit), which comprises switches 3301 and 3302, variable capacitors 3303 and 3304, operational amplifier 3305, variable capacitor 3306, and switch 3306. When switch 3301 is closed, input Vin0 is provided to operational amplifier 3305. When switch 3302 is closed, input Vin1 is provided to operational amplifier 3305. Optionally, switches 3301 and 3302 are not closed at the same time. Operational amplifier 3305 generates an output Vout, that is an amplified version of the input (either Vin0 and/or Vin1, depending on which switch is closed among switches 3301 and 3302). That is Vout=Cin/Cout*(Vin), Cin is C3303 or C3304, Cout is C3306. For example Vout=Cin/Cout*Σ(Vinx), Cin=C3303=C3304. In one embodiment, Vin0 is a W+ voltage and Vin1 is a W− voltage, and voltage summer 3300 adds them together to generate output voltage Vout.
[0176] FIG. 33B depicts voltage summer 3350, which comprises switches 3351, 3352, 3353, and 3354, variable input capacitors 3358, operational amplifier 3355, variable feedback capacitor 3356, and switch 3357. In one embodiment, Vin0 is a W+ voltage and Vin1 is a W− voltage, and voltage summer 3300 adds them together to generate output voltage Vout.
[0177] For Input=Vin0: when switch 3354 and 3351 are closed, input Vin0 is provided to top terminal of the capacitor 3358. Then switch 3351 is open and switch 3353 is closed to transfer the charge from the capacitor 3358 into the feedback capacitor 3356. Basically then the output VOUT=(C3358/C3356)*Vin0 (for case of with VREF=0 as example).
[0178] For Input=Vin1: when switch 3353 and 3354 are closed, both terminals of the capacitor 3358 are discharged to VREF. Then switch 3354 is open and switch 3352 is closed, charging the bottom terminal of the capacitor 3358 to Vin1, which in turn charges up the feedback capacitor 3356 to VOUT=−(C3358/C3356)*Vin1 (for case of VREF=0).
[0179] Hence, if Vin1 input is enabled after Vin0 input is enabled, VOUT=(C3358/C3356)* (Vin0-Vin1), for case of VREF=0 as example. This is used for example to realize w=w+−w−
[0180] Methods of input and output operation to FIG. 2 which applies to the VMM arrays discussed above can be in digital or analog form. Methods include: [0181] Sequential Inputs IN [0:q] to DACs: [0182] Operate sequentially IN0, then IN1, . . . , then INq; all input bits has same VCGin; all bit line (neuron) outputs are summed with adjusting binary index multiplier; either before ADC or after ADC [0183] Adjusting neuron (bit line) binary index multiplier method: as shown in FIG. 20, the example summer has two bit lines BL0 and BLn. A weight is distributed across multiple bit lines BL0 to BLn. For example there are 4 bit lines BL0,BL1,BL2,BL3. The output from bitline BL0 is to be multiplied by 2{circumflex over ( )}0=1. The output from bit line BLn, which stand for nth binary bit position, is multiplied by 2{circumflex over ( )}n, for example 2{circumflex over ( )}3=8 for n=3. Then the output from all bit lines after being multiplied appropriately by binary bit position 2{circumflex over ( )}n, are summed together. Then this is digitized by the ADC. This method means all cells have only binary range, the multi level range (n-bit) is accomplished by the peripheral circuit (meaning by the summer circuit). Hence the voltage drop for all the bit lines is approximately the same for highest bias level of memory cell. [0184] Operate sequentially IN0, IN1, . . . , then INq; each input bit has a corresponding analog value VCGin; all neuron outputs are summed for all input bit evaluation; either before ADC or after ADC [0185] Parallel Inputs to DACs: [0186] Each input IN[0:q] has a corresponding analog value VCGin; all neuron outputs are summed with adjusting binary index multiplier method; either before ADC or after ADC
[0187] By sequentially operates on the arrays, the power is more evenly distributed. The neuron (bit line) binary index method also reduce the power in the array since each cell in the bit line only has binary levels, the 2{circumflex over ( )}n level is accomplished by the summer circuit 2603.
[0188] Each ADC as shown in FIG. 33 can be configured to combine with next ADC for higher bit implementation with appropriate design of the ADC.
[0189] FIGS. 34A, 34B, and 34C depict output circuits that can be used for summer circuits 3003 and analog-to-digital converters 3004 in FIG. 30.
[0190] FIG. 34A depicts output circuit 3400, which comprises analog-to-digital converter 3402, which receives neuron output 3401 and outputs output digital bits 3403.
[0191] FIG. 34B depicts output circuit 3410, which comprises neuron output circuit 3411 and analog-to-digital converter 3412, which together receive neuron output 3401 and generates outputs 3413.
[0192] FIG. 34C depicts output circuit 3420, which comprises neuron output circuit 3421 and converter 3422, which together receive neuron output 3401 and generates outputs 3423.
[0193] Neuron output circuit 3411 or 3411 can, for example, perform summing, scaling, normalization, arithmetic operations, etc. Converter 3422, for example, can perform ADC, PDC, AAC, APC operation, etc.
[0194] FIG. 35 depicts neuron output circuit 3500, which comprises adjustable (scaling) current source 3501 and adjustable (scaling) current source 3502, which together generate output i.sub.OUT, which is the neuron output. This circuit can perform summation of positive weight and negative weights, i.e., w=w+−w−, and up or down scaling of the output neuron current at the same time.
[0195] FIG. 36 depicts configurable neuron serial analog-to-digital converter 3600. It includes integrator 3670 which integrates the neuron output current into the integrating capacitor 3602. One embodiment is that the digital output (count output) 3621 is produced by clocking the ramping VRAMP 3650 until the comparator 3604 switches polarity or another embodiment is by ramping down node VC 3610 by the ramp current 3651 until the VOUT 3603 reaches the VREF 3650, at which point the EC 3605 signal disables the counter 3620. The (n-bit) ADC is configurable to have lower number of bit precision <n-bits or higher number of bit precision >n-bits depending on target application. The configurability is done such as by configuring the capacitor 3602, the current 3651, or ramping rate of the VRAMP 3650, the clocking 3641, etc. In another embodiment the ADC circuits of a VMM array is configured to have lower precision <n-bits and the ADC circuits of another VMM array is configured to have high precision >n-bits. Further this ADC circuit of one neuron circuit can be configured to combine with the next ADC of the next neuron circuit to produce higher n-bit ADC precision such as by combining the integrating capacitor 3602 of the two ADC circuits.
[0196] FIG. 37 depicts configurable neuron SAR (successive approximation register) analog-to-digital converter 3700. This circuit is a successive approximation converter that bases on charge redistribution using binary capacitors. It includes a binary CDAC (DAC basing on capacitors) 3701, op-amp/comparator 3702, SAR logic 3703. As shown GndV 3704 is a low voltage reference level, for example ground level.
[0197] FIG. 38 depicts a configurable neuron combo SAR analog-to-digital converter 3800. This circuit combines two ADCs from two neuron circuits into one to achieve higher precision n-bit, for example for 4-bit ADC for one neuron circuit, this circuit can achieve >4-bit precision such as 8-bit ADC precision by combining two 4-bit ADCs. The combo circuit topology is equivalent to a split cap (bridge capacitor (cap) or attention cap) SAR ADC circuit, for example a 8-bit 4C-4C SAR ADC resulted by combining two adjacent 4-bit 4C SAR ADC circuits. A bridge circuit 3804 is needed to accomplish this, the capacitance of capacitor of this circuit is=(total number of CDAC cap unit/total number of CDAC cap unit−1).
[0198] FIG. 39 depicts a configurable neuron, pipelined SAR CDAC ADC circuit 3900 that can be used to combine with the next SAR ADC to increase the number of bits in a pipelined fashion. Residue voltage 3906 is generated by capacitor 3930 Cf to provide as input to next stage of pipelined ADC (e.g. to provide gain of 2 (ratio of Cf to C of all caps in DAC 3901) as input to next SAR CDAC ADC).
[0199] Additional implementation details regarding configurable output neuron (such as configurable neuron ADC) circuits can be found in U.S. patent application Ser. No. 16/449,201, filed on Jun. 21, 2019 by the same assignee, and titled “Configurable Input Blocks and Output Blocks and Physical Layout for Analog Neural Memory in a Deep Learning Artificial Neural Network,” which is incorporated by reference herein.
[0200] Adaptive Bias Circuit
[0201] With reference again to FIG. 20, applicant has determined that during operation, the node “ARYGND” (array ground) will not always stay at 0V. Specifically, as current is injected into ARYGND from various source lines, the voltage of ARYGND will float above 0V, for example at 0.1-0.5V. This adversely affects the accuracy of VMM system 2000, because this will affect the reading and programming of the various cells, which are affected by the difference in voltage between the input lines WL, CG, EG, and BL and the source line that is pulled down to ARYGND.
[0202] In one embodiment, there is only one source line (SLARY) for the whole array, as shown as SLARY 2888 in FIG. 20 or SLARY 3888 in FIG. 30. A voltage bias can be applied by a regulator, as shown in FIG. 45A (which is a buffer regulator) or 45B (which is a force/sense regulator), directly to SLARY 2888 or 3888 to maintain a fixed bias, e.g., 20 mV. In another embodiment, there are multiple SLARY lines, and there are multiple regulators such as regulators 4510 or 4520 to maintain fixed bias on these SLARAY lines.
[0203] FIGS. 40-42 depict the adaptive voltage differential between control gate lines, word lines, and bit lines on the one hand, and source lines on the other hand.
[0204] In FIG. 40, graph 4000 indicates that it is desired that the difference between a control gate line and a source line (labeled d(CG-SL)) for a selected cell(s) is such that the current from selected cell(s) or bitline remains constant as the source line voltage increases. Here, the x axis tracks the SL voltage, and the y axis tracks the difference between the CG voltage and SL voltage. For example, when ARYGND creeps up above 0V (which means that the source line also will creep above 0V), it is desired that the difference between a control gate line and a source line will change adaptively to maintain the cell or bitline current at a constant level. In this example, the voltage on CG will be adaptively increased as a function of source line voltage to compensate for different effects from source voltage changes. The effects to be compensated for are such as from effective reduced gate-to-source voltage due to increasing source voltage or from increasing body effect on threshold voltage due to increasing source voltage. It also may compensate for the effect caused by reduced drain-to-source voltage due to increasing source voltage. It also compensates for the effect caused by coupling from control gate CG and source voltage into the floating gate FG. The appropriate compensation function or look-up-table data can be characterized from silicon data.
[0205] In FIG. 41, graph 4100 indicates that it is desired that the difference between a word line and a source line for a selected cell (labeled as d(WL-SL)) is such that the current from the selected cell(s) or bitline remains constant as the source line voltage increases. For example, when ARYGND creeps up above 0V (which means that the source line also will creep above 0V), it is desired that the difference between a word line and a source line will be increased adaptively to maintain the current of the cell or bitline at a constant level. The voltage on word line WL, for example, will be adaptively changed as a function of source line voltage to compensate for different effects from source voltage changes similarly as described above for FIG. 40. The word line voltage adaptation preferably also compensates for voltage coupling between the WL and FG terminals.
[0206] In FIG. 42, graph 4000 indicates that it is desired that the difference between a bit line and a source line for a selected cell (labeled as d(BL-SL)) is such that the current from the selected cell(s) or bitline remains constant as the source line voltage increases. For example, when ARYGND creeps up above 0V (which means that the source line also will creep above 0V), it is desired that the difference between a bit line and a source line is such that the current from the selected cell(s) or bitline remains at a constant level. The voltage on bit line BL, for example, will be adaptively increased as a function of source line voltage to compensate for different effects such as from reduced drain-to-source voltage, body effect modulated threshold voltage, voltage coupling from source to FG, or other electrical effects.
[0207] In FIG. 43, it can be seen in graph 4300 that as temperature of a VMM array increases (as will naturally happen during operation of the VMM array or due to changes in the environment), the bias voltage that should be applied to the control gate line, and/or erase gate line, and/or word line to effect the same operation will decrease as a function of increasing temperature for the sub-threshold operation region. The bias voltage may increase as a function of increasing temperature in the linear or saturation operation region. The appropriate compensation function or a look-up-table, for example, can be characterized from silicon data. That is, in addition to changes in the voltage of ARYGND, changes in temperature also may affect the operation and accuracy of a VMM array. In one embodiment, an on-chip temperature sensor is implemented to detect the change in temperature and apply the compensation function for bias voltages accordingly.
[0208] FIG. 44A depicts an adaptive bias circuit 4410, which comprises adjustable current source 4401 and adjustable resistor 4402. One end of resistor 4402 is coupled to adjustable current source 4401 at node VREF_AB 4403, and the other end of resistor 4402 is connected to the node ARYGND from FIG. 20 or FIG. 30. When the voltage of ARYGND changes, the voltage of node VREF_AB will change by approximately the same amount, as the voltage drop across resistor 4402 will remain constant for a constant current generated by adjustable current source 4401. The resistor 4402 can be adjusted to change the voltage VREF_AB according to a defined compensation function or a look-up-table to change as a function of ARYGND voltage. Similarly, the resistance of resistor 4402 may be changed as a function of temperature changes. In addition to, or in place of, or in combination with, any adjustment to the resistance of resistor 4402, the amount of current provided by adjustable current source 4401 can be adjusted according to a defined compensation function or a look-up-table to change as a function of either temperature or changes in the voltage of ARYGND. VREF_AB therefore will reflect any real-time changes in the voltage of ARYGND and temperature and can be utilized by various circuits during read or programming operations.
[0209] FIG. 44B depicts adaptive bias circuit 4420, which consists of adjustable resistor 4421, adjustable resistor 4422, and op-amp 4423. The resistance of resistor 4421 and/or resistor 4422 can be adjusted according to a defined compensation function or a look-up-table to change as a function of ARYGND voltage so as to provide a desired voltage VREF_AB at node 4424. The resistance of resistor 4421 and/or resistor 4422 can be adjusted according to a defined compensation function or a look-up-table to change as a function of temperature.
[0210] FIGS. 45A and 45B depict regulator 4500 (comprising regulator 4510 or regulator 4520, respectively) that optionally can receive the voltage VREF_AB from adaptive bias circuit 4400 at node IN to provide a regulated voltage output at node OUT. Regulator 4520 is used in a force/sense configuration to compensate, for example, for interconnect metal line voltage drop of power bus routing, where the voltage at output node OUT is switchably connected to a feedback voltage FB, so as to force the voltage at output node OUT to follow the feedback voltage FB. When applied to VMM system 2000, the voltage OUT can be applied to node SLARY 2888, as discussed above with reference to FIG. 20.
[0211] The voltage VREF_AB at node IN is determined from a lookup table or a function based on characterization data. The output voltage at node OUT, can be used to provide bias to ARYGND or SLARY. For example, node OUT can be used as a supply a SL bias for the whole array, such as SLARY, e.g., 0 v or 15 mV. Node OUT also can be used as a bias applied to one or more bit lines, for example, to compensate for coupling mismatch, body effect mismatch, or PVT mismatch, without limitation. Node OUT also can be used as a bias voltage for Vcg, for example, to compensate for coupling mismatch, body effect mismatch, or PVT mismatch, without limitation.
[0212] FIG. 46A depicts an adaptive bias circuit comprising input digital-to-analog converter 4600. Input digital-to-analog converter 4600 received digital input signal DIN[7:0] and generates an analog signal that can be applied to an input line of a VMM array, such as a control gate line, a word line, an erase gate line, or a source line to program one or more selected cells in the VMM array. Notably, input digital-to-analog converter 4600 utilizes voltage source VREF_AB from FIGS. 44 and 45, and it utilizes ARYGND from FIGS. 20 and 44A as its ground. Input digital-to-analog converter 4600 automatically compensates for variations in ARYGND through its usage of the VREF_AB voltage.
[0213] FIG. 46B depicts an adaptive bias circuit comprising an output analog-to-digital converter 4650. Output analog-to-digital converter 4650 receives array output such as current or voltage and generates digital output bits. Notably, output analog-to-digital converter 4650 utilizes voltage source VREF_AB from FIGS. 44A and/or 44B, and it utilizes ARYGND from FIGS. 20 and 44A as its ground. Thus, output analog-to-digital converter 4650 will compensate for variations in ARYGND through its usage of the VREF_AB voltage.
[0214] FIG. 47 depicts adjustable bias row decoder 4700, which comprises word line decoder 4701 coupled to control gate decoder 4702. In this example, adjustable bias row decoder 4700 is used for row 0 in a VMM array. All of the other rows in the array will have a similar adjustable bias row decoder assigned to it.
[0215] Word line decoder 4701 comprises PMOS transistor 4703 and NMOS transistor 4704 arranged as an inverter and NAND gate 4705, configured as shown. Control gate decoder 4702 comprises input digital-to-analog converter 4600 from FIG. 46, inverter 4706, switch 4707, switch 4708, and NMOS transistor 4709 acting as a pass gate, configured as shown. Here, the word line WL0 and the control gate line CG0 will be activated when NAND dated 4705 receives address signals corresponding to the row assigned to adjustable bias row decoder 4700 (here, row 0). In that instance when WL0 and CG0 are activated, the analog output voltage of input digital-to-analog converter 4600 will be applied to control gate CG0. Here, the control gate line CG0 receives a compensated bias voltage provided by input digital-to-analog converter 4600. Similar means for EG or WL compensation can be used as well.
[0216] FIG. 48 depicts current-to-voltage summer circuit 4800, which is used to convert array output (BL) current into a voltage, which is identical to current-to-voltage summer circuit 3100 in FIG. 31 except that operational amplifier 3102 receives VREF_AB (from FIGS. 44 and 45) instead of VREF on its non-inverting input and the array output currents refers to virtual ground node ARYGND.
[0217] FIG. 49 depicts current-to-voltage summer circuit 4900 comprising operational amplifier 4901, variable resistor 4902, and current source 4903 drawing current Ineu (which is a current received from a bit line of a VMM array). Operational amplifier receives VREF_AB (from FIGS. 44A and/or 45B) on its non-inverting input. Operational amplifier 4901 outputs a voltage, Vneuout. The array output currents refers to virtual ground node ARYGND.
[0218] FIG. 50 depicts current-to-voltage summer 5000, which is identical to current-to-voltage summer 3200 in FIG. 32 except that operational amplifier 3202 receives VREF_AB (from FIGS. 44A and/or 44B) instead of VREF on its non-inverting input. The array output currents refers to virtual ground node ARYGND.
[0219] FIG. 51 depicts voltage summer 5100, which is identical to voltage summer 3300 in FIG. 33A except that it utilizes voltage VREF_AB (from FIGS. 44A and/or 44B) instead of VREF. The array output voltage Vinx refer to virtual ground node ARYGND.
[0220] FIG. 52 depicts voltage summer 5200, which is identical to voltage summer 3350 in FIG. 33B except that it utilizes voltage VREF_AB (from FIGS. 44A and/or 44B) instead of VREF. The array output voltage Vinx refer to virtual ground node ARYGND.
[0221] FIG. 53 depicts VMM high voltage decode circuits, comprising erase gate decoder circuit 5301, control gate decoder circuit 5304, source line decoder circuit 5307, and high voltage level shifter 5311, which are appropriate for use with memory cells of the type shown in FIG. 3.
[0222] Erase gate decoder circuit 5301 comprises PMOS select transistor 5302 (controlled by signal HVO_B) and NMOS de-select transistor 5303 (controlled by signal HVO_B), configured as shown.
[0223] Control gate decoder circuit 5304 comprises PMOS select transistor 5304 (controlled by signal HVO_B) and NMOS de-select transistor 5306 (controlled by signal HVO_B), configured as shown.
[0224] Source line decoder circuit 5307 comprises NMOS monitor transistor 5308 (controlled by signal SL MON), driving transistor 5309 (controlled by signal HVO , and de-select transistor 5310 (controlled by signal HVO_B), configured as shown.
[0225] High voltage level shifter 5311 receives enable signal EN and outputs high voltage signal HV and its complement HVO_B, and receives for its voltage rails HVSUP (a high voltage) and HVSUP_LOW.
[0226] It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed therebetween) and “indirectly on” (intermediate materials, elements or space disposed therebetween). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed therebetween) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.
