Multi-level pulser and related apparatus and methods

Abstract

Apparatus and methods are provided directed to a device, including at least one ultrasonic transducer, a multi-level pulser coupled to the at least one ultrasonic transducer; the multi-level pulser including a plurality of input terminals configured to receive respective input voltages, an output terminal configured to provide an output voltage, and a signal path between a first input terminal and the output terminal including a first transistor having a first conductivity type coupled to a first diode and, in parallel, a second transistor having a second conductivity type coupled to a second diode.

Claims

1. An apparatus for an ultrasound device, comprising: a level shifter comprising: a level shifter input terminal to receive an input voltage; a level shifter output terminal to provide an output voltage level-shifted from the input voltage; circuitry coupled between the level shifter input terminal and the level shifter output terminal, the circuitry comprising: a first inverter having a first inverter input terminal and a first inverter output terminal; a capacitor having a first terminal and a second terminal; a diode having an anode and a cathode; and a series of at least second and third inverters, each of the second and third inverters having a power connection, the second inverter having a second inverter input terminal and a second inverter output terminal, and the third inverter having a third inverter input terminal and a third inverter output terminal; wherein: the first inverter input terminal is or is coupled to the level shifter input terminal; the first inverter output terminal is coupled to the first terminal of the capacitor; the second terminal of the capacitor is coupled to the second inverter input terminal; the anode of the diode is coupled to the power connection; the cathode of the diode is coupled to the second terminal of the capacitor; and the third inverter output terminal is or is coupled to the level shifter output terminal.

2. The apparatus of claim 1, wherein: the first inverter comprises a positive power supply connection coupled to a first voltage and a negative power supply connection coupled to a second voltage; and the level shifter is configured to receive either of the first voltage or the second voltage as the input voltage.

3. The apparatus of claim 1, wherein: each of the second and third inverters comprises a positive power supply connection coupled to a first voltage and a negative power supply connection coupled to a second voltage; and the level shifter is configured to output, as the output voltage, a voltage that is either the first voltage or the second voltage.

4. The apparatus of claim 3, wherein the first voltage and/or the second voltage is substantially between approximately −300 V and 300 V.

5. The apparatus of claim 1, wherein: each of the second and third inverters comprises a positive power supply connection coupled to a first voltage and a negative power supply connection coupled to a second voltage; and the anode of the diode is coupled to the second voltage.

6. The apparatus of claim 1, further comprising: a pulser having a pulser input terminal and a pulser output terminal; and an ultrasonic transducer having an ultrasonic transducer input terminal; wherein: the level shifter output terminal is coupled to the pulser input terminal; and the pulser output terminal is coupled to the ultrasonic transducer input terminal.

7. The apparatus of claim 6, wherein: the pulser comprises a p-type metal-oxide-semiconductor field-effect transistor (pMOSFET); and the series of two or more second inverters comprises an odd number of inverters.

8. The apparatus of claim 6, wherein: the pulser comprises a n-type metal-oxide-semiconductor field-effect transistor (nMOSFET); and the series of two or more second inverters comprises an even number of inverters.

9. The apparatus of claim 6, wherein the level shifter, the pulser, and the ultrasonic transducer are monolithically integrated on a single substrate.

10. The apparatus of claim 1, wherein: the first inverter input terminal is coupled to the level shifter input terminal; and the third inverter output terminal is coupled to the level shifter output terminal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Various aspects and embodiments of the application will be described with reference to the following figures. It should be appreciated that the figures are not necessarily drawn to scale. Items appearing in multiple figures are indicated by the same reference number in all the figures in which they appear.

(2) FIG. 1 is a block diagram of an ultrasound device including a multi-level pulser and/or a level shifter, according to a non-limiting embodiment of the present application.

(3) FIG. 2 illustrates a non-limiting circuit diagram of a multi-level pulser, according to a non-limiting embodiment of the present application.

(4) FIG. 3A illustrates a circuit diagram of a first embodiment of a level shifter, according to a non-limiting embodiment of the present application.

(5) FIG. 3B illustrates a circuit diagram of a second embodiment of a level shifter, according to a non-limiting embodiment of the present application.

(6) FIG. 4A illustrates a non-limiting equivalent circuit of the circuit of FIG. 2, during a first phase of a multi-level pulse formation, according to a non-limiting embodiment of the present application.

(7) FIG. 4B illustrates a non-limiting equivalent circuit of the circuit of FIG. 2, during a second phase of a multi-level pulse formation, according to a non-limiting embodiment of the present application.

(8) FIG. 4C illustrates a non-limiting equivalent circuit of the circuit of FIG. 2, during a third phase of a multi-level pulse formation, according to a non-limiting embodiment of the present application.

(9) FIG. 4D illustrates a non-limiting equivalent circuit of the circuit of FIG. 2, during a fourth phase of a multi-level pulse formation, according to a non-limiting embodiment of the present application.

(10) FIG. 4E illustrates a non-limiting equivalent circuit of the circuit of FIG. 2, during a fifth phase of a multi-level pulse formation, according to a non-limiting embodiment of the present application.

(11) FIG. 4F illustrates a non-limiting equivalent circuit of the circuit of FIG. 2, during a sixth phase of a multi-level pulse formation, according to a non-limiting embodiment of the present application.

(12) FIG. 5 is a graph illustrating a non-limiting example of a time-dependent multi-level pulse and the control signals, according to a non-limiting embodiment of the present application.

DETAILED DESCRIPTION

(13) The inventors have recognized and appreciated that the power necessary to transmit high-intensity pulses may be greatly decreased by forming electric pulses having multiple levels.

(14) Aspects of the present application relate to high-intensity focused ultrasound (HIFU) procedures that may be used to focus high-intensity ultrasound energy on targets to treat diseases or damaged tissues by selectively increasing the temperature of the target or the region surrounding the target. HIFU procedures may be used for therapeutic or ablative purposes. Pulsed signals may be used to generate HIFUs. According to aspects of the present application, the generation of such high-intensity pulses may require driving voltages of several tens to several hundreds of volts.

(15) The power consumption associated with the generation of typical 2-level pulses having a “low” voltage and a “high” voltage is proportional to the square of the high voltage. For example, the generation of a 2-level pulse having a “low” voltage equal to 0 requires a power equal to:
P.sub.( 2)=C*V.sup.2*f
where P(.sub.2) is the power needed to generate the 2-level pulse, C is the capacitance of the load receiving the pulse, V is the “high” voltage and f is the repetition frequency of the 2-level pulse.

(16) According to aspects of the present application, the power consumption associated with the generation of pulses for HIFU procedures may exceed several tens to thousands of watts, thus causing the circuit to generate significant amounts of heat.

(17) Aspects of the present application relate to multi-level pulsers designed to decrease power consumption and heat dissipation.

(18) Furthermore, aspects of the present application relate to a level shifter circuit configured to drive the multi-level pulser. The level shifter disclosed herein may dissipate considerably less power compared to typical level shifters. Accordingly, power may be dissipated only when a level is switched, while static power consumption may be negligible.

(19) The aspects and embodiments described above, as well as additional aspects and embodiments, are described further below. These aspects and/or embodiments may be used individually, all together, or in any combination of two or more, as the application is not limited in this respect.

(20) FIG. 1 illustrates a circuit for processing received ultrasound signals, according to a non-limiting embodiment of the present application. The circuit 100 includes N ultrasonic transducers 102a . . . 102n, wherein N is an integer. The ultrasonic transducers are sensors in some embodiments, producing electrical signals representing received ultrasound signals. The ultrasonic transducers may also transmit ultrasound signals in some embodiments. The ultrasonic transducers may be capacitive micromachined ultrasonic transducers (CMUTs) in some embodiments. The ultrasonic transducers may be piezoelectric micromachined ultrasonic transducers (PMUTs) in some embodiments. Further alternative types of ultrasonic transducers may be used in other embodiments.

(21) The circuit 100 further comprises N circuitry channels 104a . . . 104n. The circuitry channels may correspond to a respective ultrasonic transducer 102a . . . 102n. For example, there may be eight ultrasonic transducers 102a . . . 102n and eight corresponding circuitry channels 104a . . . 104n. In some embodiments, the number of ultrasonic transducers 102a . . . 102n may be greater than the number of circuitry channels.

(22) According to aspects of the present application, the circuitry channels 104a . . . 104n may include transmit circuitry. The transmit circuitry may include level shifters 106a . . . 106n coupled to respective multi-level pulsers 108a . . . 108n. The multi-level pulsers 108a . . . 108n may control the respective ultrasonic transducers 102a . . . 102n to emit ultrasound signals.

(23) Circuitry channels 104a . . . 104n may also include receive circuitry. The receive circuitry of the circuitry channels 104a . . . 104n may receive the electrical signals output from respective ultrasonic transducers 102a . . . 102n. In the illustrated example, each circuitry channel 104a . . . 104n includes a respective receive switch 110a . . . 110n and an amplifier 112a . . . 112n. The receive switches 110a . . . 110n may be controlled to activate/deactivate readout of an electrical signal from a given ultrasonic transducer 102a . . . 102n. More generally, the receive switches 110a . . . 110n may be receive circuits, since alternatives to a switch may be employed to perform the same function. The amplifiers 112a . . . 112n may be trans-impedance amplifiers (TIAs).

(24) The circuit 100 further comprises an averaging circuit 114, which is also referred to herein as a summer or a summing amplifier. In some embodiments, the averaging circuit 114 is a buffer or an amplifier. The averaging circuit 114 may receive output signals from one or more of the amplifiers 112a . . . 112n and may provide an averaged output signal. The averaged output signal may be formed in part by adding or subtracting the signals from the various amplifiers 112a . . . 112n. The averaging circuit 114 may include a variable feedback resistance. The value of the variable feedback resistance may be adjusted dynamically based upon the number of amplifiers 112a . . . 112n from which the averaging circuit receives signals. The averaging circuit 114 is coupled to an auto-zero block 116.

(25) The auto-zero block 116 is coupled to a time gain compensation circuit 118 which includes an attenuator 120 and a fixed gain amplifier 122. Time gain compensation circuit 118 is coupled to an analog-to-digital converter (ADC) 126 via ADC drivers 124. In the illustrated example, the ADC drivers 124 include a first ADC driver 125a and a second ADC driver 125b. The ADC 126 digitizes the signal(s) from the averaging circuit 114.

(26) While FIG. 1 illustrates a number of components as part of a circuit of an ultrasound device, it should be appreciated that the various aspects described herein are not limited to the exact components or configuration of components illustrated. For example, aspects of the present application relate to the multi-level pulsers 108a . . . 108n and the level shifters 106a . . . 106n.

(27) The components of FIG. 1 may be located on a single substrate or on different substrates. For example, as illustrated, the ultrasonic transducers 102a . . . 102n may be on a first substrate 128a and the remaining illustrated components may be on a second substrate 128b. The first and/or second substrates may be semiconductor substrates, such as silicon substrates. In an alternative embodiment, the components of FIG. 1 may be on a single substrate. For example, the ultrasonic transducers 102a . . . 102n and the illustrated circuitry may be monolithically integrated on the same semiconductor die. Such integration may be facilitated by using CMUTs as the ultrasonic transducers.

(28) According to an embodiment, the components of FIG. 1 form part of an ultrasound probe. The ultrasound probe may be handheld. In some embodiments, the components of FIG. 1 form part of an ultrasound patch configured to be worn by a patient.

(29) FIG. 2 illustrates the circuit diagram of a multi-level pulser, according to aspects to the present application. In some embodiments, multi-level pulser 200 may be configured to transmit a pulse to capacitor C. Capacitor C may represent the capacitance associated with an ultrasound transducer. For example, capacitor C may represent a capacitive micromachined ultrasonic transducer (CMUT). However, multi-level pulser 200 may be configured to transmit a pulse to a resistor, a resistive network or a network exhibiting any suitable combination of resistive and reactive elements.

(30) In the non-limiting embodiment illustrated in FIG. 2, multi-level pulser 200 is configured to provide an N-level pulse, where N may assume any value greater than 2. The power consumption P.sub.N associated with the transmission of a N-level pulser to capacitor C is equal to:
P.sub.(N)=C*V.sup.2*f/(N−1)
where f is the repetition frequency of the pulsed waveform. Accordingly, power consumption is reduced by a factor N−1 compared to typical 2-level pulsers.

(31) In some embodiments, N-level pulser 200 may comprise 2N−2 transistors and 2N−4 diodes. However, any suitable number of transistors may be used. Among the 2N−2 transistors, N−1 may exhibit one type of conductivity and N−1 may exhibit the opposite type of conductivity. However any other suitable combination of types of conductivity may be used. For example, N−1 transistors may be nMOS and N−1 transistors may be pMOS. However any other suitable type of transistor may be used.

(32) N-level pulser 200 may comprise N circuit blocks 201.sub.1, 201.sub.2 . . . 201.sub.N. The N circuit blocks may be connected to node 202. One terminal of capacitor C may also be connected to node 202. The second terminal of capacitor C may be connected to ground. Circuit block 201.sub.1 may comprise pMOS transistor T.sub.1, having the source connected to a reference voltage V.sub.DD and the drain connected to node 202. Reference voltage V.sub.DD may be a voltage supply. The gate of transistor T.sub.1 may be driven by signal V.sub.G1.

(33) Circuit block 201.sub.N may comprise nMOS transistor T.sub.2N-2, having the source connected to a reference voltage V.sub.SS and the drain connected to node 202. In some embodiments, reference voltage V.sub.SS may be less than reference voltage V.sub.DD. However, pulser 200 is not limited in this respect. Furthermore, reference voltage V.sub.ss may positive, negative or equal to zero. The gate of transistor T.sub.2N-2 may be driven by signal V.sub.G2N-2.

(34) In some embodiments, circuit blocks 201.sub.2 may comprise two transistors T.sub.2 and T.sub.3 and two diodes D.sub.2 and D.sub.3. Transistor T.sub.2 and diode D.sub.2 may be connected in series and transistor T.sub.3 and diode D.sub.3 may also be connected in series. The two series may be connected in parallel. In some embodiments, T.sub.2 may be a pMOS transistor, having the source connected to the reference voltage V.sub.MID2 and the drain connected to the anode of D.sub.2 and T.sub.3 may be an nMOS transistor, having the source connected to V.sub.MID2 and the drain connected to the cathode of D.sub.3. In some embodiments, V.sub.MID2 may be greater than V.sub.SS and less than V.sub.DD. The cathode of D.sub.2 and the anode of D.sub.3 may be connected to node 202. Furthermore, the gate of T.sub.2 may be driven by signal V.sub.G2 and the gate of T.sub.3 may be driven by signal V.sub.G3.

(35) In some embodiments, circuit blocks 201.sub.i, where i may assume any value between 3 and N−1, may comprise two transistors T.sub.2i-2 and T.sub.2i-1 and two diodes D.sub.2i-2 and D.sub.2i-1. Transistor T.sub.2i-2 and diode D.sub.2i-2 may be connected in series and transistor T.sub.2i-1 and diode D.sub.2i-1 may also be connected in series. The two series may be connected in parallel. In some embodiments, T.sub.2i-2 may be a pMOS transistor, having the source connected to the reference voltage V.sub.MIDi and the drain connected to the anode of D.sub.2i-2 and T.sub.2i-1 may be an nMOS transistor, having the source connected to V.sub.MIDi and the drain connected to the cathode of D.sub.2i-1. In some embodiments, V.sub.MIDi may be greater than V.sub.SS and less than V.sub.MID2. The cathode of D.sub.2i-2 and the anode of D.sub.2i-1 may be connected to node 202. Furthermore, the gate of T.sub.2i-2 may be driven by signal V.sub.G2i- 2 and the gate of T.sub.2i-1 may be driven by signal V.sub.G2i-1.

(36) V.sub.DD, V.sub.SS and V.sub.MIDi, for any value of i, may have values between approximately −300V and 300V, between approximately −200V and 200V, or any suitable value or range of values. Other values are also possible.

(37) FIG. 3A and FIG. 3B illustrate two non-limiting embodiments of a level shifter circuit, according to aspects of the present application. In some embodiments, level shifter 301, shown in FIG. 3A, may be integrated on the same chip as pulser 200. In some embodiments, level shifter 301 may be used to drive any of the pMOS transistors of pulser 200. For example, level shifter 301 may be used to output signal V.sub.G2i-2 to drive the gate of transistor T.sub.2i-2. The input voltage V.sub.IN2i-2 to level shifter 301 may be a control signal having two possible voltage levels: V.sub.SS and V.sub.SS+δV, where δV may assume any suitable value or range of values. In some embodiments, control signal V.sub.IN2i-2 may be generated by a circuit integrated on the same chip as level shifter 301. However, control signal V.sub.IN2i-2 may also be generated by a circuit integrated on a separate chip. In some embodiments, level shifter 301 may comprise an inverter I.sub.M1, followed by capacitor C.sub.M. The power supply pins of inverter I.sub.M1 may be connected to voltages V.sub.SS and V.sub.SS+δV. Capacitor C.sub.M may be followed by the series of a number of inverters. In some embodiments, capacitor C.sub.M is followed by three inverters I.sub.M2, I.sub.M3 and I.sub.M4. The “−” and “+” power supply pins of inverter I.sub.M2, I.sub.M3 and I.sub.M4 may be connected to voltages V.sub.MIDi−ΔV and V.sub.MIDi respectively. In some non-limiting embodiments, level shifter 301 may comprise diode D.sub.M. The cathode or diode D.sub.M may be connected to the output of capacitor C.sub.M, while the anode may be connected to the V.sub.MIDi−ΔV rail. While level shifter 301 comprises four inverters in the non-limiting embodiment of FIG. 3A, any suitable number of inverters may otherwise be used. Output voltage V.sub.G2i-2 may assume two possible voltages: V.sub.MIDi−ΔV and V.sub.MIDi.

(38) In some embodiments, level shifter 302, shown in FIG. 3B, may be integrated on the same chip as pulser 200. In some embodiments, level shifter 302 may be used to drive any of the nMOS transistors of pulser 200. For example, level shifter 302 may be used to output signal V.sub.G2i-1 to drive the gate of transistor T.sub.2i-1. The input voltage V.sub.IN2i-1 to level shifter 302 may be a control signal having two possible voltage levels: V.sub.SS and V.sub.SS+δV. In some embodiments, control signal V.sub.IN2i-1 may be generated by a circuit integrated on the same chip as level shifter 302. However, control signal V.sub.IN2i-1 may also be generated by a circuit integrated on a separate chip. In some embodiments, level shifter 302 may comprise an inverter I.sub.P1, followed by capacitor C.sub.P. The power supply pins of inverter I.sub.P1 may be connected to voltages V.sub.SS and V.sub.SS+δV. Capacitor C.sub.P may be followed by the series of a number of inverters. In some embodiments, capacitor C.sub.P is followed by two inverters I.sub.P2 and I.sub.P3 The power supply pins of inverter I.sub.M2 and I.sub.M3 may be connected to voltages V.sub.MIDi and V.sub.MIDi+ΔV. In some non-limiting embodiments, level shifter 302 may comprise diode DP. The cathode or diode D.sub.P may be connected to the output of capacitor C.sub.P, while the anode may be connected to the V.sub.MIDi rail. While level shifter 302 comprises three inverters in the non-limiting embodiment of FIG. 3B, any suitable number of inverters may otherwise be used. Output voltage V.sub.G2i-1 may assume two possible voltages: V.sub.MIDi and V.sub.MIDi+ΔV.

(39) According to aspects of the present application, level shifters 301 and 302 may dissipate power only when a level is switched, while static power may be negligible. Capacitors C.sub.M and C.sub.P may be used to shift the voltage level by storing a constant voltage drop across them. For example, the static power consumption may be less than 100mW, less than 1mW, less than 1 μW or less than any suitable value.

(40) FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D, FIG. 4E, and FIG. 4F illustrate six snapshots of pulser 200 corresponding to the six phases associated with the formation of a 4-level pulse, according to aspects on the present application. In the figures, only the active blocks are shown. While in the non-limiting example N is equal to 4, any other suitable value of N, such that N is greater than 2, may otherwise be used. In the example, V.sub.SS is set to 0.

(41) FIG. 5 illustrates a non-limiting example of multi-level pulse 500 generated according to aspects of the present application. In the non-limiting example, pulse 500 exhibits 4 levels: 0, V.sub.MID3, V.sub.MID2, and V.sub.DD. In addition, FIG. 5 illustrates the 6 control signals V.sub.G1, V.sub.G2, V.sub.G3, V.sub.G4, V.sub.G5, and V.sub.G6 used to respectively drive the gates of transistors T.sub.1, T.sub.2, T.sub.3, T.sub.4, T.sub.5, and T.sub.6. The process associated with the pulse generation can be divided in 6 phases. Between t.sub.1 and t.sub.2, pulse 500 may be increased from 0 to V.sub.MID3 by providing a negative pulse 504 to transistor T.sub.4 through V.sub.G4 as shown in FIG. 5. FIG. 4A illustrates pulser 201 between t.sub.1 and t.sub.2. During this period, the gate of transistor T.sub.4 may be driven by a voltage equal to V.sub.MID3−ΔV. ΔV may be chosen so as to create a conductive channel and cause transistor T.sub.4 to drive a current between the source and the drain passing through diode D.sub.4. Such current may charge capacitor C, such that an output voltage of V.sub.MID3 is obtained, neglecting any voltage drop on T.sub.4 and D.sub.4. Pulse 504 may be obtained through level shifter 301.

(42) Between t.sub.2 and t.sub.3, pulse 500 may be increased from V.sub.MID3 to V.sub.MID2 by providing a negative pulse 502 to transistor T.sub.2 through V.sub.G2 as shown in FIG. 5. FIG. 4B illustrates pulser 201 between t.sub.2 and t.sub.3. During this period, the gate of transistor T.sub.2 may be driven by a voltage equal to V.sub.MID2−ΔV. ΔV may be chosen so as to create a conductive channel and cause transistor T.sub.2 to drive a current between the source and the drain passing through diode D.sub.2. Such current may charge capacitor C, such that an output voltage of V.sub.MID2 is obtained, neglecting any voltage drop on T.sub.2 and D.sub.2. Pulse 502 may be obtained through level shifter 301.

(43) Between t.sub.3 and t.sub.4, pulse 500 may be increased from V.sub.MID2 to V.sub.DD by providing a negative pulse 501 to transistor T.sub.1through V.sub.G1 as shown in FIG. 5. FIG. 4C illustrates pulser 201 between t.sub.3 and t.sub.4. During this period, the gate of transistor T.sub.1 may be driven by a voltage equal to V.sub.DD−ΔV. ΔV may be chosen so as to create a conductive channel and cause transistor T.sub.1 to drive a current between the source and the drain. Such current may charge capacitor C, such that an output voltage of V.sub.DD is obtained, neglecting any voltage drop on T.sub.1. Pulse 501 may be obtained through level shifter 301.

(44) Between t.sub.4 and t.sub.5, pulse 500 may be decreased from V.sub.DD to V.sub.MID2 by providing a positive pulse 503 to transistor T.sub.3 through V.sub.G3 as shown in FIG. 5. FIG. 4D illustrates pulser 201 between t.sub.4 and t.sub.5. During this period, the gate of transistor T.sub.3 may be driven by a voltage equal to V.sub.MID2+ΔV. ΔV may be chosen so as to create a conductive channel and cause transistor T.sub.3 to drive a current between the drain and the source. Such current may discharge capacitor C, such that an output voltage of V.sub.MID2 is obtained, neglecting any voltage drop on T.sub.3 and D.sub.3. Pulse 503 may be obtained through level shifter 302.

(45) Between t.sub.5 and t.sub.6, pulse 500 may be decreased from V.sub.MID2 to V.sub.MID3 by providing a positive pulse 505 to transistor T.sub.5 through V.sub.G5 as shown in FIG. 5. FIG. 4E illustrates pulser 201 between t.sub.5 and t.sub.6. During this period, the gate of transistor T.sub.5 may be driven by a voltage equal to V.sub.MID3+ΔV. ΔV may be chosen so as to create a conductive channel and cause transistor T.sub.5 to drive a current between the drain and the source. Such current may discharge capacitor C, such that an output voltage of V.sub.MID3 is obtained, neglecting any voltage drop on T.sub.5 and D.sub.5. Pulse 505 may be obtained through level shifter 302.

(46) After t.sub.6, pulse 500 may be decreased from V.sub.MID3 to 0 by providing a positive pulse 506 to transistor T.sub.6 through V.sub.G6 as shown in FIG. 5. FIG. 4F illustrates pulser 201 after t.sub.6. During this period, the gate of transistor T.sub.6 may be driven by a voltage equal to ΔV. ΔV may be chosen so as to create a conductive channel and cause transistor T.sub.6 to drive a current between the drain and the source. Such current may discharge capacitor C, such that an output voltage of 0 is obtained, neglecting any voltage drop on T.sub.6. Pulse 506 may be obtained through level shifter 302.

(47) In the non-limiting example in connection to FIG. 5, pulse 500 is unipolar. However, multi-level pulser 200 in not limited in this respect. Multi-level pulser 200 may alternatively be configured to transmit bipolar pulses exhibiting levels having positive and negative voltages. In accordance with another aspect of the present application, the multi-level pulser 200 may be considered a multi-level charge recycling waveform generator in that charge recycling occurs on the decrementing step as charge is transferred from the output capacitance back into the power supply. In accordance with another aspect of the present application, although the multi-level pulser has been described as being used to drive a capacitive output, it may also be used to drive a resistive output.

(48) The amount of power saving when using a level shifter of the types described herein may be significant. In some embodiments, utilizing a level shifter of the types described herein may provide substantial power saving by setting the static power consumption to approximately zero. Accordingly, power may be dissipated only during switching states.

(49) Having thus described several aspects and embodiments of the technology of this application, it is to be appreciated that various alterations, modifications, and improvements will readily occur to those of ordinary skill in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the technology described in the application. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described.

(50) As described, some aspects may be embodied as one or more methods. The acts performed as part of the method(s) may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

(51) All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and/or ordinary meanings of the defined terms.

(52) The phrase “and/or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases.

(53) As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements.

(54) As used herein, the term “between” used in a numerical context is to be inclusive unless indicated otherwise. For example, “between A and B” includes A and B unless indicated otherwise.

(55) In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of” and “consisting essentially of” shall be closed or semi-closed transitional phrases, respectively.