Voltage dividers

Abstract

A voltage divider circuit arrangement includes a resistive divider circuit portion constructed from first and second resistors (R1, R2) The first and second resistors are connected in series and are arranged to provide a refresh voltage (Vrefresh) at a refresh node between them. A capacitive divider circuit portion is constructed from first and second capacitors (C1, C2). The first and second capacitors are connected in series and are arranged to provide an output voltage (Vout) at an output node. A switching circuit portion is arranged intermittently to switch the voltage divider circuit arrangement between a first mode wherein the resistive divider is enabled and the output node is connected to the refresh node, and a second mode wherein the resistive divider is disabled and the output node is not connected to the refresh node.

Claims

1. A voltage divider circuit arrangement comprising: a resistive divider circuit portion comprising at least first and second resistors having first and second resistor impedance values respectively, wherein said first and second resistors are connected in series and are arranged to provide a refresh voltage at a refresh node therebetween; a capacitive divider circuit portion comprising at least first and second capacitors having first and second capacitor impedance values respectively, wherein said first and second capacitors are connected in series and are arranged to provide an output voltage at an output node therebetween; a switching circuit portion arranged intermittently to switch the voltage divider circuit arrangement between a first mode wherein the resistive divider circuit portion is enabled and the output node is connected to the refresh node, and a second mode wherein the resistive divider circuit portion is disabled and the output node is not connected to the refresh node; and a hysteresis circuit portion arranged to vary the refresh voltage and the output voltage between a first value and a second value; wherein the hysteresis circuit portion comprises a hysteresis resistor and a hysteresis capacitor, wherein said the hysteresis circuit portion is arranged selectively to connect said hysteresis resistor in series with at least one of the first and second resistors and to connect said hysteresis capacitor in parallel with at least one of the first and second capacitors; and wherein the hysteresis circuit portion further comprises a first hysteresis transistor connected in parallel with the hysteresis resistor and a second hysteresis transistor connected in series with the hysteresis capacitor, wherein a first hysteresis signal is applied to the gate terminal of the first hysteresis transistor and a second hysteresis signal is applied to the gate terminal of the second hysteresis transistor.

2. The voltage divider circuit arrangement as claimed in claim 1, wherein a ratio between the first and second resistor impedance values is substantially equal to a ratio between the first and second capacitor impedance values and an input voltage connected across the resistive divider circuit portion is the same as an input voltage connected across the capacitive divider circuit portion.

3. The voltage divider circuit arrangement as claimed in claim 1, configured to provide a predetermined delay between the output node being disconnected from the refresh node and the resistive divider circuit portion being disabled when the switching circuit portion switches to the second mode.

4. The voltage divider circuit arrangement as claimed in claim 1, wherein the intermittent switching between the first mode and the second mode is periodic.

5. The voltage divider circuit arrangement as claimed in claim 1, wherein the switching circuit portion comprises an oscillator circuit portion arranged to produce a reference signal at a reference frequency and a one shot circuit portion arranged to produce the switch mode signal from the reference signal.

6. The voltage divider circuit arrangement as claimed in claim 1, wherein the first hysteresis transistor comprises a p-channel metal-oxide-semiconductor field-effect-transistor and the second hysteresis transistor comprises an n-channel metal-oxide-semiconductor field-effect-transistor.

7. The voltage divider circuit arrangement as claimed in claim 1, configured to provide a predetermined delay between the resistive divider circuit portion being enabled and the output node being connected to the refresh node when the switching circuit portion switches to the first mode.

8. The voltage divider circuit arrangement as claimed in claim 7, further comprising a delay circuit arranged to provide the predetermined delay between the resistive divider circuit portion being enabled and the output node being connected to the refresh node when the switching circuit portion switches to the first mode and/or a predetermined delay between the output node being disconnected from the refresh node and the resistive divider circuit portion being disabled when the switching circuit portion switches to the second mode.

9. The voltage divider circuit arrangement as claimed in claim 1, wherein the intermittent switching is controlled by a mode switch signal.

10. The voltage divider circuit arrangement as claimed in claim 9, wherein the switching circuit portion comprises a second switching transistor connected between the refresh node and the output node.

11. The voltage divider circuit arrangement as claimed in claim 9, wherein the mode switch signal comprises a series of pulses.

12. The voltage divider circuit arrangement as claimed in claim 9, wherein the switching circuit portion comprises a first switching transistor connected in series with the resistive divider circuit portion.

13. The voltage divider circuit arrangement as claimed in claim 12, wherein the first switching transistor comprises a p-channel metal-oxide-semiconductor field-effect-transistor arranged to receive at its gate terminal a logical negation of the mode switch signal.

14. The voltage divider circuit arrangement as claimed in claim 10, wherein the second switching transistor comprises an n-channel metal-oxide-semiconductor field-effect-transistor arranged to receive at its respective gate terminal the mode switch signal.

15. A voltage regulating circuit arrangement comprising: an error amplifier arranged to compare a reference voltage to a feedback voltage and produce at its output an error voltage proportional to a difference between said reference and feedback voltages; a pass field-effect-transistor arranged such that a source terminal thereof is connected to an input voltage, a gate terminal thereof connected to the output of the error amplifier, and a drain terminal thereof is connected to a load capacitor, wherein a regulator output voltage is produced at a node between the drain terminal of the pass field-effect-transistor and the load capacitor; and a voltage divider circuit arrangement comprising: a resistive divider circuit portion comprising at least first and second resistors having first and second resistor impedance values respectively, wherein said first and second resistors are connected in series and are arranged to provide a refresh voltage at a refresh node therebetween; a capacitive divider circuit portion comprising at least first and second capacitors having first and second capacitor impedance values respectively, wherein said first and second capacitors are connected in series and are arranged to provide the feedback voltage at an output node therebetween; a switching circuit portion arranged intermittently to switch the voltage divider circuit arrangement between a first mode wherein the resistive divider circuit portion is enabled and the output node is connected to the refresh node, and a second mode wherein the resistive divider circuit portion is disabled and the output node is not connected to the refresh node; and a hysteresis circuit portion arranged to vary the refresh voltage and the output voltage between a first value and a second value wherein the hysteresis circuit portion comprises a hysteresis resistor and a hysteresis capacitor, wherein said the hysteresis circuit portion is arranged selectively to connect said hysteresis resistor in series with at least one of the first and second resistors and to connect said hysteresis capacitor in parallel with at least one of the first and second capacitors; and wherein the hysteresis circuit portion further comprises a first hysteresis transistor connected in parallel with the hysteresis resistor and a second hysteresis transistor connected in series with the hysteresis capacitor, wherein a first hysteresis signal is applied to the gate terminal of the first hysteresis transistor and a second hysteresis signal is applied to the gate terminal of the second hysteresis transistor.

16. The voltage regulating circuit as claimed in claim 15, wherein the first hysteresis transistor comprises a p-channel metal-oxide-semiconductor field-effect-transistor and the second hysteresis transistor comprises an n-channel metal-oxide-semiconductor field-effect-transistor.

Description

(1) Certain embodiments of the present invention will now be described with reference to the accompanying drawings, in which:

(2) FIG. 1 is a circuit diagram of a voltage divider circuit arrangement in accordance with an embodiment of the present invention;

(3) FIG. 2 is a graph showing the output voltage produced by the divider circuit of FIG. 1 during operation;

(4) FIG. 3 is a circuit diagram of a low-dropout voltage regulator that includes the voltage divider circuit arrangement of FIG. 1 in accordance with a further embodiment of the present invention; and

(5) FIG. 4 is a graph showing the voltage produced by the low-dropout voltage regulator of FIG. 3.

(6) FIG. 1 is a circuit diagram of a voltage divider circuit arrangement 2 in accordance with an embodiment of the present invention. The voltage divider circuit arrangement 2 is arranged to receive an input voltage V.sub.in and produce a lower output voltage V.sub.out. The voltage divider circuit arrangement 2 shown in FIG. 1 is divided into three logical circuit portions: a resistive divider circuit portion 4; a capacitive divider circuit portion 6; and a switching circuit portion 8. The construction and function of each of the circuit portions 4, 6, 8 will be described in further detail below. It will of course be appreciated that these logical divisions are for illustrative purposes only and will typically all form part of a single integrated circuit.

(7) The resistive divider circuit portion 4 comprises: a first resistor R.sub.1; a second resistor R.sub.2; a hysteresis resistor R.sub.H; and a hysteresis p-channel metal-oxide-semiconductor field-effect-transistor (pMOSFET) 10.

(8) The capacitive divider circuit portion 6 comprises: a first capacitor C.sub.1; a second capacitor C.sub.2; a hysteresis capacitor C.sub.H; and an n-channel metal-oxide-semiconductor field-effect-transistor (nMOSFET) 12.

(9) The switching circuit portion 8 comprises: a low frequency oscillator 14; a monostable multivibrator circuit or “one-shot” pulse generator 16; a Boolean inverter 18; a delay circuit 20; a first switching pMOSFET 22; and a second switching nMOSFET 24.

(10) The resistive divider circuit portion 4 is arranged such that the resistors R.sub.1, R.sub.2, R.sub.H are connected in series with one another and with the first switching pMOSFET 22 such that the input voltage V.sub.in is connected to the source terminal of the first switching pMOSFET 22, the drain terminal of the first switching pMOSFET 22 is connected to one terminal of the hysteresis resistor R.sub.H, the other terminal of the hysteresis resistor R.sub.H is connected to a first terminal of the first resistor R.sub.1, the second terminal of the first resistor R.sub.1 is connected to a first terminal of the second resistor R.sub.2, and the second terminal of the second resistor R2 is connected to ground GND. The first hysteresis pMOSFET 10 is connected in parallel with the hysteresis resistor R.sub.H such that its source terminal is connected to a first terminal of the hysteresis resistor R.sub.H and its drain terminal is connected to the other terminal of the hysteresis resistor R.sub.H. The gate terminal of the hysteresis pMOSFET 10 is arranged to receive a hysteresis signal 26 as will be described in further detail below. A “refresh node” 28 connected between the first resistor R.sub.1 and the second resistor R.sub.2 is connected to the drain terminal of the second switching nMOSFET 24.

(11) The capacitive divider circuit portion 6 is arranged such that the first capacitor C.sub.1 and the second capacitor C.sub.2 are connected in series such that one terminal of the first capacitor C.sub.1 is connected to the input voltage V.sub.in, the other terminal of the first capacitor C.sub.1 is connected to a first terminal of the second capacitor C.sub.2, and the other terminal of the second capacitor C.sub.2 is connected to ground GND. An output node 30 is connected between the first capacitor C.sub.1 and the second capacitor C.sub.2 and is further connected to the source terminal of the second switching nMOSFET 24. The hysteresis capacitor C.sub.H is connected in parallel with the second capacitor C2 such that a first terminal of the hysteresis capacitor C.sub.H is connected to the output node 30, and the other terminal of the hysteresis capacitor C.sub.H is connected to the drain terminal of the second hysteresis nMOSFET 12. The source terminal of the second hysteresis nMOSFET is connected to ground GND and the gate terminal of the second hysteresis nMOSFET 12 is arranged to receive the hysteresis signal 26.

(12) The switching circuit portion 8 is arranged such that the oscillator 14 produces a reference clock signal having a particular frequency, e.g. 2 kHz, which is input to the one-shot pulse generator 16. The one-shot pulse generator 16 produces a series of relatively short pulses at the frequency set by the oscillator 14. This pulse signal is input to the inverter 18 and the delay circuit 20. The inverter 18 performs a Boolean NOT operation on the pulse signal and applies the inverted pulse signal to the gate terminal of a first switching pMOSFET 22. The non-inverted pulse signal is applied to the gate terminal of the second switching nMOSFET 24 after a predetermined delay as set by the delay circuit 20.

(13) Each time the one-shot pulse generator 16 produces a pulse (i.e. at the frequency set by the oscillator 14), the first switching pMOSFET 22 is forced to conduct for a brief period of time thus enabling the resistive divider circuit portion 4. Assuming that the hysteresis signal 26 is logic low such that the hysteresis pMOSFET 10 is enabled, this allows current to flow from V.sub.in through the first switching pMOSFET 22, the first hysteresis pMOSFET 10, the first resistor R.sub.1, and the second resistor R.sub.2 to ground. As such, the voltage at the refresh node 28 will be

(14) $\frac{R_2}{R_1+R_2}.Math.V_{in}.$

(15) After the duration set by the delay circuit 20 to enable the resistive divider circuit portion to settle, the second switching nMOSFET 24 is also made to conduct. This allows the voltage at the refresh node 28 to be “copied” to the output node 30 within the capacitive divider circuit portion 6. After the pulse has ended, the switching transistors 22, 24 are disabled, thus disconnecting the output node 30 from the refresh node 28 before disabling the resistive divider circuit portion 4. Disconnecting the output node 30 from the refresh node 28 before disabling the resistive divider circuit portion 4 prevents the output node 30 being pulled down when the output of the resistive divider circuit portion 4 falls after being disabled. The output voltage V.sub.out is then provided solely by the capacitive divider circuit portion 6 until the next pulse generated by the one-shot pulse generator 16.

(16) Providing the ratio between the impedance of the first resistor R.sub.1 and the impedance of the second resistor R.sub.2 is substantially equal to the ratio between the impedance of the first capacitor C.sub.1 and the second capacitor C.sub.2, the output voltage V.sub.out, will be the same proportion of the input voltage V.sub.in as would be the case if the resistive divider circuit portion 4 was used alone. Moreover the output voltage V.sub.out can track changes in the input voltage V.sub.in. However, due to the fact that capacitors “block” DC currents, only a negligible amount of current flows through the capacitive divider circuit portion 6 (due to leakage associated with non-ideal capacitors) when compared to the current required by the resistive divider circuit portion 4.

(17) FIG. 2 is a graph showing the output voltage V.sub.out provided by the divider circuit arrangement 2 of FIG. 1 during operation. At a first time t.sub.0, the voltage V.sub.pulse produced by the one-shot pulse generator 16 undergoes a rising edge such that it transitions from logic low to logic high. Due to the inverter 18, the voltage V.sub.enable applied to the gate terminal of the first switching pMOSFET 22 undergoes a falling edge such that it transitions from logic high to logic low.

(18) This enables the resistive divider circuit portion 4 and the voltage V.sub.refresh at the refresh node 28 undergoes a rising edge and thus transitions from 0 V to the value determined by the ratio of the resistances of R.sub.1 and R.sub.2. After a short delay t.sub.delay set by the delay circuit 20, the voltage V.sub.sample applied to the gate terminal of the second switching nMOSFET 24 undergoes a rising edge such that it transitions from logic low to logic high at t.sub.1. This causes the output voltage V.sub.out to begin rising to the value of V.sub.refresh while the capacitors C.sub.1, C.sub.2 (and optionally C.sub.H) are charged.

(19) At a subsequent time t.sub.2, the pulse ends and thus V.sub.pulse drops to logic low. This causes V.sub.sample to return to its former logic low value and, shortly thereafter, V.sub.enable to return to its former logic high value at t.sub.3. This disconnects the output node 30 from the refresh node 28 at t.sub.2 and subsequently disables the resistive divider circuit portion 4 at t.sub.3. After this occurs, the output voltage V.sub.out is provided only by the capacitive divider circuit portion 6 until the next time that V.sub.pulse undergoes a rising edge at t.sub.4.

(20) While in this particular embodiment the output node 30 is connected to the intermittently operated resistive divider circuit portion 4 periodically, arrangements are envisaged in which the output voltage V.sub.out is compared to a reference value and a pulse is applied to refresh the output voltage V.sub.out only if it has dropped by more than a threshold amount.

(21) The hysteresis signal 26 may be applied such that the hysteresis resistor R.sub.H and the hysteresis capacitor C.sub.H are effectively added to or removed from the voltage divider circuit arrangement 2. Providing the values of these are chosen correctly, the impedance ratios associated with the resistive divider circuit portion 4 and the capacitive divider circuit portion 6 may be varied between two distinct values. Specifically, if the hysteresis signal 26 is logic low, the value of the refresh voltage V.sub.refresh will be

(22) $\frac{R_2}{R_1+R_2}.Math.V_{in}$
as described previously, however if the hysteresis signal 26 is logic high, the value of the refresh voltage V.sub.refresh will be

(23) $\frac{R_2}{R_1+R_2+R_H}.Math.V_{in}.$
Similarly, if the hysteresis signal 26 is logic low, the value of the output voltage V.sub.out will be

(24) $\frac{C_1}{C_1+C_2}.Math.V_{in}$
as described previously, however if the hysteresis signal 26 is logic high, the value of the output voltage V.sub.out will be

(25) $\frac{C_1}{C_1+C_2+C_H}.Math.V_{in}.$
If the output voltage V.sub.out is used as an input to a comparator (not shown), it may be advantageous to vary the output voltage V.sub.out between two different values.

(26) As mentioned before, because the impedance ratio associated with the capacitive divider circuit portion 6 is the same as the impedance ratio associated with the resistive divider circuit portion 4, the output voltage V.sub.out will “track” any changes in the input voltage V.sub.in in the same manner that the resistive divider circuit portion 4 would.

(27) FIG. 3 is a circuit diagram of a low-dropout (LDO) voltage regulator 28 that includes the voltage divider circuit arrangement 2 of FIG. 1 in accordance with a further embodiment of the present invention. The LDO 28 comprises: an error amplifier 30; a pass p-channel metal-oxide-semiconductor field-effect-transistor or “pass-FET” 32; and a load including a load capacitor 34 and a load current 36.

(28) The error amplifier 30 is an operational amplifier or “op-amp” that is arranged such that its inverting input is connected to a reference voltage V.sub.ref and its non-inverting input is connected to the output of the voltage divider circuit arrangement 2, referred to in FIG. 3 as a feedback voltage Vfb (i.e. the voltage labelled as the output voltage V.sub.out in FIG. 1). The error amplifier 30 compares the feedback voltage V.sub.fb to the reference voltage V.sub.ref and produces an error voltage V.sub.error that is dependent on the difference between them that is applied to the gate terminal of the pass-FET 32. The error amplifier 30 adjusts the gate-source voltage of the pass-FET 32 in response to the difference between the feedback voltage V.sub.fb and the reference voltage V.sub.ref so as to “top up” the output voltage V.sub.LDO across the load (i.e. across the load capacitor 34) in the manner of a conventional LDO regulator.

(29) The feedback voltage V.sub.fb is derived from the output voltage V.sub.LDO produced by the LDO 28 using the voltage divider circuit 2 which is arranged in the feedback path of the error amplifier 30. In other words, the output voltage V.sub.LDO produced by the LDO 28 is effectively the input voltage V.sub.in provided to the voltage divider 2 as described previously with reference to FIG. 1.

(30) FIG. 4 is a graph showing the voltage V.sub.LDO produced by the low-dropout voltage regulator 28 of FIG. 3. Due to the intermittent “refreshing” of the feedback voltage V.sub.fb (i.e. the voltage taken from the node between C.sub.1 and C.sub.2), the average current consumption of the LDO 28 is reduced compared to a conventional LDO voltage regulator that uses a resistive divider to derive its feedback voltage. Between refreshes, the feedback voltage V.sub.fb will “droop” over time due to leakage of the second switching nMOSFET 24. However, by refreshing the feedback voltage V.sub.fb at a sufficiently high frequency (as set by the frequency of the clock signal CLK produced by the oscillator 14), the amount of “drooping” V.sub.fbdroop of the feedback voltage V.sub.fb can be maintained below a desired amount.

(31) Thus it will be appreciated by those skilled in the art that embodiments of the present invention described herein provide an improved voltage divider circuit arrangement that has a lower average current consumption than conventional voltage divider circuit arrangements known in the art. It will be appreciated by those skilled in the art that the embodiments described herein are merely exemplary and are not limiting on the scope of the invention.